CALIBRATION APPARATUS AND METHOD THEREOF, MULTI-CHANNEL DRIVING CIRCUIT AND CURRENT BALANCING METHOD

Abstract

A calibration method for adjusting an offset voltage of a unit is proposed. The unit, capable of operating in a calibration mode or a normal mode, includes a first input terminal, a second input terminal and an output terminal. The calibration method includes: operating the unit in a calibration mode; providing a programmable voltage to the first input terminal; providing a constant voltage to the second input terminal; adjusting the programmable voltage monotonously when an output status of the output terminal is not changed; latching the programmable voltage when the output status toggles; and operating the unit in a normal mode after the output status toggles.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention is related to a calibration apparatus and method thereof.

2. Description of the Prior Art

Current balance is an important specification for an LED (Light Emitting Diode) driving circuit driving chains of LEDs. In conventional specification, the uniformity for the chains of LEDs is required to be within 1%. However, due to the variation in process parameters during manufacturing, the electronic components of the LED driving circuit may not be able to meet the specification of current balance.

FIG. 1 is a diagram illustrating conventional multi-channel LED driving circuit 100. Using power switch M₁ and booster 11, input voltage V_in is boosted to the voltage level required for driving LED chains 13 and 14. Multi-channel driving circuit 12 is configured to control the channel current of transistors M₃ and M₄ using current driving circuits 15 and 16, respectively. Each of current driving circuits 15 and 16 compares the voltage signal fed back from corresponding resistors R₁ and R₂ with reference voltage V_REF, thereby dynamically controlling the corresponding channel current and further stabilizing the current flowing through resistors R₁ and R₂. Ideally, if the resistance of resistor R₁ equals to that of resistor R₂, the current flowing through LED chains 13 and 14 may be equalized for achieving current balance.

However, error amplifiers OPA₁ and OPA₂ of multi-channel LED driving circuit 100 may not have ideal characteristics. Due to process variations, error amplifiers OPA₁ and OPA₂ may exhibit unmatched offset voltages, the difference between which is likely to hinder multi-channel LED driving circuit 100 from meeting the specification of current balance.

SUMMARY OF THE INVENTION

The present invention provides a calibration method for adjusting an offset voltage of a unit under calibration. The unit under calibration, having a first input terminal, a second input terminal and an output terminal, is configured to operate in a calibration mode or a normal mode. The calibration method includes operating the unit under calibration in the calibration mode, providing a programmable voltage to the first input terminal, providing a constant voltage to the second input terminal, adjusting the programmable voltage monotonously when an output status of the output terminal remains unchanged, latching the programmable voltage when the output status toggles, and operating the unit under calibration in the normal mode after the output status toggles.

The present invention further provides a calibration apparatus for compensating an offset voltage of a comparator which includes a first input terminal, a second input terminal and an output terminal. The calibration apparatus includes a counter configured to adjust a digital signal monotonously, a programmable voltage generating unit configured to generate a programmable voltage on the first terminal according to a first input voltage and the digital signal, and a latch circuit configured to generate a latched digital signal by latching the digital signal when an output status of the output terminal changes, thereby preventing the programmable voltage from being interfered by the counter. A second input voltage is supplied to the second input terminal and the difference between the first and second input voltages is a constant value.

The present invention further provides a multi-channel driving circuit which provides current balancing. The multi-channel driving circuit includes a plurality of current driving circuits each configured to control a corresponding channel current according to a channel current control voltage. Each current driving circuit includes a comparator having a first input terminal, a second input terminal and an output terminal for controlling the corresponding channel current; a latch circuit configured to provide a latched digital signal; and a compensation voltage generator configured to generate a compensation voltage according to the latched digital signal. A sum of the compensation voltage and a first input voltage is supplied to one input terminal among the first and second input terminals. A second input voltage is supplied to the other input terminal among the first and second input terminals. One input voltage among the first and second input voltages corresponds to the channel current. The other input voltage among the first and second input voltages corresponds to the channel current control voltage.

The present invention further provides a current balancing method for driving multiple channels. The current balancing method includes adjusting a digital signal monotonously and, for each corresponding channel, adjusting a compensation voltage according to the digital signal, providing a sum of the compensation voltage and a first input voltage to a first input terminal of a comparator, providing a second input voltage to a second input terminal of the comparator, generating a latched digital signal by latching the digital signal when an output status of an output terminal of the comparator changes, and controlling the comparator according to the latched digital signal, a channel current control voltage and a corresponding feedback voltage for driving the corresponding channel. A difference between the first and second input voltages is a constant value, and the corresponding feedback voltage is associated with a current flowing through the corresponding channel.

These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram illustrating a conventional multi-channel LED driving circuit.

FIG. 2 is a diagram illustrating a multi-channel LED driving circuit according to an embodiment of the present invention.

FIG. 3 is a detailed diagram illustrating a calibration apparatus according to an embodiment of the present invention.

FIG. 4 is a flowchart illustrating a calibration method according to the present invention.

DETAILED DESCRIPTION

FIG. 2 is a diagram illustrating multi-channel LED driving circuit 200 according to an embodiment of the present invention. Multi-channel LED driving circuit 200 also includes booster 11 and LED chains 13 and 14, which may be implemented as depicted in FIG. 1, or may adopt other devices having similar function as well known to those skilled in the art. As shown in FIG. 2, multi-channel LED driving circuit 200 further includes current driving circuits 201 and 202, counter 203 and mode control unit 204. Current driving circuit 201, including calibration circuit 211 and switch S₁, is configured to adjust a unit under calibration (such as error amplifier OPA₃). So is current driving circuit 202. Mode control unit 204 switches driving circuits 201 and 202 to a calibration mode or a normal mode. Since both current driving circuits 201 and 202 operate in the same manner, only the operation of current driving circuit 201 is described in subsequent paragraphs.

In the normal mode when switch S₁ is turned on (short-circuited), calibration circuit 211 may provide level shift to reference voltage V_REF, feedback voltage V₃ (the voltage signal fed from resistor R₃), or both. Calibration circuit 211 converts reference voltage V_REF and feedback voltage V₃ into two input voltages V_i1 and V_i2, based on which error amplifier OPA₃ may control the control terminal of transistor switch M₅, thereby regulating the current flowing through resistor R₃. Therefore, calibration circuit 211 and error amplifier OPA₃ together function as equivalent error amplifier OPA_X, to which reference voltage V_REF and feedback voltage V₃ are supplied as the two input signals. Reference voltage V_REF may be viewed as a channel current control voltage. The amount of constant level shift provided by calibration circuit 211 is determined in the calibration mode.

In the calibration mode, switch S₁ is turned off (open-circuited) . In one embodiment, calibration circuit 211 provides two input voltages V_i1 and V_i2 to error amplifier OPA₃ by commonly shifting reference voltage V_REF. In one embodiment, voltage shift V_shift1, the difference between reference voltage V_REF and input voltages V_i1 varies with the output of counter 203, while voltage shift V_shift2, the difference between reference voltage V_REF and input voltages V_i2, is constant. After entering the calibration mode, output of counter 204 increases or decreases monotonously, and voltage shift V_shift1 provided by calibration circuit 211 increases or decreases with the output of counter 203 accordingly. After the offset voltage of error amplifier OPA_X reaches a predetermined value, output V_TR1 of error amplifier OPA₃ toggles. After then, calibration circuit 211 is configured to latch voltage shift V_shift1 so as to prevent interference associated with the output of counter 203. As counter 203 continues to vary, the voltage shifts of other calibration circuits (such as that of calibration circuit 222) may be adjusted until the voltage shift provided by each calibration circuit has been latched. Latched voltage shift V_shift1 and constant voltage shift V_shift2 may thus be used in the normal mode. Under such circumstance, the voltage shift of the equivalent error amplifier in each current driving circuit may be maintained within a range defined by the same predetermined value, which allows multi-channel LED driving circuit 200 to meet the specification of current balance.

FIG. 3 is a detailed diagram illustrating an embodiment of current driving circuit 201 and related peripheral devices. Compared to ideal error amplifier IOPA₁, non-ideal error amplifier OPA₃ exhibits offset voltage V_OS1 which may occur on any input terminal. For ease of illustration, it is assumed that offset voltage V_OS1 occurs on first input terminal I₁ of error amplifier OPA₃.

In the calibration mode when switch S₁ disconnects non-ideal error amplifier OPA₃ from X₃, reference voltage V_REF is supplied to the control terminal of transistor M₈ via switch S₉, and feedback voltage V₃ (the voltage signal fed from resistor R₃) is isolated from the control terminal of transistor M₈.

Transistor M₈ and adder 305 are configured to shift reference voltage V_REF, thereby generating corresponding input voltage V_i2 (on second input terminal In₂ of error amplifier OPA₃). Voltage shift V_shift2 may be obtained as follows:

V _shift2 =V _th8 +I _f *R _R6 - - -   (1)

In equation (1), V_th8 represents the threshold voltage of transistor M₈, I_f the current flowing through resistor R₆, and R_R6 the resistance of resistor R₆. In this embodiment, voltage shift V_shift2 has a constant value since V_th8, M₈ and I_f are all constants.

Digital-to-analog converter (DAC) 31 is configured to supply analog signal current I (L_D)) to resistor R₅ by selecting one current source or a combination of current sources from current sources I₁-I₅ according to digital signal L_D. Similar to the operation of transistor Mg and adder 305, voltage shift V_shift2 between input voltage V_i1 (on first input terminal IN₁ of error amplifier OPA₃) and reference voltage V_REF may be obtained as follows:

V _shift1 =V _th7 +I(L_D)*R_R5 - - -   (2)

In equation (2), V_th7 represents the threshold voltage of transistor M₇, and R_R5 the resistance of resistor R₅. In this embodiment, input voltage V_i1 is a programmable voltage since the current flowing through resistor R₅ may be programmed according to digital signal L_D.

Upon entering the calibration mode, latch circuit 301 does not function, and digital signals L_D and S_D both increase or decrease monotonously with counter 203. As digital signal L_D varies, voltage shift V_shift1 and input voltage V_i1 also change accordingly. Once the difference between input voltages V_i1 and V_i2 exceeds a specific value, error amplifier OPA₃ changes its output signal V_TR1, which in turn triggers latch circuit 301. When latch circuit 301 is functioning, digital signal L_D is latched at a constant value and no longer varies with digital signal S_D. Therefore, digital signal L_D may be viewed as a latched digital signal.

In the normal mode, digital signal L_D remained latched and is not influenced by output signal V_TR1. Switch S₁ shorts output Out₁ to X₃, and feedback voltage V₃ (the voltage signal fed from resistor R₃) is supplied to the control terminal of transistor M₈ via switch S₉.

In FIG. 3, it is assumed that offset voltage V_os1 of error amplifier OPA₃ is 0.03V, voltage shift V_shift1 is (0.8+L_D*0.001)V, voltage shift V_shift2 is 0.85V, counter 203 outputs 5-bit digital signal (count values between 0 and 32), and reference voltage V_REF is 0.5V.

A calibration method using calibration circuit 211 is provided so that those skilled the art may practice the present invention from the disclosure. FIG. 4 is a flowchart illustrating the calibration method according to the present invention. In FIG. 4, the calibration method begins with step 401, then followed by step 402 in which mode control unit 204 operates switches S₁ and S₉ so that the unit under calibration OPA₃ in current driving circuit 201 operates in a calibration mode.

In step 403, input voltage V_i1 supplied to first terminal In₁ is (V_REF+V_shift1), whose value, (1.3+L_D*0.001)V, may be programmed by digital signal L_D; input voltage V_i2 supplied to second terminal In₂ is (V_REF+V_shift2), which has a constant value of 1.35V. Since the initial value of counter 203 is 0, currently input voltage V_i1 is 1.3V and the voltage difference between the positive and negative input terminals of ideal error amplifier IOPA₁ is −0.02V (=1.3V+0.03V−1.35V), thereby generating logic 0 as output signal V_TR1.

In step 404 when counter 203 is increased monotonously by 1, digital signals S_D and L_D become 1, input voltage V_i1 increases by 0.001V and becomes 1.301V, the voltage difference between the positive and negative input terminals of ideal error amplifier IOPA₁ becomes −0.019V, and output signal V_TR1 remains at logic 0.

In step 405, it is determined whether the status of the output terminal changes. If output signal V_TR1 remains at logic 0, the calibration method goes back to step 404 after step 405 for increasing counter 203 further by 1. Therefore, the voltage difference between the positive and negative input terminals of ideal error amplifier IOPA₁ increases by 0.001V after each time step 404 is executed. After looping back to step 404 subsequent to step 405 several times, digital signal S_D may be increased to 21, and the voltage difference between the positive and negative input terminals of ideal error amplifier IOPA₁ may reach 0.001V. As a result, output signal V_TR1 switches to logic 1. Since the status of the output terminal has been changed, step 406 is executed after step 405 instead of looping back to step 404.

In step 406, latch circuit 301 latches the current value of digital signal L_D (=21) and the states of switches SW₁-SW₅, thereby latching input voltage V_i1 equivalently. After that, digital signal L_D in current driving circuit 201 remains constant even if counter 203 continues to increase. Under such circumstance, voltage shift V_shift1 of current driving circuit 201 is fixed to 0.821V (=0.8+21*0.001), voltage shift V_shift2 is still 0.85V, and the voltage difference between the two input terminals of equivalent error amplifier OPA_x is about 0.001V (=V_shift1+V_os1−V_shift2=0.821+0.03−0.85).

In step 407, mode control unit 204 operates switches SW₁ and SW₉ so that the unit under calibration OPA₃ may return to the same state as those of current driving circuits 15 and 16 in FIG. 1, thereby operating current driving circuit 201 in a normal mode.

The calibration method ends in step 408. When operating a current driving circuit according to the flowchart in FIG. 4, the voltage difference between the two input terminals of the equivalent error amplifier is nearly zero (between 0 and 0.001V), thereby capable of achieving current balance.

In the embodiment illustrated in FIG. 3, the programmable voltage shift is provided to the positive input terminal of error amplifier OPA₃. In another embodiment, the programmable voltage shift may be provided to the negative input terminal of error amplifier OPA₃.

In the embodiment illustrated in FIG. 3, reference voltage V_REF and feedback voltage V₃ are respectively coupled to the positive and negative input terminals of error amplifier OPA₃. In another embodiment, feedback voltage V₃ and reference voltage V_REF may be respectively coupled to the positive and negative input terminals of error amplifier OPA₃.

In the embodiment illustrated in FIG. 3, reference voltage V_REF is supplied to the control terminals of both transistors M₇ and M₈. In another embodiment, two different reference voltages may be supplied to the control terminals of transistors M₇ and M₈ as long as the difference between these two reference voltages remains substantially constant.

Normally, a driving circuit is able to execute a soft-start procedure. When multi-channel LED driving circuit 200 in FIG. 2 executes a soft-start procedure, for example, voltage V_out is gradually raised to the working voltage required for driving LED chains 13 and 14. During the period when the soft-start procedure is executed, LED chains 13 and 14 does not light, and the calibration mode illustrated in FIG. 4 may be operable while executing the soft-start procedure.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.

Claims

1. A calibration method for adjusting an offset voltage of a unit under calibration, wherein the unit under calibration having a first input terminal, a second input terminal and an output terminal is configured to operate in a calibration mode or a normal mode, the calibration method comprising: operating the unit under calibration in the calibration mode;providing a programmable voltage to the first input terminal;providing a constant voltage to the second input terminal;adjusting the programmable voltage monotonously when an output status of the output terminal remains unchanged;latching the programmable voltage when the output status toggles; andoperating the unit under calibration in the normal mode after the output status toggles.

2. The calibration method of claim 1 wherein adjusting the programmable voltage monotonously comprises: providing a digital signal;gradually decreasing or increasing the digital signal; andconverting the digital signal into the programmable voltage.

3. The calibration method of claim 2 wherein latching the programmable voltage comprises: generating a latched digital signal by latching the digital signal so as to prevent the programmable voltage from being interfered by the digital signal.

4. The calibration method of claim 1 further comprising executing a soft-start procedure for raising a supply voltage of a load gradually to a working voltage, wherein the unit under calibration operates in the calibration mode during a period when the soft-start procedure is executed.

5. The calibration method of claim 4 wherein the load comprises a plurality of light-emitting units.

6. A calibration apparatus for compensating an offset voltage of a comparator which includes a first input terminal, a second input terminal and an output terminal, the calibration apparatus comprising: a counter configured to adjust a digital signal monotonously;a programmable voltage generating unit configured to generate a programmable voltage on the first terminal according to a first input voltage and the digital signal; anda latch circuit configured to generate a latched digital signal by latching the digital signal when an output status of the output terminal changes, thereby preventing the programmable voltage from being interfered by the counter;wherein a second input voltage is supplied to the second input terminal and a difference between the first and second input voltages is a constant value.

7. The calibration apparatus of claim 6 wherein the second input voltage equals to the first input voltage.

8. The calibration apparatus of claim 6 wherein the programmable voltage generating unit comprises: a digital-to-analog converter (DAC) configured to generate a corresponding analog signal according to the digital signal; andan adder configured to generate the programmable voltage by summing the corresponding analog signal and the first input voltage.

9. The calibration apparatus of claim 8 wherein the DAC is configured to convert the digital signal into a current signal and the adder includes a resistor through which the current signal flows.

10. A multi-channel driving circuit which provides current balancing, comprising: a plurality of current driving circuits each configured to control a corresponding channel current according to a channel current control voltage, each current driving circuit comprising: a comparator having a first input terminal, a second input terminal and an output terminal for controlling the corresponding channel current;a latch circuit configured to provide a latched digital signal; anda compensation voltage generator configured to generate a compensation voltage according to the latched digital signal, wherein: a sum of the compensation voltage and a first input voltage is supplied to one input terminal among the first and second input terminals;a second input voltage is supplied to the other input terminal among the first and second input terminals;one input voltage among the first and second input voltages corresponds to the channel current; andthe other input voltage among the first and second input voltages corresponds to the channel current control voltage.

11. The multi-channel driving circuit of claim 10 further comprising: a counter configured to adjusting a digital signal monotonously; wherein in each driving circuit when an output status of the output terminal of the comparator changes, the latch circuit generates a latched digital signal by latching the digital signal.

12. The multi-channel driving circuit of claim 10 wherein each driving circuit is configured to drive at least one corresponding light-emitting unit, and comprises: a resistor for detecting a current flowing through the corresponding light-emitting unit.

13. The multi-channel driving circuit of claim 10 wherein the compensation voltage generator comprises: a digital-to-analog converter (DAC) configured to generate a corresponding analog signal according to the digital signal; andan adder configured to generate the compensation voltage by summing the corresponding analog signal and the first input voltage.

14. The multi-channel driving circuit of claim 10 wherein the DAC is configured to convert the digital signal into a current signal and the adder includes a resistor through which the current signal flows.

15. A current balancing method for driving multiple channels, comprising: adjusting a digital signal monotonously; andfor each corresponding channel: adjusting a compensation voltage according to the digital signal;providing a sum of the compensation voltage and a first input voltage to a first input terminal of a comparator;providing a second input voltage to a second input terminal of the comparator, wherein a difference between the first and second input voltages is a constant value;generating a latched digital signal by latching the digital signal when an output status of an output terminal of the comparator changes; andcontrolling the comparator according to the latched digital signal, a channel current control voltage and a corresponding feedback voltage for driving the corresponding channel, wherein the corresponding feedback voltage is associated with a current flowing through the corresponding channel.