CALIBRATION OF IMPAIRMENTS IN A MULTICHANNEL TIME-INTERLEAVED ADC

Abstract

Techniques for correcting component mismatches in an M-channel time-interleaved Analog to Digital Converter (ADC). A number, M, of clock signals drive a corresponding number of main ADC elements with a selected plurality of different clock phases. Each of the ADCs has at least one of an offset correction input, a gain correction input, or a phase correction input. The M digital values output by the ADCs are interleaved to form a digital representation of the input signal. Also provided is a reference ADC that outputs reference digital values in response to at least one of the M clock signals at a time. The output of the reference ADC is compared and/or combined with the output from a selected one of the main ADCs to provide an estimate of offset, gain or phase. The error is accumulated to determine a corresponding correction of offset, gain or phase which is then fed back to the respective input of the corresponding main ADC.

Description

BACKGROUND

An efficient way of providing very high sample rates, rates that cannot be provided by a single Analog-to-Digital Converter (ADC), is to use a parallel connection of slower ADCs operating in a time-interleaved fashion. Such a so-called M-channel time-interleaved ADC (MCTIADC) comprises M ADCs, each operating at a sample rate that is 1/M of the overall system sample rate. In the absence of any impairments or mismatch errors between the ADCs, i.e., assuming all the ADCs are either ideal or have exactly the same characteristics, the output samples appear at equally spaced intervals in a manner that creates a seamless image of a single ADC operating at the system sample frequency.

In practice, however, there are component mismatches between the different ADCs that severely degrade the performance of an MCTIADC system. The commonly occurring mismatches are offset, gain and sample instants. In other words, the offsets and gains of all the ADCs are not the same and the ADCs do not sample at uniform sample instants of the system sample frequency. These mismatches give rise to unnecessary frequency tones or spurs in the spectrum of the signal that significantly reduce the performance of the MCTIADC system.

A typical variation of Signal-to-Noise ratio (SNR) is shown in FIG. 1 wherein a tone is swept from a low frequency to almost half the sample rate of a simulated MCTIADC system for various mismatch errors. As can be seen from the figure, the performance of the four-channel ADC is severely hampered due to these errors. Hence, it becomes imperative to estimate and correct these errors to improve the performance of the MCTIADC system.

SUMMARY

An extra ADC, called the reference ADC, can be used to minimize the effects of offset, gain and sample-time mismatches in an MCTIADC by appropriately estimating and correcting these errors in an adaptive manner. In addition, the adaptive method can be used in a blind mode wherein the use of any particular calibration signal is circumvented. In other words, the input signal itself serves as the calibrating signal to estimate and correct the mismatch errors.

More particularly, in a preferred embodiment, the estimation and correction of offset, gain and timing errors in an M-channel time-interleaved Analog-to-Digital Converter (MCTIADC) is accomplished by using an extra ADC used as a reference ADC. For practical purposes in this embodiment it is assumed that the wordlength of the extra ADC is less than or equal to that of the ADCs in the MCTIADC system.

The concept is based on the model shown in FIG. 2. There are M ADCs, each operating at 1/Mth the sample rate of the MCTIADC system sample frequency. There is a single reference ADC (ADC_r) with a wordlength equal to (R≦N) where N is the wordlength of the ADCs in the MCTIADC. The input to any ADC_k, where k=1, 2, . . . , M, that is being calibrated is also connected to ADC_r. In this way, the estimation and correction of the impairments of ADC_k is performed with respect to the impairments of ADC_r.

In order to obtain the offset error in each ADC_k, the signal that passes through ADC_k is also passed through ADC_r. A total of N_o samples is averaged (or summed) from the outputs of both ADC_k and ADC_r. Call the sum or average of the signals from ADC_k as X_k and the sum or average of the signals from ADC_r as X_r. The sign of the offset error, i.e., sign (X_r−X_k), is used to drive an adaptive algorithm to minimize this error such that the offset value of ADC_k is as close to that of ADC_r. This procedure is repeated for each k where k=1, 2, . . . , M. Thus, the offset errors in all the ADCs in the MCTIADC system will be minimized with respect to that of ADC_r.

For estimating the gain error in each ADC_k, the same configuration as mentioned above is adopted. The outputs of both ADC_k and ADC_r are squared and an average (or sum) of N_g samples is obtained. Let the sum or average of the squared values of the signals from ADC_k be Y_k and that from ADC_r be Y_r. The sign of the gain error, i.e., sign (Y_r−Y_k), is used to drive an adaptive algorithm to minimize this error such that the gain of ADC_k is as close to that of ADC_r. This procedure is repeated for each k where k=1, 2, . . . , M. Thus, the gain errors in all the ADCs in the MCTIADC system will be minimized with respect to the gain error of ADC_r.

In order to obtain the sample-time error in each ADC_k, a correlation between the outputs from ADC_k and ADC_r over N_p samples is first obtained. An adaptive algorithm based on the slope of this correlation is then used to drive the sampling error between ADC_r and ADC_k to a minimum. Again, this procedure is repeated for each k where k=1, 2, . . . , M. Thus, the sample-time errors in all the ADCs in the MCTIADC system will be minimized with respect to the sample-time error of ADC_r.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing will be apparent from the following more particular description of example embodiments of the invention, as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating embodiments of the present invention.

FIG. 1 illustrates Signal to Noise Ratio (SNR) variation with input frequency of a typical prior art four-channel Time-Interleaved Analog-to-Digital Converter for various mismatch errors.

FIG. 2 is a block diagram level model of M-channel Time-interleaved ADC using an extra ADC as reference according to one embodiment.

FIG. 3 illustrates a spectrum of a single tone signal with offset mismatch error before correction in a four-channel time-interleaved ADC.

FIG. 4A is a schematic illustrating how an offset error is estimated.

FIG. 4B is a schematic representing the recursive structure for effecting the offset correction.

FIG. 5 illustrates a spectrum of a single tone signal with offset mismatch error after correction in a four-channel time-interleaved ADC.

FIG. 6 illustrates a spectrum of a single tone signal with gain mismatch error before correction in a four-channel time-interleaved ADC.

FIG. 7A is a schematic illustrating how gain error is estimated.

FIG. 7B is a schematic representing the recursive structure for effecting the gain correction.

FIG. 8 illustrates a spectrum of a single tone signal with gain mismatch error after correction in a four-channel time-interleaved ADC.

FIG. 9 illustrates a spectrum of a single tone signal with phase mismatch error before correction in a four-channel time-interleaved ADC.

FIG. 10A is a schematic illustrating how phase error is estimated.

FIG. 10B is a schematic representing the recursive structure for effecting the phase correction.

FIG. 11 illustrates a spectrum of a single tone signal with phase mismatch error after correction in a four-channel time-interleaved ADC.

FIG. 12 illustrates a spectrum of a single tone signal with offset, gain and phase mismatch errors before correction in a four-channel time-interleaved ADC.

FIG. 13 illustrates a spectrum of a single tone signal with offset, gain and phase mismatch error after correction in a four-channel time-interleaved ADC.

FIG. 14 illustrates a spectrum of a wide-band signal with offset, gain and phase mismatch errors before correction in a four-channel time-interleaved ADC.

FIG. 15 illustrates a spectrum of a wide-band signal with offset, gain and phase mismatch error after correction in a four-channel time-interleaved ADC

FIG. 16 is a high level diagram of a digital receiver that may use the ADC System.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT

A description of example embodiments follows. While the invention is defined solely by the claims presented at the end of this document and therefore may be susceptible to embodiment in different forms, there is shown in the drawings, and will be described herein in detail, one or more specific embodiments, with the understanding that the present disclosure is to be considered but one exemplification of the principles of the invention. It is also to be understood that there is no intent to limit the invention to that which is specifically illustrated and described herein. Therefore, any references to the “invention” which may occur in this document are to be interpreted only as a reference to one particular example embodiment of but one aspect of the invention(s) claimed.

In preferred embodiments, estimation and correction of offset, gain and/or sample is timing or phase mismatch errors is provided in an M-channel Time-Interleaved Analog-to-Digital (MCTIADC) system. Here, the estimation is done in the digital domain while the correction is performed in the analog domain. The various errors are estimated by performing signal processing operations on the outputs of all the ADCs, including a reference ADC, viz., ADC_r, while corresponding correction values are communicated to all the ADCs through Digital-to-Analog Converters (DACs). The DACs provide appropriate voltages or currents and control either directly or indirectly the correction of each of the ADCs for the different mismatch errors.

FIG. 2 shows a high level schematic of an MCTIADC system 100 wherein each “main” ADC 102-1, 102-2, . . . , 102-M is operating at F_S/M sampling rate and clocked at the appropriate phase Φ. The different phases applied to the different ADCs depend on the number, M, of ADCs 102. In a preferred implementation the increment between phases applied to each ADC is 2π/M. For example, if M=4 and the phase applied to a first ADC 102-1 is Ω, then the phases applied to ADC 102-2, 102-3 and 102-4 respectively are Ω+90, Ω+180, and Ω+270 degrees.

The clocking operation is controlled by a distributor circuit 104 which cycles the input signal x(t) through all the ADCs 102 in the MCTIADC system. The input to a chosen one of the “main” ADCs 102, say ADC_k, (102-k) is also input to the “reference” ADC 102-r, i.e, ADC_r. The outputs from ADC_k 102-k and ADC_r 102-r are used to estimate and correct offset, gain and sample-time mismatches of ADC_k. The commutator 108 operates at the sample rate F_S and cycles through the output of every ADC 102-1, 102-2, . . . 102-k, . . . , 102-M to provide the output y(n) at F_S. As can be noted, the commutator 108 performs the opposite function of the distributor 104. Outputs from each ADC 102-1, 102-2, . . . , 102-k, . . . , 102-M, as well as the output from the reference ADC 102-r, are input to a digital signal processor (DSP) 110 in an appropriate manner. The DSP 110 performs the estimation of all the errors and provides signals corresponding to offset, is gain, and phase correction, represented by, O_k, G_k, and P_k that are then fed, respectively, to all the ADCs 102-1, 102-2, . . . , 102-k, . . . , 102-M. These correction values are forwarded to the ADCs though a set of digital to analog connectors (DACs) 112. Below we will describe the estimation of offset, gain, and phase mismatch errors by the DSP 110 using the outputs of each ADC, in conjunction with the output of the reference ADC, and their correction using adaptive algorithms that are performed within the DSP. There is typically a DAC 112 associated with each of the O_k, G_k and P_k correction inputs, for k=1 to m (e.g., there are typically 3 times M DACs 112 in total).

Offset Correction

Due to the different offset values of the ADCs 102, offset spurs show up at kF_S/M frequencies. FIG. 3 shows the spectrum resulting from a simulation of a 110 MHz tone in a four-channel time-interleaved ADC system sampling at 1 GHz where the offset spurs appear at DC, 250 MHz and 500 MHz. As mentioned earlier, the offset spurs occur at multiples of the sample frequency of each ADC, i.e., multiples of 250 MHz, in this case. In order to minimize the amplitude of these spurs, the offsets of each ADC must be determined. The process involved in obtaining the offset mismatch error of each ADC is as follows. The input to a selected ADC_k is also input to the reference ADC 102-r, i.e., ADC_r. The output from both these ADCs (102-k, 102-r) will be different due to different offsets of these two ADCs. At this point it must be mentioned that it is not necessary to reduce the offsets of all the ADCs 102 in the MCTIADC system to zero. It is only important to minimize the difference between the offset of each ADC 102-1, 102-2, . . . , 102-M in the MCTIADC system with respect to the offset of the reference ADC 102-r. In this way, all the ADCs will approximately have the same offset after correction.

Please note that the following discussion details how the various correction values are derived, and uses the pronoun “we” as is typical in discussing mathematical derivations in the plural first person. However, the use of the pronoun “we” herein is not meant to imply that there is more than one inventor of this particular patent.

Towards estimating the offset error of each ADC, we define the average value of the output of ADC_k as

$\begin{array}{cc}{X}_k=\frac{1}{N_o}\sum _{n=0}^{N_o-1}x_k\left(n\right)& \left(1\right)\end{array}$

where x_k(n) represents the samples from ADC_k, and N_o is the number of samples collected to obtain the average X_k and k=1, 2, . . . M. The signal input to ADC_k is also input to ADC_r and consequently we define the average value of the output of ADC_r as

$\begin{array}{cc}{X}_r=\frac{1}{N_o}\sum _{n=0}^{N_o-1}x_R\left(n\right)& \left(2\right)\end{array}$

We define an offset error for ADC_k as

E _k ^offset =X _r −X _k  (3)

for k=1, 2, . . . M.

Such an offset error may be estimated by the circuit shown in FIG. 4A. A selector 120 chooses which one of the M ADC outputs is ADC_k at any point in time. The selected ADC_k is then subtracted 122 from ADC_r 102-r to obtain a difference. The difference is then accumulated by summer 124 and delay 126 over N_o samples to obtain E_k^offset. The accumulation is then reset by other circuitry (not shown) to obtain the next estimate of E_k^offset.

It should be noted that the division by N_o operation specified in the above equations and not shown in FIG. 4A is not necessary. This is because, as will be understood, it is really only the sign of the result that is used for the correction.

We now provide an adaptive algorithm to correct the offset error in each ADC_k based on E_k^offset, for k=1, 2, . . . M. One implementation of the algorithm is shown in FIG. 4B.

By way of introduction, let ODAC_k be the DAC 112-O-k (FIG. 2) that provides the offset correction to ADC_k. Let R_O be the range of ODAC_k. For example, for an 8-bit ODAC_k, R_O=2⁸=256. A step size that controls the convergence of the adaptive algorithm is denoted by μ_kⁱ for ADC_k at the ith iteration. The value of μ_kⁱ is constrained to be in the range [μ_k^offsetmin, μ_k^offsetmax]. Let O_kⁱ be the value input to the ODAC_k. For example, for an 8-bit ODAC_k, the values of O_kⁱ can vary between [−128, 127] or between [0, 255]. The constant O_bias is a value that allows the correction to be done with respect to a certain bias. For instance, O_bias=R_O/2=128 when the input to the ODAC_k lies in the range [0, 255]. On the other hand when the range of the ODAC_k input values is in [−128, 127], O_bias can assume a value of zero. Let a_kⁱ denote a variable that provides correction to the ODAC_k input O_kⁱ associated with ADC_k at the ith iteration. We can now write the adaptive algorithm for offset correction as

$\begin{array}{cc}{O}_k^i=O_{\mathrm{bias}}+\mathrm{round}\left({\alpha }_k^i\right)& \left(4\right)\\ {\alpha }_k^{i+1}={\alpha }_k^i+\mathrm{sign}\left(E_k^{\mathrm{offset}}\right){\mu }_k^i& \left(5\right)\\ {\mu }_k^{i+1}=\max \left(\frac{{\mu }_k^i}{2},{\mu }_k^{\mathrm{offsetmin}}\right)\mathrm{for}i=r_k& \left(6\right)\end{array}$

where a_k⁰=0, μ_k⁰=μ_k^offsetmax, and r_k is any arbitrary positive number. The convergence can be controlled by μ_kⁱ by changing its value at every r_kth iteration.

In FIG. 4B, a schematic for adaptive algorithm performing offset correction is depicted. The sign 401 of each E_k^offset is multiplied 402 by the adaptation step-size and accumulated by summer 404 and delay 405. The accumulated value in each iteration is rounded 406 to the nearest integer value and added 408 to the offset bias, O_bias, to provide the offset correction value O_kⁱ to the ODAC_k. The output from ODAC_k 112-o-k directly or indirectly controls the offset setting on ADC_k, as depicted in FIG. 2. Such an adaptive process converges to an optimal value that minimizes the offset in ADC_k with respect to that in ADC_r.

FIG. 5 shows the spectrum of the simulated tone mentioned in FIG. 3 after correction. As can be seen from the figure, the offset spurs at 250 MHz and 500 MHz are significantly reduced. In this simulation, it must be mentioned that the word length of each ADC_k is 14 bits while that of ADC_r is 10 bits.

Gain Correction

Gain differences in the ADCs 102-1, 102-2, . . . , 102-k, . . . , 102-M produce gain spurs at +F_in+kF_S/M frequencies, where F_in, is the set of input frequencies and k=1, 2, . . . , M. FIG. 6 shows the simulated spectrum of a simulated 110 MHz tone in a four-channel time-interleaved ADC sampling at 1 GHz where the gain spurs appear at 140 MHz, 360 MHz and 390 MHz. In order to minimize the amplitude of these spurs, the power of the signals from each ADC 102-1, 102-2, . . . , 102-k, . . . , 102-M must be determined and compared with that of the reference ADC. Again, as in the case of the offset mismatch estimation, the input to ADC_k is also passed through ADC_r. The output from both these ADCs will be different due to differences in the gain of the two ADCs (ADC_k and ADC_r). In the process of minimizing the difference in the gains between the different ADCs, we compare the gain of each ADC_k with that of ADC, and use an adaptive algorithm to minimize the difference. In this way, all the ADCs will eventually be adjusted to have approximately the same gain.

Towards minimizing the difference in gains of all the ADCs, we define

$\begin{array}{cc}{Y}_k=\frac{1}{N_g}\sum _{n=0}^{N_g-1}x_k^2\left(n\right)& \left(7\right)\end{array}$

where x_k(n) represents the samples from ADC_k, N_g is the number of samples collected to obtain Y_k, and k=1, 2, . . . M. Since the same input is passed through ADC_r, we define

$\begin{array}{cc}{Y}_r=\frac{1}{N_g}\sum _{n=0}^{N_g-1}x_r^2\left(n\right)& \left(8\right)\end{array}$

We now define a gain error for each ADC_k as

E _k ^gain =Y _r −Y _k  (9)

for k=1, 2, . . . M.

Below we outline an adaptive algorithm to correct the gain error in each ADC_k based on E_k^gain, for k=1, 2, . . . M.

A flow diagram of one implementation to determine E_k^gain is shown in FIG. 7A. This implementation takes advantage of the fact that the difference of the sum of the squares as specified by equations (7)(8) and (9) can be determined by taking the squares first and then the difference. Selector 140 chooses one of the ADC outputs as ADC_k which is then squared 142. The output of ADC_k is then squared at 144. The difference of the squares is determined by subtractor 146 and then accumulated by summer 147 and delay 148. The accumulated output provides E_k^gain. As for the gain determination, the division by N_g is not necessary in this implementation since only the sign of the result is used for the correction.

Once the gain error has been determined, the next step is to determine an amount of the correction. Referring back to FIG. 2, let GDAC_k be the DAC 112-G-k that provides the gain correction to ADC_k. Let R_G be the range of the GDAC_k. A step size that controls the convergence of the adaptive algorithm associated with gain correction is denoted by v_kⁱ for ADC_k at the ith iteration. The value of v_kⁱ lies in the range [v_k^offsetmin, v_k^offsetmax]. Let G_kⁱ be the value input to the GDAC_k. Again, the values of G_kⁱ can vary between [−128, 127] or between [0, 255] if R_G=256. The constant G_bias is a value that allows the correction to be done with respect to a certain bias. For the case when G_bias=R_G/2=128, the input to the GDAC_k lies in the range [0, 255]. On the other hand, when the range of the GDAC_k input values is in [−128, 127], G_bias=0. Let β_kⁱ denote a variable that provides correction to the GDAC_k input G_kⁱ associated with ADC_k at the ith iteration. We can now write the adaptive algorithm for gain correction as

$\begin{array}{cc}{G}_k^i=G_{\mathrm{bias}}+\mathrm{round}\left({\beta }_k^i\right)& \left(10\right)\\ {\beta }_k^{i+1}={\beta }_k^i+\mathrm{sign}\left(E_k^{\mathrm{gain}}\right)v_k^i& \left(11\right)\\ v_k^{i+1}=\max \left(\frac{v_k^i}{2},v_k^{\mathrm{gainmin}}\right)\mathrm{for}i=s_k& \left(12\right)\end{array}$

where β_k⁰=0, v_k⁰=v_k^gainmax, and s_k is any arbitrary positive number. The convergence can be controlled by v_kⁱ by changing its value at every s_kth iteration.

In FIG. 7B, a schematic for an adaptive algorithm to perform the gain correction is shown. The sign 700 of each E_k^gain is multiplied 702 by the adaptation step-size and accumulated 704, 706. The accumulated value in each iteration is rounded 708 to the nearest integer value and added 710 to the gain bias, G_bias, to provide the gain correction value to GDAC_k 112-G-k. The output of GDAC_k directly or indirectly controls the gain setting on the selected ADC_k. The above adaptive process converges to an optimal value that minimizes the gain error in each ADC_k.

FIG. 8 shows the spectrum of the simulated tone mentioned in FIG. 6 after gain mismatch correction. As can be seen from the figure, the gain spurs at 140 MHz, 360 MHz and 390 MHz have been minimized. Just as in the simulation for offset mismatch estimation and correction, the wordlength of each ADC_k is 14 bits while that of ADC, is 10 bits.

Phase Correction

Since all the ADCs 102-1, 102-2, . . . , 102-k, . . . , 102-M do not have uniform sample instants in reference to the sampling frequency of the MCTIADC, timing or phase spurs show up at the same frequencies as those due to gain errors. The one difference is that gain spurs are orthogonal to the phase spurs. Additionally, as can be seen from FIG. 1, the spur is dependent on the frequency of the input signal. FIG. 9 shows the simulation spectrum of a 110 MHz tone in a four-channel time-interleaved ADC sampling at 1 GHz with phase spurs. As can be seen, the phase spurs occur at the same frequencies as those shown in FIG. 6. In order to minimize the amplitude of these spurs, the phase of each ADC_k 102-1, 102-2, . . . , 102-k, . . . , 102-M is compared with the phase of ADC_r 102-r and the difference is minimized. As in the case of offset and gain, the input to a selected ADC_k is also input to the reference ADC, i.e., ADC_r. The concept of minimizing the difference in the sample timings of these two ADCs will be explained below.

Let us define

$\begin{array}{cc}{Z}_k=\frac{1}{N_p}\sum _{n=0}^{N_p-1}{\left(x_r\left(n\right)-x_k\left(n\right)\right)}^2& \left(13\right)\end{array}$

where N_p is the number of samples collected to obtain the average Z_k, and k=1, 2, . . . M. It is observed that the variation of Z_k with phase follows a quadratic curve. Consequently, the minimum of Z_k is obtained as the minimum of the quadratic curve. Towards this end, we define a phase error for ADC_k as

$\begin{array}{cc}{E}_k^{\mathrm{phase}}=\frac{1}{N_p}\sum _{n=1}^{N_p-1}\left(x_r\left(n\right)-x_k\left(n\right)\right)\left(x_k\left(n\right)-x_k\left(n-1\right)\right)& \left(14\right)\end{array}$

which is obtained by differentiating Z_k from Eqn. (13).

FIG. 10A is a flow diagram illustrating how the phase error can be determined in one implementation. The ADC_k output by selector 170 is subtracted from ADC_r at 172. ADC_k is also fed to delay 174 and subtractor 176. The outputs of subtractor 176 and difference 172 are multiplied by each other and then accumulated by summer 178 and delay 179. The result provides E_k^phase. As with the offset and gain error measurement, only the sign of the result will be used, so division by N_p is not necessary in the practical embodiment shown.

We now provide an adaptive algorithm to correct the phase error in each ADC_k based on the determined E_k^phase, for k=1, 2, . . . M.

Let PDAC_k be the DAC 112-P-k that provides the timing or phase correction to ADC_k. Let R_P be the range of the PDAC_k. A step size that controls the convergence of the adaptive algorithm associated with phase correction is denoted by ξ_kⁱ for ADC_k at the ith iteration. The value of ξ_kⁱ is constrained to be in the range [ξ_k^phasemin, ξ_k^phasemax]. Let P_kⁱ be the value input to the PDAC_k. The values of P_kⁱ can vary between [−128, 127] or between [0, 255] if R_P=256. The constant P_bias is a value that allows the correction to be done with respect to a certain bias. For the case when P_bias=R_P/2=128, the input to the PDAC_k lies in the range [0, 255]. On the other hand, when the range of the PDAC_k input values is in [−128, 127], P_bias=0. Let γ_kⁱ denote a variable that provides correction to the PDAC_k input P_kⁱ associated with ADC_k at the ith iteration. We can now write the adaptive algorithm for phase correction as

$\begin{array}{cc}{P}_k^i=P_{\mathrm{bias}}+\mathrm{round}\left({\gamma }_k^i\right)& \left(15\right)\\ {\gamma }_k^{i+1}={\gamma }_k^i+\mathrm{sign}\left(E_k^{\mathrm{phase}}\right){\xi }_k^i& \left(16\right)\\ {\xi }_k^{i+1}=\max \left(\frac{{\xi }_k^i}{2},{\xi }_k^{\mathrm{phasemin}}\right)\mathrm{for}i=t_k& \left(17\right)\end{array}$

where γ_k⁰=0, ξ_k⁰=ξ_k^phasemax, and t_k is any arbitrary positive number. The convergence of the adaptive algorithm is controlled ξ_kⁱ by changing its value at every t_kth iteration.

In FIG. 10B, a schematic for adaptive algorithm performing phase correction is shown. The sign 1000 of each E_k^phase is multiplied 1001 by the adaptation step-size and accumulated (1002, 1004). The accumulated value in each iteration is rounded 1006 to the nearest integer value and added 1010 to the phase bias, P_bias, to provide the phase correction value to PDAC_k 112-P-K. The output from PDAC_k directly or indirectly controls the phase setting on ADC_k.

FIG. 11 shows the simulated spectrum of the tone mentioned in FIG. 9 after phase correction. As can be seen from the figure, the phase spurs at 140 MHz, 360 MHz and 390 MHz have been minimized. Again, the word length of each ADC_k is 14 bits while that of ADC_r is 10 bits.

So far we have described the adaptive algorithms pertaining to specific mismatch errors. In the presence of all the mismatches, viz., offset, gain and phase mismatches, the adaptive algorithms are either run in a round-robin manner, starting with offset, then gain and then phase, for each ADC_k or in a parallel fashion where all the mismatches are estimated and corrected simultaneously, or some sort of hybrid approach, where all of the adjustments for a given ADC_k are determined and corrected simultaneously, or all m offsets, then gain, then phase are determined simultaneously, etc.

FIG. 12 shows the spectrum of a simulated tone with all the mismatch errors while FIG. 13 shows the spectrum after all mismatch errors have been minimized. As can be seen from the figure, the offset spurs at 250 MHz and 500 MHz, as well as gain and phase spurs at 140 MHz, 360 MHz and 390 MHz have been minimized.

The adaptive algorithms described thus far have shown to work for the case when the input is a single tone. It can be shown that the same set of algorithms will work for the case when the input signal is a wide-band. FIG. 14 shows the spectrum of a simulated wide-band signal comprised of many sinusoids in presence of offset, gain and phase mismatch errors In this simulation, we have chosen a signal with 100 tones between zero and F_S/8 and another 100 tones between 3F_S/8 to F_S/2 so as to visualize the offset, gain and phase mismatch spurs populating the spectrum between F_S/8 to 3F_S/8. It can be seen from FIG. 15 that mismatch spurs have been significantly minimized.

High sample rate, time interleaved ADCs such as that described above can find application in many different types of systems. One such application is in a digital radio receiver. Such receivers have historically used analog tuner devices to demodulate a small portion of the input signal spectrum down to a low frequency. Relatively speaking, the tuner output has a low center frequency and low total bandwidth, thus allowing a low speed analog-to-digital converter to be used to digitize the data. Using high speed ADC systems 100, the total bandwidth can be increased while retaining the flexibility of digital systems.

One particular use of the ADC system 100 is to implement a digital radio receiver as generally shown in FIG. 16. A radio frequency (RF) signal is fed to a radio frequency RF amplifier 504. In a wireless application, the RF signal may be received from an antenna 502; in other applications such as a cable modem, it may be received via a wire. The amplified RF signal is then fed to an RF translator 506 to down-convert the amplified RF signal to an intermediate frequency (IF). After the RF translator 506 (which may be optional) the ADC 510 (which may be implemented as the ADC system 100 described above) is then used to digitize the RF input into digital samples for subsequent processing. A digital local oscillator 511 may operate digital mixers 512-i and 512-q to provide for in phase and quadrature samples thereof. A digital low pass filter 520 limits the frequency content of resulting signal to the desired bandwidth. A demodulator 530 then recovers the original modulated signal from the same using. One or more of the operations of the digital local oscillator 511, mixers 512, low pass filter 520 and/or demodulator 530 may be implemented in a digital signal processor (DSP) 550. The recovered signal may then be further processed converted back to an analog baseband signal or the like, depending on the specific end use for the digital receiver.

While this invention has been particularly shown and described with references to example embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the invention encompassed by the appended claims.

Claims

1. An apparatus comprising: a clock signal generator, for generating a plurality, M, of clock signals with at least some of clock signals having a different one of a selected plurality of clock phases offset by an amount determined by M;a plurality, M, of Analog to Digital Converters (ADCs) coupled to the clock signal generator, the ADCs for converting an input signal to a set of ADC outputs as M digital values in response to a respective one of the M clock signals, each of the ADCs having at least one of an offset correction input, a gain correction input, or a phase correction input;a multiplexer, for interleaving the M digital values output by the ADCs to form a digital representation of the input signal;at least one reference ADC coupled to the clock signal generator and the is input signal, and to output a reference digital value in response to at least one of the M clock signals; andan adaptive processor, for estimating at least one of an offset, gain or phase error in at least one of the ADCs, and generating one or more correction signals in response thereto by: selecting at least one of the M digital values as a selected digital value;comparing the selected digital value and the reference value to produce a comparison result;determining an error estimate by accumulation of the comparison result over a predetermined number of samples of the selected digital value and the reference value;from the error estimate, determining at least one of an offset, gain or phase correction value corresponding to one or more estimated correction signals; andthe estimated correction signals connected to at least a corresponding one of the offset, gain, or phase correction inputs of the ADCs.

2. The apparatus of claim 1 wherein the adaptive processor determines an offset error estimate from a difference between an average of the selected digital values and an average of the accumulated reference values.

3. The apparatus of claim 1 wherein the adaptive processor determines a gain error estimate from a difference of squares of the selected digital value and the reference value.

4. The apparatus of claim 1 wherein the adaptive processor determines a phase error estimate from a difference between the selected digital values and the reference values, as well as from a difference between two consecutive samples of the selected digital values, prior to the accumulation.

5. The apparatus of claim 1 additionally comprising: one or more Digital to Analog Converters (DACs), connected to receive at least one of the offset, gain, or phase correction values, and to produce an analog correction signal to be applied to a selected one of the M ADCs.

6. The apparatus of claim 5 additionally comprising: a plurality of DACs, with M of the DACs associated with each of an offset, gain, or phase correction input to each one of the M ADCs.

7. The apparatus of claim 1 wherein the adaptive processor further determines offset, gain, and phase corrections individually one at a time for each of the M ADCs, and a single reference ADC, ADCr, provides the reference values for correcting one of the offset, gain, and phase for a given one, ADCk, of the M ADCs at a given time.

8. The apparatus of claim 1 wherein a plurality of reference ADCs provide two or more reference values to enable corrections of offset, gain, and phase for two or more of the M ADCs at a given time.

9. The apparatus of claim 1 wherein the adaptive processor corrects for offset error and further determines an offset error for ADCk as

10. The apparatus of claim 1 wherein the adaptive processor corrects for gain error and further determines a gain error for each ADCk as

11. The apparatus of claim 1 wherein the adaptive processor corrects for phase error and further determines a phase error for ADCk as

12. The apparatus of claim 1 implemented in a receiver for a communication system.

13. A method comprising: generating a plurality, M, of clock signals, with at least some of clock signals having a different one of a selected plurality of clock phases, where a is phase difference between selected clock phases depends on a value of M;converting an input signal with a plurality, M, of Analog to Digital Converters (ADCs) coupled to the M clock signals, to provide to a set of ADC outputs as M digital signals, each of the ADCs having at least one of an offset correction input, a gain correction input, or a phase correction input;interleaving the M digital values output by the ADCs to form a digital representation of the input signal;converting the input signal with a reference ADC to output reference digital values in response to at least one of the M clock signals; andestimating one or more correction signals for at least one of offset, gain, and phase error in at least one of the ADCs by: determining a set of selected digital values from one of the M digital signals over a predetermined number of ADC output samples;determining a set of reference values over a predetermined number of ADC output samples;comparing the set of selected digital values and the set of reference values, to produce a comparison result;accumulating the comparison result to provide an error estimate; andfrom the error estimate, determining at least one of an offset, gain or phase correction corresponding to one or more correction signals to be applied to correct at least one of offset, gain, or phase error of at least one of the ADCs.

14. The method of claim 13 further comprising: estimating an offset error from a difference between an average of the accumulated digital values and an average of the accumulated reference values.

15. The method of claim 13 further comprising: estimating a gain error from a difference of squares of a digital value and at least one reference value.

16. The method of claim 13 further comprising: estimating a phase error from a difference between the digital values and the reference values as well as from a difference between two consecutive samples of the selected digital values.

17. The method of claim 13 additionally comprising: Digital to Analog Converting at least one of the offset, gain, or phase correction values to provide an analog correction signal, andproviding the corresponding analog correction signal to a selected one of the correction inputs of the ADCs.

18. The method of claim 17 additionally comprising: providing a plurality of offset, gain, or phase correction input to each one of the correction inputs of the M ADCs.

19. The method of claim 13 additionally comprising: individually determining offset, gain, and phase corrections for each of the ADCs using a single reference ADC, ADCr, to determine a signal to be fed to one of the offset, gain, or phase correction input of a given one, ADCk, of the ADCs at a given instant in time.

20. The method of claim 13 additionally comprising: providing a plurality of reference signals to two or more offset, gain, and phase correction inputs of two or more of the ADCs at a given time.

21. The method of claim 13 additionally comprising correcting for offset error by: determining an offset error for ADCk as

22. The method of claim 13 additionally comprising correcting for gain error by: determining a gain error for each ADCk as

23. The method of claim 13 additionally comprising correcting for phase error by: determining a phase error for ADCk as

24. The method of claim 13 used as part of a communication signal receiving process.

25. A system comprising: a radio frequency amplifier, for receiving an input radio frequency signal;a translator, for down converting the input radio frequency signal to a received signal;an M-channel time-interleaved analog to digital converter (MCTIADC) connected to the received signal and to provide a digitized received signal, the MCTIADC further comprising: a plurality, M, of Analog to Digital Converters (ADCs) for converting the received signal to a set of ADC outputs as M digital values, each of the ADCs having at least one of an offset correction input, a gain correction input, or a phase correction input;a multiplexer, for interleaving the M digital values output by the ADCs to provide the digitized received signal;at least one reference ADC coupled to the received signal, and to output a reference digital value; andan adaptive processor, for estimating at least one of an offset, gain or phase error in at least one of the ADCs from the set of ADC outputs and the reference digital value, and generating one or more correction signals to be applied to one of the offset, gain, or phase correction inputs of at least one of the ADCs; anda digital demodulator, connected to the digitized received signal, and to provide a digital demodulated signal.