CALIBRATION STRATEGY FOR REDUCED INTERMODULATION DISTORTION

Abstract

The present disclosure relates to a circuit and method for reducing intermodulation distortion in a non-linear device having a differential output stage. A calibration circuit is provided for adding a calibration offset voltage to at least one of one output branch of the differential output stage and a bulk terminal of a transistor of one output branch of the differential output stage to obtain a desired output offset at the differential output stage. Thereby, a certain degree of asymmetry is introduced so that both output branches of the differential output stage are matched or optimized to improve the IIP2 factor and reduce intermodulation distortions.

Description

BACKGROUND

1. Technical Field

The present disclosure generally relates to a circuit and method for reducing the 2^nd order intermodulation distortion in a non-linear device having a differential output stage. In particular, the present disclosure relates to a trimming strategy for improving an intermodulation intercept point second order (IIP2) in an active or passive mixer.

2. Description of the Related Art

When a carrier signal or the like is modulated by or mixed with another signal of different frequency, non-linearity of the respective processing device, e.g., mixer, causes undesired output frequencies that are different from the input frequencies. Namely, when input signals having two or more frequencies are mixed together, distortion is produced, i.e., intermodulation distortion (IMD) having additional undesired frequencies. In the case of second order distortions, the frequencies of intermodulation components correspond to the sum of the two input frequencies and the difference between the two input frequencies. Thus, when two input signals having two different input frequencies are applied to the non-linear device, the intermodulation distortion product IM2 occurs at the difference frequency of two test tones.

The signal strength of two test tones outputTestTones[dBV] and the unwanted product IM2[dBV] can be measured at the output of a DUT (Device Under Test). Additionally it is known which power of test tones pwrINPUT[dBm] is applied at the DUT.

Further, the term losses[dB] represents the attenuation of test tones by the DUT. With this data the second order Input Intersept Point IIP2 of the DUT is defined as follows.

IIP2[dBm]=outputTestTones[dBV]−IM2[dBV]+pwrINPUT[dBm]+losses[dB]

This value IIP2 remains constant over a wide range of applied input power.

The IIP2 is an important parameter used to characterize a radio frequency (RF) communication system and represents a special kind of non-linearity of the communication system. The value of the intercept point decreases with increased non-linearity of the system and vice versa. IIP2 is high if the symmetry of a system is good. A very nonlinear system with high symmetry may have a good IIP2. A further expression characterizes the linearity. It is called IIP3. The IIP3 is not regarded and not needed for the parameter IIP2.

For a mixer in a receiver, a high IIP2 is required. An IIP2 calibration or trimming circuit for adjusting the IIP2 is necessary.

In M. Hotti et al., “An IIP2 Calibration Technique for Direct Conversion Receivers”, ISCAS 2004, IEEE, pages IV-257 to 260, an improvement for a IIP2 calibration method for a Gilbert cell type mixer is described. A high IIP2 is maintained over the entire base band channel in wide band systems, while detection of a correct trimming code is provided to implement an on-chip tuning engine. The criteria for trimming are the DC voltage steps at the mixer output caused by a signal from the transmitter. However, an ideal trimming is not possible due to the poor accuracy of measuring the DC steps. Moreover, the proposed solution leads to a significant loss of DC headroom, while a change of DC headroom contributes a lot to IIP2 trimming.

Additionally, S. Zhou et al., “A CMOS Passive Mixer with Low Flicker Noise for Low-Power Direct-Conversion Receiver”, IEEE, Solid-State Circuits, VOL. 40; No. 5; May 2005 discloses an IIP2 trimming circuit for passive mixers, where DC offset at mixer gates is trimmed for best IIP2. However, a very complex circuitry is required to provide the desired trimming capability.

Furthermore, chopper stabilization of IIP2 is suggested in E. Bautista, “A High IIP2 Down Conversion Mixer Using Dynamic Matching”, IEEE, Solid-State Circuits; VOL. 35, No. 12; December 2000. However, the chopper frequency introduces the risk of spurious responses.

In addition thereto, published US Patent Application 2005/0143044 A1 discloses a circuit for calibrating IIP2 and for reducing second order intermodulation, which includes a common mode feedback circuit and a load impedance operatively connected between first and second output terminals of a mixer in a direct conversion receiver. The common mode feedback circuit reduces second order intermodulation of the mixer by detecting an output voltage of the mixer and adjusting a gain of the mixer. The IIP2 is controlled by controlling the gain of the common mode feedback circuit. Common-mode signal parts are used for IIP2 calibration.

BRIEF SUMMARY

The present disclosure provides a calibration or trimming circuit and method, which are suitable for low voltage, high frequency applications.

A circuit for reducing intermodulation distortion in a nonlinear device having a differential output stage is provided, the circuit includes an offset voltage circuit that outputs a calibration offset voltage, and a calibration circuit coupled to the offset voltage circuit to add the calibration offset voltage to at least one of one output branch of the differential output stage and a bulk terminal of a transistor of one output branch of the differential output stage to obtain a desired output offset at the differential output stage.

In accordance with another embodiment of the present disclosure, a method for reducing intermodulation distortion in a non-linear device having a differential output stage is provided, the method including the steps of generating a calibration offset voltage, and adding said calibration offset voltage to at least one of one output branch of the differential output stage and a bulk terminal of a transistor of one output branch of the differential output stage to obtain an output offset at the differential output stage.

In accordance with another embodiment of the present disclosure, a circuit is provided, the circuit including an active mixer having a differential output circuit with first and second output branches, and a trimming circuit coupled to the mixer. The trimming circuit applies a first offset voltage to either one of a bulk terminal of a transistor of a first branch of the differential output circuit or to an output of the first branch of the differential output circuit or to both the bulk terminal and the output of the first branch of the differential output circuit. The trimming circuit also obtains the first offset voltage from one of a memory circuit or a detecting circuit that detects an offset voltage at the output of the differential output circuit, the first offset voltage leading to an asymmetry between the first and second branches of the differential output circuit to minimize second order intermode distortion and trimming the intermodulation intercept point second order.

In accordance with another embodiment of the present disclosure, a circuit is provided that includes a passive mixer circuit having a plurality of transistors in an output circuit thereof, and a trimming circuit coupled to the plurality of transistors in the passive mixer circuit and structured to supply an offset voltage that comprises an average bulk voltage applied to a bulk terminal of all of the plurality of transistors and a compensation offset voltage that is applied at the bulk terminal of one of the plurality of transistors to compensate for errors caused by an offset threshold voltage.

In the circuit, IIP2 is trimmed by introducing an asymmetry of a transistor pair, e.g., through a bulk voltage asymmetry. This is applicable to active and to passive mixers. Active mixers need a DC supply current with a voltage drop at transistors, passive mixers do not. Transistors in passive mixers are ohmic switches only. IIP2 in passive mixers depends on symmetry at On- and OFF-resistances and on symmetry of the load impedance. For active mixers there is additionally the need for symmetry of voltages at the transistors, e.g., between drain and source. This requirement is also used in the present disclosure for the option to trim IIP2 by trimmed differences at supply voltages for a transistor pair from an active mixer. Different voltages at a transistor pair change the symmetry as well. The present disclosure can be applied to single-balanced mixers or to double-balanced mixers or in simple symmetrical active gain stages.

Accordingly, by adding a calibration offset voltage to the output branch or applying it to a bulk terminal of a transistor connected to the output branch, a certain degree of asymmetry is introduced in a simple manner, so that both output branches of the differential output stage are matched or optimized to improve the IIP2 factor and reduce intermodulation distortions.

The calibration offset voltage may be obtained in different manners, reflecting different aspects of the present disclosure.

According to a first aspect, a memory or computer readable medium may be provided for storing a plurality of offset voltage values of the differential output branch, wherein the circuit is adapted to select as the calibration offset voltage an offset voltage value that is associated with a minimum value of the related output values. As an example, the related output values may correspond to second order intermodulation products. Thereby, an easy solution to the above problem can be provided, wherein second order intermodulation (IM2) results are stored for different offset voltage values, e.g., during manufacturing of the circuit. Then, during application, the stored offset voltage value that led to the minimum IM2 result is applied.

According to a second aspect, the offset voltage at an output of the differential output stage is detected and used for generating the calibration offset voltage. In the second aspect, a value of a desired offset voltage may be stored, and the calibration offset voltage is generated at a value required to obtain the stored value at the output of the differential output stage.

According to a third aspect, a value of the calibration offset voltage, that may have been determined during circuit evaluation, is stored, and—during circuit application—the calibration offset voltage is generated at a value corresponding to the stored value. This solution is preferable for passive mixers or other passive circuits, where no DC current is provided in the switches of the output branches. Moreover, this solution is feasible if large transistors are used in mixers with low power.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

The embodiments of the present disclosure will now be described based on preferred embodiments with reference to the accompanying drawings in which:

FIG. 1 shows a schematic block diagram of a calibration circuit according to the preferred embodiments;

FIG. 2 shows a schematic circuit diagram of an active mixer with IIP2 calibration according to a first preferred embodiment;

FIG. 3 shows a schematic circuit diagram of a passive mixer circuit with IIP2 calibration according to a second preferred embodiment;

FIG. 4 shows a diagram indicating IIP2 values vs. bulk voltage values for a passive mixer;

FIG. 5 shows a diagram indicating IIP2 trimming by bulk offset voltage;

FIG. 6 shows a flow diagram of a calibration method; and

FIG. 7 shows a schematic circuit diagram of a mixer circuit with IIP2 calibration according to a third preferred embodiment.

DETAILED DESCRIPTION

In the following, the preferred embodiments are described on the basis of mixer circuits with differential output stage, such as a double balanced mixer.

Second order distortion in the mixer produces a static DC offset at the output of the mixer as well as local oscillator (LO) self-mixing. Therefore, by minimizing the change in the DC offset, it is possible to detect the correct trimming or calibration state. However, it is noted that the DC offset at the mixer output is a cumulative offset comprising static DC offset due to self-mixing and device mismatch. Therefore, optimum calibration is achieved when the DC offset caused by the second order intermodulation distortion is minimized. The typical DC offset from LO self-mixing is 60 dB larger than the DC offset from IIP2. Only DC offsets and possible DC offset steps must be kept small that are caused at cases of bad IIP2. A constant DC offset in no problem.

According to the preferred embodiments, two possibilities are suggested for IIP2 trimming or calibration. According to the first possibility, the output offset voltage can be calibrated or trimmed by adding an offset voltage in an output branch of the differential output stage of the mixer circuit in order to obtain an asymmetry until IIP2 is compensated. As an alternative or additional second possibility, the voltage applied at a bulk terminal of a transistor in an output branch of the differential output stage can be calibrated or trimmed until IIP2 is optimized.

A criteria for trimming or calibration can be the output DC offset of the mixer circuit as far as this output is not the above static DC offset due to self-mixing or device mismatch. This criteria is specially suitable for active mixer circuits, such as the Gilbert cell, where the output DC offset is about 1000 times larger than for passive mixer circuits.

FIG. 1 shows a schematic block diagram of a calibration arrangement according to the preferred embodiments. A calibrating or trimming circuit 20 applies a trimming signal TS to a mixer circuit 10 in order to minimize second order intermodulation distortion to optimize IIP2. The trimming signal TS is an offset voltage applied (case 1) to the differential output stage of the mixer circuit 10 in order to introduce an asymmetry required to obtain a desired DC offset at the output of the mixer circuit 10. The application of the offset voltage may be achieved by adding the offset voltage at the input- or at the output-branch and/or (case 2) by applying the output voltage to a bulk terminal of a transistor connected to the output branch, e.g., of the mixer circuit 10.

The trimming circuit 20 may be adapted to read input values for generating the trimming signal TS from a memory, e.g., a look-up table 30, connected thereto. Additionally, as an optional measure, the output signal OS of the mixer circuit 10 may be fed back to the trimming circuit 20 in order to provide a feedback loop used for continuously adapting the trimming signal TS to changes in the output signal OS of the mixer circuit 10. The feedback path (as indicated by the dotted arrow in FIG. 1) may as well be used for directly measuring or detecting the DC offset at the output of the mixing circuit 10 in order to provide an additional input value to the trimming circuit 20.

FIG. 2 shows a schematic circuit diagram of an active mixer (Gilbert cell) with IIP2 calibration according to the first preferred embodiment. It is noted that in FIG. 2, only the circuit portion relating to the differential output branch of the active mixer is shown, while other circuit portions, such as a local oscillator driver, trans-impedance circuit, and a foot portion of the Gilbert cell have been omitted to reduce complexity.

As can be gathered from FIG. 2, a first offset voltage is applied at a connection point V26 at the bulk terminal of the left transistor to control asymmetry of the differential output branches. As an additional or alternative option, a second offset voltage is applied at the connection point V22, so as to add an offset voltage to the left output branch. The voltage sources indicated at connection points V5 and V6 represent current-to-voltage converter outputs and could thus be replaced by resistor symbols or corresponding current-to-voltage circuits.

Either the offset voltage provided at connection point V22 or the offset voltage provided at connection point V26 is used for IIP2 compensation. The respective non-used offset voltage may be set to zero. However, the two compensation offset voltages at connection points V22 and V26 may as well be used in combination, if desired.

It is noted that the voltage sources indicated in FIG. 2 are of a mere symbolic nature and represent any voltage generation circuitry suitable for generating and applying a desired compensation voltage. As an example, such a voltage generation circuit may consist of at least one resistor to which a current from a digital-to-analog converter (DAC) is applied to generate the required offset voltage. Thereby, the applied or added offset voltage can be controlled simply by applying a digital control word to the DAC. Of course, there are other suitable alternatives (e.g., based on resistor networks, operational amplifiers, or active or passive semiconductor elements) for generating and applying or adding the proposed offset voltages. This applies to any cases in the following description, where a simple symbol of a voltage source is shown to represent voltage generation circuits.

As already mentioned, the application of the proposed offset voltage to the bulk terminal of the left transistor T1 or the addition of the proposed offset voltage to the left output branch or a combination of both leads to an asymmetry between the two branches to thereby generate a desired output offset of the Gilbert cell, required to minimize second order intermodulation distortions and optimize IIP2.

FIG. 3 shows a schematic circuit diagram of a passive mixer circuit with IIP2 compensation according to the second preferred embodiment, where—again—parts of the whole mixer circuits have been omitted for reasons of clarity and brevity. In particular, an active trans-impedance circuit has been omitted at the mixer output, which serves to fix the output. Furthermore, the orientation of the transistors T1 to T4 is changed from a vertical to a horizontal direction. Connection point V33 provides a constant DC operation voltage for the complete passive circuitry that does not need a DC supply current. The output voltages at V29 and V30 are control voltages at an active trans-impedance circuit. Thus the mixer outputs are virtual grounds at an operational amplifier circuitry. The two DC voltage sources at V29 and V30 are thus not actually provided and just represent voltage sources which may be used for simulation purposes.

In the circuit of FIG. 3, an average bulk voltage is applied at connection point V32 and an additional compensation offset voltage is applied at connection point V31. Thus, the transistors T1 to T3 have the average bulk voltage applied at their bulk terminals, while the transistor T4 has the additional compensation offset voltage applied at its bulk terminal, in addition to the average bulk voltage. The compensation offset voltage at connection point V31 serves to compensate for errors caused by an offset threshold voltage due to device mismatch or due to local oscillator (LO) self-mixing.

The so-called amplitude modulation (AM) interferer test may be used for type approval. A modulation signal more than 6 MHz apart from the RF carrier frequency jumps in power to −31 dBm. The wanted RF signal is set 3 dB above reference sensitivity. A DC-step appears at about the midamble of a wanted RX burst. In cases of good IIP2 compensation, output DC steps are in the order of 5 μV and, for bad compensation of IIP2, in the order of up to 100 μV at the symmetrical output of the trans-impedance circuit behind the mixer. DC currents are asymmetrical for a case of bad IIP2 compensation of the active mixer of FIG. 2. This current asymmetry causes a DC output offset voltage that is about 1000 times larger than the above small DC step. Therefore, as already mentioned above, the output offset of the mixer can be used as a criteria for IIP2 calibration or trimming.

In the case of the active mixer circuit of FIG. 2, a trimming or calibration strategy may be to measure the output voltage offset for trimmed good IIP2 calibration. Then, typical cases are calculated during the evaluation phase of the die and the values are stored in the look-up table 30 of FIG. 1. Now, during application of the active mixer circuit, the trimming circuit 20 calibrates the offset voltage for the goal or target value stored in the look-up table 30. A required accuracy for measurements of the automatic trimming circuit 20 may be in the order of 2 mV.

In case of the passive mixer of FIG. 3, the following trimming or calibration strategy can be used. Here, fairly no correlation is provided between IIP2 and a rather strong DC current asymmetry, because there is no DC current in the switches of the passive mixer. If the offset bulk voltage is trimmed at the passive mixer, the overall output DC offset is moved only little, e.g., by +/−5 μV. Consequently, in view of the additional large offset resulting from LO self-mixing, it is difficult to filter DC offset changes from the noise background.

It is therefore proposed to fix typical compensation offset voltage values after the evaluation phase and reuse them during application without any further measurements. This can be feasible if large transistors are used in the passive mixer.

FIG. 4 shows a diagram indicating IIP2 values in dB over voltage values of the bulk offset voltage in the case of a passive mixer as shown in FIG. 3. In the underlying measurements, the bulk offset voltage is trimmed from −100 mV to +100 mV and the threshold offset voltage applied at connection point V33 is set to −10 mV and +10 mV. LO self-mixing is not considered here. The two curves with their peaks on the right-hand side relate to the offset voltage of −10 mV, while the upper curve relates to a receiving power at the antenna of −43 dBm and the lower curve relates to a receiving power at the antenna of −31 dBm. The two curves with their peaks at the left-hand side relate to the offset threshold voltage of 10 mV, while the upper curve relates to a receiving power at the antenna of −31 dBm and the lower curve to a receiving power at the antenna of −43 dBm. Thus, it can be seen from FIG. 4 that bulk trimming results do not depend on the power level of the applied two-tone test, but merely on the offset threshold voltage.

FIG. 5 shows a diagram indicating IIP2 versus bulk offset voltage value for the same range as in FIG. 4, but with strong LO self-mixing as the influence. The case relates to a two-tone test at an antenna power level of −43 dBm with an offset threshold voltage of 0 V and a parasitic local oscillator of 30 μA at the RF input of the passive mixer circuit for about 90° plus the phases 0°, 90°, 180° and 270°.

The curve with the peak on the left-hand side relates to 90°, and the curve with the peak on the right-hand side relates to 270°. The two curves with the peak in the center relate to 0° and 180°, while the lower one of these curves relates to 0°. The arrow indicates the robustness of the passive mixer against LO self-mixing.

FIG. 6 shows a schematic flow diagram of a further trimming or calibration strategy usable for both kinds of mixers, e.g., as shown in FIGS. 2 and 3, wherein the IM2 product obtained at the output of the mixer is minimized after a two-tone measurement.

Similar to FIGS. 4 and 5, the bulk offset voltage is changed from −100 mV to +100 mV and the obtained IM2 products (e.g., IIP2) are stored in the look-up table or memory 30 of FIG. 1. After this initial measurement, the value of the bulk offset voltage for the minimum IM2 product (i.e., maximum IIP2) is applied during application of the mixer circuit.

In step S101, a bulk offset voltage is set and the IM2 product is measured in step S102. Then, in the example of FIG. 6, the respective offset value is stored if it relates to the minimum IM2 product, i.e., if the IM2 product is the smallest of all values obtained so far. (Step S103). Then, in step S104 it is checked whether the end of the range of bulk offset voltage values has been reached. If not, the procedure returns to step S101 and selects the next bulk offset voltage. On the other hand, if it is determined in step S104 that the end of range has been reached, the stored offset voltage corresponds to the minimum IM2 product and is applied by the calibration circuit 20 of FIG. 1 (step S105).

Of course, step S103 can be modified in a sense that all offset values are stored together with their associated IM2 products. Then, step S105 is amended to include a selection operation for selecting the stored offset voltage with the minimum associated IM2 product. Then, the number of storage operations is however increased, as each individual processing loop includes a storing operation.

FIG. 7 shows a schematic circuit diagram of a portion of a mixer circuit according to the third preferred embodiment, similar to FIG. 3, where the bulk offset voltage is however applied at a connection point V35 and thus at the left transistor T1. Accordingly, the asymmetry is introduced at the left output branch to which the transistors T1 and T2 are connected.

The above mixer circuits may be implemented in a 2.7 2 V technology in the case of the active Gilbert cell and in a 1.2 1 V technology in the case of the passive mixer. In the circuit diagrams of FIGS. 2, 3, and 7, the introduction of the threshold offset voltage at one transistor pair is used to simulate a bad IIP2 situation. However, in both cases it is possible to compensate the bad IIP2 by trimming the bulk voltage of one transistor, or by adding an offset voltage to the respective output branch or a combination of both in the case of the active mixer circuit of FIG. 2. The proposed bulk trimming for optimization of IIP2 may be used for passive and active circuits. In the case of active circuits, IIP2 may, as well, be calibrated using a desired or predetermined asymmetry of the supply voltages for a transistor pair of the differential output stage. DC offset components (DC Stepp) of active mixer circuits may be used as criteria for IIP2 trimming of a Gilbert cell. This option is possible for Gilbert cells due to the fact that for the signal processing a resolution of 2 mV is still high enough for quantization.

In summary, a circuit and method for reducing intermodulation distortion in a non-linear device having a differential output stage have been described. Calibration means are provided for adding a calibration offset voltage to at least one of one output branch of said differential output stage and a bulk terminal of a transistor of one output branch of said differential output stage, to obtain a desired output offset at said differential output stage. Thereby, a certain degree of asymmetry is introduced, so that both output branches of the differential output stage are matched or optimized to improve the IIP2 factor and reduce intermodulation distortions.

It is noted that the present disclosure is not restricted to the above preferred embodiments and can be used for compensation of any intermodulation distortions in any non-linear device with differential output stage. The preferred embodiments may thus vary within the scope of the attached claims.

Finally but yet importantly, it is noted that the term “comprises” or “comprising” when used in the specification including the claims is intended to specify the presence of stated features, means, steps or components, but does not exclude the presence or addition of one or more other features, means, steps, components or group thereof. Further, the word “a” or “an” preceding an element in a claim does not exclude the presence of a plurality of such elements. Moreover, any reference sign does not limit the scope of the claims.

The various embodiments described above can be combined to provide further embodiments. All of the U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications and non-patent publications referred to in this specification and/or listed in the Application Data Sheet are incorporated herein by reference, in their entirety. Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, applications and publications to provide yet further embodiments.

These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.

Claims

1. A circuit for reducing intermodulation distortion in a non-linear device having a differential output stage, said circuit comprising: an offset voltage circuit that outputs a calibration offset voltage; anda calibration circuit coupled to the offset voltage circuit to add the calibration offset voltage to at least one of one output branch of said differential output stage and a bulk terminal of a transistor of one output branch of said differential output stage to obtain a desired output offset at said differential output stage.

2. The circuit of claim 1, further comprising a memory storing a plurality of offset voltage values, wherein said circuit is adapted to select from the memory as said calibration offset voltage an offset voltage value associated with a minimum related output value.

3. The circuit of claim 2 wherein said minimum related output value corresponds to a minimum second order intermodulation product.

4. The circuit of claim 1, further comprising a detecting circuit that detects an offset voltage at an output of said differential output stage.

5. The circuit of claim 4, further comprising a memory to store a value of a desired offset voltage, wherein the offset voltage circuit reads said value of said desired offset voltage and generates said calibration offset voltage at a value required to obtain said read value at said output offset differential output stage.

6. The circuit of claim 1, further comprising a memory for storing a value of said calibration offset voltage, wherein said offset voltage circuit is adapted to read said value of said calibration offset voltage and to generate said calibration offset voltage at a value corresponding to said read value.

7. The circuit of claim 1 wherein said non-linear device comprises a mixer circuit.

8. The circuit of claim 1 wherein said offset voltage circuit comprises a resistor device to which a current from a digital-to-analog converter is supplied.

9. The circuit of claim 1 wherein said calibration offset voltage is added to one of the supply voltages of one of the transistors of a transistor pair.

10. The circuit of claim 9 wherein said calibration offset voltage is added to a bulk voltage of said one transistor of said transistor pair.

11. A method for reducing intermodulation distortion in a non-linear device having a differential output stage, said method comprising the steps of: generating a calibration offset voltage; andadding said calibration offset voltage to at least one of one output branch of said differential output stage and a bulk terminal of a transistor of one output branch of said differential output stage to obtain an output offset at said differential output stage.

12. The method of claim 11, further comprising storing a plurality of offset voltage values and selecting the calibration offset voltage having an offset voltage value that is associated with the minimum related output value.

13. The method of claim 12 wherein said minimum related output value corresponds to a minimum second order intermodulation product.

14. The method of claim 11, further comprising detecting an offset voltage at an output of said differential output stage.

15. The method of claim 14, further comprising storing a value of a desired offset voltage, wherein said calibration offset voltage is generated at a value required to obtain said stored value at said output of said differential output stage.

16. The method of claim 11, further comprising storing a value of said calibration offset voltage, wherein said calibration offset voltage is generated at a value corresponding to said stored value.

17. The method according to of claim 11 wherein the offset output of the differential output stage is used for trimming an intermodulation intercept point second order.

18. The method of claim 17, further comprising using the offset output in DC offset components of active mixer circuits as criterion for trimming the intermodulation intercept point second order of a Gilbert cell.

19. A circuit, comprising: an active mixer having a differential output circuit with first and second output branches; anda trimming circuit coupled to the mixer, the trimming circuit applying a first offset voltage to either one of a bulk terminal of a transistor of a first branch of the differential output circuit or to an output of the first branch of the differential output circuit or to both the bulk terminal and the output of the first branch of the differential output circuit, the trimming circuit obtaining the first offset voltage from one of a memory circuit or a detecting circuit that detects an offset voltage at the output of the differential output circuit, the first offset voltage leading to an asymmetry between the first and second branches of the differential output circuit to minimize second order intermode distortion and trimming the intermodulation intercept point second order.

20. The circuit of claim 19 wherein the memory circuit comprises a look-up table of stored values.

21. The circuit of claim 19 wherein the trimming circuit is structured to continuously monitor the output signal of the mixer circuit and to adapt the first offset voltage to changes in the differential output circuit output signal.

22. A circuit, comprising: a passive mixer circuit having a plurality of transistors in an output circuit thereof; anda trimming circuit coupled to the plurality of transistors in the passive mixer circuit and structured to supply an offset voltage that comprises an average bulk voltage applied to a bulk terminal of all of the plurality of transistors and a compensation offset voltage that is applied at the bulk terminal of one of the plurality of transistors to compensate for errors caused by an offset threshold voltage.

23. The circuit of claim 21 wherein the trimming circuit is coupled to an output of the passive mixer circuit to receive an output offset of the passive mixer circuit and to generate the offset voltage therefrom.

24. The circuit of claim 22, comprising a memory coupled to the trimming circuit and having a look-up table of stored values from which the trimming circuit draws the offset voltage.