The present invention relates to a capacitive load drive circuit that changes the potential of each electrode of apparatuses such as a plasma display apparatus (a PDP apparatus) and a liquid crystal display apparatus, a method for driving the same, and a plasma display apparatus.
A plasma display apparatus (a PDP apparatus) or a liquid crystal apparatus comprises a plurality of electrodes arranged adjacently or in opposition to each other and the potential at each electrode is changed between a high potential and a low potential. Each electrode forms a capacitive load between itself and an electrode arranged adjacently thereto or between itself and an electrode arranged in opposition thereto, and a drive circuit for changing the potential at each electrode between the high potential and the low potential eventually changes the potential of a terminal of the capacitive load. Such a drive circuit is called a capacitive load drive circuit, is widely used and is not limited to use only in a PDP apparatus or a liquid crystal display apparatus. In a PDP apparatus, as the difference between a high potential and a low potential (the drive voltage) is large, it is necessary to use a drive element having a large withstand voltage and the period (the drive period) to be changed is also short, therefore, there arises a problem of such as heat radiation and more improvements to a capacitive load drive circuit are required. Here, although explanation is made using a capacitive load drive circuit used in a PDP apparatus as an example, the present invention is not limited to this capacitive load drive circuit but can be applied to other capacitive load drive circuits used in other apparatuses.
A PDP apparatus and a capacitive load drive circuit used therein are described, for example, in U.S. Pat. No. 6,686,912, U.S. Pat. No. 6,496,166 and U.S. Pat. No. 6,373,452, and are widely known, therefore, a detailed explanation will not be given here but only the points directly relating to the present invention are explained briefly.
In a PDP apparatus, a plurality of first electrodes (X electrodes) and second electrodes (Y electrodes) extending in a first direction are arranged by turns on one of substrates and a plurality of address electrodes extending in a second direction perpendicular to the first direction are arranged on the other opposing substrate, and a display cell is formed at the intersection between a pair of the neighboring X and Y electrodes and the address electrodes. A discharge gas is sealed in between the substrates, a voltage is applied across each gap between neighboring electrodes to cause a discharge to occur, and ultraviolet beams produced by the discharge excite phosphors provided on the opposing substrate to cause to emit light. A capacitor is formed between neighboring electrodes and, in particular, a large capacitor is formed between the X electrode and the Y electrode because the X and Y electrodes are arranged in parallel and adjacently.
A PDP apparatus currently put to practical use is an address/display separation system AC type PDP apparatus, in which a period during which a cell to be displayed is selected (an address period) and a display period during which a discharge is caused to occur for lighting to produce a display (a sustain period) are separated.
The PDP apparatus comprises a first (X) electrode drive circuit, a second (Y) electrode drive circuit, and an address electrode drive circuit for changing the potentials of the X electrode, the Y electrode, and the address electrode, respectively, according to the drive waveforms shown in
As shown schematically, during the sustain period, a sustain pulse is applied alternately to all the X electrodes and the Y electrodes and as the capacitance between the X electrode and the Y electrode is large. What consumes a large power among operations of the X electrode drive circuit and the Y electrode drive circuit is the application of the sustain pulse. The problem of the operation, that is, the application of the sustain pulse by the X electrode drive circuit and the Y electrode drive circuit is explained below.
As described above, it is necessary for the Y electrode drive circuit to apply a scan pulse sequentially to the Y electrodes during the address period and the respective Y electrodes are provided with the individual second (Y) electrode drive circuits. Each of the individual Y electrode drive circuits comprises a switch SW3 for switching connections between the other terminal (the Y electrode) of the capacitive load Cp and a high-potential power supply, a switch SW4 for switching connections between the Y electrode and a low-potential power supply, a diode D3 provided in parallel to the switch SW3, and a diode D4 provided in parallel to the switch SW4. The diodes D3 and D4 are provided for the same purposes as the diodes D1 and D2. During the sustain period, all the individual Y electrode drive circuits perform the same action, therefore, it is assumed that the Y electrode drive circuit shown on the right-side in
The MOSFET allows a current to flow in both the directions but the bipolar transistor and the IGBT allow a current to flow only in one direction. Moreover, after the bipolar transistor and IGBT are brought into the ON-state to allow a current to flow, there exist a number of residual carriers in the elements and the state will be maintained for a somewhat long time. In contrast to this, after the MOSFET is brought into the ON-state to allow a current to flow, the residual carriers decrease rapidly. However, if a current flows through the parasitic diode of the MOSFET, there exist a number of residual carriers and the state is maintained for a somewhat long time. Similarly, if a current flows through the individual diodes, there exist a number of residual carriers in the elements and the state is maintained for a somewhat long time.
When the potential of the X electrode is changed from the high potential to the low potential, SW1, SW3 and SW4 are brought into the OFF-state (the cutoff state) and SW2 is brought into the ON-state. Due to this, the X electrode of Cp is connected to the low-potential power supply in the X electrode drive circuit via SW2 and the X electrode changes from the high potential to the low potential. In this case, a current path is formed as follows: the low-potential power supply in the Y electrode drive circuit, D4, Cp, SW2 and to the low-potential power supply in the X electrode drive circuit. In
When the potential of the Y electrode is changed from the low potential to the high potential, SW1 and SW4 are brought into the OFF-state and, while SW2 is maintained in the ON-state, SW3 is brought into the ON-state. Due to this, the X electrode of Cp is connected to the high-potential power supply in the Y electrode drive circuit via SW3 as shown in
When the potential of the Y electrode is changed from the high potential to the low potential, SW1, SW2 and SW3 are brought into the ON-state and SW4 is brought into the ON-state. Due to this, as shown in
As the operations in
As described above, in the operations shown in
As described above, after the bipolar transistor and IGBT are brought into the ON-state to allow a current to flow, there exist a number of residual carriers in the elements and the state is maintained for a somewhat long time. Moreover, when a current flows through the parasitic diode and the individual diodes of the MOSFET, there exist a number of residual carriers in the elements and the state is maintained for a somewhat long time.
In the PDP apparatus, the number of sustain pulses relates to the luminance of a display and there is a demand for an increase in number of sustain pulses in one display frame for improving luminance. Therefore, the period of a sustain pulse is required to be as short as possible and, for example, a period of about 1 μs is desired. If, however, the period of a sustain pulse is shortened, there arises a problem in that, before the residual carriers, which are produced when the bipolar transistor and IGBT are brought into conduction, decrease, the potentials of the terminals (X electrode and Y electrode) of a capacitive load change, and the residual carriers act as a load. This problem is explained below with reference to
As shown in
Similarly, as shown in
In the operations shown in
Power P consumed by the residual carriers in the capacitive load drive circuit described above is expressed as
P=Qc×Vs×f
where a charge amount of residual carriers that increase a drive current is Qc, a potential difference (voltage) between the high potential and the low potential is Vs, and a sustain frequency is f.
As described above, in the PDP apparatus, a voltage to be applied to a capacitive load (between the X electrode and the Y electrode) is as high as about 180V and the sustain frequency f is also high, therefore, there arises a big problem of an increase in power consumption by the residual carriers that increase the drive current and of heat generation in drive elements in conjunction therewith.
The object of the present invention is to reduce power consumption by residual carriers in a capacitive load drive circuit and a PDP apparatus using the same.
In order to attain the above-mentioned object, according to the present invention, the residual carriers are reduced by driving the carriers using a voltage sufficiently lower than the drive voltage instead of using the drive voltage to be applied to the capacitive load (between the X electrode and the Y electrode). As the voltage to be used to reduce the residual carriers is small, the power consumption can be considerably reduced compared to the case where the residual carriers are reduced using the drive voltage.
In a first aspect according to the present invention, power consumption by residual carriers, which are formed when a diode provided in parallel to a switch circuit of a capacitive load drive circuit is brought into conduction, is reduced, and the switch circuit connected in parallel to the diode is brought into conduction (brought into the ON-state) during a period of time from when the diode is brought into conduction until the potential of a terminal to which the diode is connected changes. By bringing the switch circuit connected in parallel to the diode into conduction, a closed circuit is formed by the diode and the switch circuit and the residual carriers formed in the diode are reduced. The voltage applied to the closed circuit is almost zero and power consumption is very small even if a current due to the residual carriers flows through the closed circuit.
The first aspect according to the present invention can also be applied to a case where a capacitive load drive circuit having the fundamental configurations shown in
A second aspect according to the present invention comprises an inductance element at the output part of a capacitive load drive circuit. When a discharge (charge) of a capacitive load is completed and the current that flows through the diode is terminated, a voltage in the opposite direction is generated by the counter electromotive force of the inductance element and a current flows in the direction in which the residual carriers formed in the diode are reduced. The inductance value of the inductance element is set to the minimum value that can reduce the residual carriers formed in the diode.
The second aspect according to the present invention can be applied not only to a capacitive load drive circuit having the fundamental configurations shown in
A third aspect according to the present invention comprises a voltage source that generates a potential higher than the low potential and lower than the high potential and an intermediate offset switch that switches connections between the terminal of the capacitive load and the voltage source, and when the terminal of the capacitive load is at the low potential, the intermediate off switch is brought into conduction by temporarily putting it into the ON-state. Due to this, the residual carriers in the switch circuit and the diode connected between the terminal of the capacitive load and the low-potential power supply are reduced. This causes the potential of the terminal of the capacitive load to vary by the amount of voltage corresponding to the power supply, but if the voltage of the voltage source is small, no problem will be brought about. For example, when the drive voltage is 180V and the voltage of the voltage source is 5V, the power consumption by the residual carriers can be reduced to 1/36.
The third aspect can be applied to a capacitive load drive circuit having the fundamental configuration shown in
A fourth aspect according to the present invention comprises a high power supply switch that switches connections between the high potential side terminal of a first switch and the high potential side power supply, a voltage source that generates a voltage higher than the high potential by a predetermined value, and a high potential offset switch that switches connections between the high potential side terminal of the first switch and the voltage source, and when the terminal of the capacitive load is at the high potential, the high potential offset switch is brought into conduction by temporarily putting it into the ON-state. Due to the residual carriers in the switch circuit and the diode connected between the capacitive load terminal, the high potential power supply can be reduced. This causes the potential of the capacitive load terminal to vary by the amount of voltage corresponding to the power supply, but if the voltage of the voltage source is small, no problem will be brought about. For example, when the drive voltage is 180V and the voltage of the voltage source is 5V, the power consumption by the residual carriers can be reduced to 1/36.
The fourth aspect can be applied to a capacitive load drive circuit having the fundamental configuration shown in
A fifth aspect according to the present invention is applied to an ALIS system PDP apparatus disclosed in U.S. Pat. No. 6,373,452. In the ALIS system PDP apparatus, first electrodes (X electrodes) and second electrodes (Y electrodes) are arranged adjacently by turns, a first display line is formed between the Y electrode and the X electrode adjacent to one side of the Y electrode in question, and a second display line is formed between the Y electrode and the X electrode adjacent to the other side of the Y electrode and, in an odd field in which a display is produced by the use of the first display lines, in-phase sustain pulses are applied to odd-numbered X electrodes and even-numbered Y electrodes and are also applied to even-numbered X electrodes and odd-numbered Y electrodes during the sustain period and, in an even field in which a display is produced by the use of the second display lines, in-phase sustain pulses are applied to odd-numbered X electrodes and odd-numbered Y electrodes and are also applied to even-numbered X electrodes and even-numbered Y electrodes during the sustain period. Moreover, the respective X and Y electrodes form the same respective capacitive loads between themselves and the respective neighboring electrodes on both the sides thereof. The drive circuit is provided with an odd X electrode drive circuit that drives odd-numbered X electrodes, an even X electrode drive circuit that drives even-numbered X electrodes, an odd Y electrode drive circuit that drives odd-numbered Y electrodes, and an even Y electrode drive circuit that drives even-numbered Y electrodes.
According to the fifth aspect of the present invention, during the sustain period in the odd field, the even Y electrode drive circuit supplies a sustain pulse delayed by a brief period of time from that in the odd X electrode drive circuit and the odd Y electrode drive circuit supplies a sustain pulse delayed by a brief period of time from that in the even X electrode drive circuit, and during the sustain period in the even field, the odd Y electrode drive circuit supplies a sustain pulse delayed by a brief period of time from that in the odd X electrode drive circuit and the even Y electrode drive circuit supplies a sustain pulse delayed by a brief period of time from that in the even X electrode drive circuit. Here, a “brief period of time” means a time sufficiently shorter than a time required for the change of potential when the potential of the X electrode or Y electrode is changed by switching switches.
A conventional ALIS system PDP apparatus comprises X electrodes and Y electrodes to which in-phase sustain pulses are applied. Those electrodes are referred to as in-phase X electrodes and in-phase Y electrodes, respectively, here. According to the fifth aspect of the present invention, a sustain pulse to be applied to the in-phase Y electrode is delayed from a sustain pulse to be applied to the in-phase X electrode by a very brief period of time. Due to this, the potential of the in-phase X electrode changes slightly before the change of the potential of the in-phase Y electrode and this change propagates to the Y electrode via a capacitor between the in-phase X and Y electrodes, reducing the residual carriers in the switches that make up the Y electrode drive circuit. As the amount of delay is small, the potential difference (voltage) between the in-phase X and Y electrodes produced when the potentials of both the electrodes change is small, and the residual carriers are driven by this voltage, therefore, the power consumption by the residual carriers can be considerably reduced.
In the conventional ALIS system PDP apparatus, in-phase sustain pulses are applied to the in-phase X and Y electrodes, therefore, the capacitor between the in-phase X and Y electrodes does not act as a load to the drive circuit. In contrast to this, according to the fifth aspect of the present invention, as a potential difference is produced between the in-phase X and Y electrodes, the capacitor will act as a load to the drive circuit but, if the potential difference between the in-phase X and Y electrodes is small, the effect of reduction in power consumed by the residual carriers is stronger than the effect of increase in drive power due to the load.
It is also possible to reduce the power consumption by the residual carriers as follows. During the sustain period in the odd field, the even Y electrode drive circuit supplies a sustain pulse whose sustain pulse fall is slightly delayed from that in the odd X electrode drive circuit and the odd Y electrode drive circuit supplies a sustain pulse whose sustain pulse fall is slightly delayed from that in the even Y electrode drive circuit, and during the sustain period in the even field, the odd Y electrode drive circuit supplies a sustain pulse whose sustain pulse fall is slightly delayed from that in the odd X electrode drive circuit and the even Y electrode drive circuit supplies a sustain pulse whose sustain pulse fall is slightly delayed from that in the even X electrode drive circuit.
What can be reduced in the fifth aspect is only the power consumption by the residual carriers formed in the elements that make up the switch circuit of the Y electrode drive circuit, and the power consumption by the residual carriers in the elements that make up the switch circuit of the X electrode drive circuit cannot be reduced. Therefore, when the switch circuits of the X and Y electrode drive circuits are composed of bipolar transistors or IGBTs, the power consumption by the residual carriers can be halved at most.
It is necessary for the Y electrode drive circuit to integrate the individual Y electrode drive circuits, the number of which is equal to that of the Y electrodes. If the individual Y electrode drive circuit is composed of IGBTs, the residual carriers cause a problem. If the fifth aspect is applied here, the power consumption by the residual carriers formed in the IGBTs that make up the switch circuit of the Y electrode drive circuit can be halved and the power consumption can be reduced because the number of the residual carriers in the MOSFETs that make up the X electrode drive circuit is small.
When the switch circuits of the odd and even X electrode drive circuits are composed of MOSFETs, the parasitic diode that exists in parallel with a MOSFET can be used or another individual diode can be connected thereto.
The features and advantages of the invention will be more clearly understood from the following description taken in conjunction with the accompanying drawings, in which:
The plurality of the address electrodes A are driven individually by an address driver 2. One end of each of the plurality of the X electrodes is connected commonly and driven commonly by an X electrode drive circuit 3. A Y electrode drive circuit is composed of individual Y electrode drive circuits 4-1, 4-2, . . . , the number of which is equal to that of the Y electrodes, and each of the individual Y electrode drive circuits drives the Y electrode corresponding thereto.
The configuration described above is the same as that of a conventional PDP apparatus and the details thereof are described in, for example, U.S. Pat. No. 6,686,912, U.S. Pat. No. 6,496,166 and U.S. Pat. No. 6,373,452. Therefore, an explanation will not be given here.
As shown in
In the PDP apparatus in the first embodiment, it is assumed that switches SW1 and SW2 in the X electrode drive circuit 3 are composed of a MOSFET and diodes D1 and D2 are composed of a parasitic diode of the MOSFETs making up SW1 and SW2 and an individual diode connected in parallel to the MOSFET. Switches SW3 and SW4 in each of the individual Y electrode drive circuits 4-1, 4-2, . . . , are composed of an IGBT, diodes D3 and D4 are composed of an individual diode connected in parallel to the IGBT making up SW3 and SW4, and the plurality of the individual Y electrode drive circuits 4-1, 4-2, . . . , are integrated into an IC chip. The reason to configure in the manner described above is that the IGBT is more suitable for integration compared to the MOSFET.
As is obvious from comparison between
By the way, it is not necessary for SW4 to be in the ON-state continuously as shown in
During the sustain period, if SW4 is put into the ON-state (the conduction state) after SW1 to SW3 are put into the OFF-state (the cutoff state) in order to change the potential of the Y electrode from H to L, a current path from the low potential power supply in the X electrode drive circuit to the low potential power supply in the Y electrode drive circuit via D2, the inductance element L, Cp, and SW4 is formed as shown in
The inductance value of the inductance element L needs to be specified so that the minimum voltage VA that can reduce the residual carriers formed in the diode, the current flowing through the induction element L during discharge being taken into consideration.
The residual carriers in D4 in the Y electrode drive circuit can also be reduced by means of the inductance element L provided at the output part of the X electrode drive circuit. The operation principles are explained below with reference to
Although the inductance element L is provided at the output part of the X electrode drive circuit in the third embodiment, it is also possible to provide an inductance element at the output part of the Y electrode drive circuit.
As shown in
After the potential of the X electrode changes from H to L, the residual carriers are formed in D4 and SW4, but if SW11 is put into the ON-state (the conduction state) during a period of time from when the potential of the X electrode changes from H to L until when the potential of the Y electrode changes from L to H, a closed circuit (a loop) composed of the voltage source VX, SW11, Cp, and SW4 or D4 is formed, the potential of the X electrode is raised to a potential higher than the low potential by Vx, and the residual carriers in D2 and SW2 are reduced via Cp.
The voltage Vx of the voltage source VX is sufficient as long as it is capable of reducing the residual carriers and it can be very small. For example, when the drive voltage is 180 V and Vx is 5 V, the power consumption by the residual carriers can be reduced to 1/36.
By the way, if SW11 is put into the ON-state, the potential of the X electrode increases from the low potential by Vx, but if the amount of increase is small, no problem will be brought about.
In the PDP apparatus in the fourth embodiment, there is a case where both potentials of the X electrode and Y electrode change to the low potential simultaneously but not a case where both potentials change to the high potential simultaneously during the sustain period, but in the configuration in the fourth embodiment, there is a case where both potentials of the X electrode and Y electrode change to the high potential simultaneously as in the second embodiment and the configuration can also be applied to a case where both potentials do not change to the low potential simultaneously. However, as when the X electrode is at the low potential, the Y electrode is at the high potential, therefore, the residual carriers in SW4 and D4 in the Y electrode drive circuit cannot be reduced. Therefore, it is necessary to provide the voltage source VX and SW11 both in the X electrode drive circuit and in the Y electrode drive circuit.
As described in
Similarly, after the potential of the Y electrode changes from L to H, residual carriers are formed in SW3 and, therefore, SW15 is put into the OFF-state and SW16 is put into the ON-state during a period of time from when the potential of the Y electrode changes from L to H until when the potential of the Y electrode changes from H to L, as shown in
By the way, as in the second embodiment, in the case where both potentials of the X electrode and Y electrode change to the high potential simultaneously but do not change to the low potential simultaneously, the residual carriers are formed in D1 and D3, as described in
The voltage Vy of the voltage sources VY1 and VY2 is sufficient as long as it is capable of reducing the residual carriers and can be very small. For example, when the drive voltage is 180 V and Vy is 5 V, the power consumption by the residual carriers can be reduced to 1/36.
By the way, when the switches in the X electrode drive circuit are composed of MOSFETs, the switches in the Y electrode drive circuit are composed of IGBTs, and potentials are changed so that there is a case where both potentials of the X electrode and Y electrode change to the low potential simultaneously but do not change to the high potential simultaneously, the residual carriers in SW1 are few and D1 is not used during the sustain period, therefore, SW13 and SW14 need not be provided.
Next, the PDP apparatus in the fifth embodiment is explained. The PDP apparatus in the fifth embodiment is the ALIS system PDP apparatus described in U.S. Pat. No. 6,373,452. As the ALIS sytem PDP apparatus is described in detail in, for example, U.S. Pat. No. 6,373,452, a detailed explanation will not be given here but only the parts concerned will be explained below.
In the plasma display panel 11, the X electrodes and the Y electrodes are arranged by turns at substantially equal intervals, therefore, capacitive loads are formed between each X electrode and the Y electrode adjacent to one side of the X electrode in question and between the X electrode and the Y electrode adjacent to the other side of the X electrode, and capacitive loads are formed between each Y electrode and the X electrode adjacent to one side of the Y electrode in question and between the Y electrode and the X electrode adjacent to the other side of the Y electrode. Here, a capacitive load formed between an odd-numbered X electrode and an odd-numbered Y electrode is denoted by Cp11, a capacitive load formed between an odd-numbered X electrode and an even-numbered Y electrode is denoted by Cp12, a capacitive load formed between an even-numbered X electrode and an odd-numbered Y electrode is denoted by Cp21, and a capacitive load formed between an even-numbered X electrode and an even-numbered Y electrode is denoted by Cp22. Moreover, an odd-numbered X electrode is denoted by X1, an even-numbered X electrode is denoted by X2, an odd-numbered Y electrode is denoted by Y1, and an even-numbered Y electrode is denoted by Y2.
Still moreover, a first display line is formed between each Y electrode and the X electrode adjacent to one side of the Y electrode in question and a second display line is formed between the Y electrode and the X electrode adjacent to the other side of the Y electrode. For example, the first display line is formed between the X1 electrode and the Y1 electrode and between the X2 electrode and the Y2 electrode, and the second display line is displayed between the Y1 electrode and the X2 electrode and between the Y2 electrode and X1 electrode. In the ALIS system PDP apparatus, an interlaced display is produced and the first display line is displayed in the odd field and the second display line is displayed in the even field. When the first display line is displayed (in the odd field), in-phase sustain pulses are applied to the X1 electrode and Y1 electrode and in-phase sustain pulses are applied to the X2 electrode and Y1 electrode during the sustain period. When the second display line is displayed (in the even field), in-phase sustain pulses are applied to the X1 electrode and Y1 electrode and in-phase sustain pulses are applied to the X2 electrode and the Y2 electrode during the sustain period.
In a PDP apparatus in a sixth embodiment also, switches SW1 and SW2 in the odd X electrode drive circuit 130 and switches SW5 and SW6 in the even X electrode drive circuit 13E are composed of MOSFETs and switches SW3 and SW4 in the plurality of the individual odd Y electrode drive circuits 140-1, 140-2, . . . , and switches SW7 and SW8 in the plurality of the individual even Y electrode drive circuits 14E-1, 14E-2, . . . , are composes of IGBTs. The individual odd Y electrode drive circuits 140-1, 140-2, . . . , and the individual even Y electrode drive circuits 14E-1, 14E-2, . . . , are integrated into IC chips, respectively. Individual diodes are used as diodes D1 to D8.
During the sustain period in the odd field in the conventional case, the potentials of the X1 electrode and Y2 electrode and the potentials of the X2 electrode and Y1 electrode change in phase but, during the sustain period in the odd field in the sixth embodiment, as shown in
For example, when SW1 and SW7 are put into the ON-state and the X1 electrode and the Y2 electrode change to the high potential, as shown in
Next, SW2 and SW8 change into the ON-state in order to change the X1 electrode and the Y2 electrode to the low potential. At this time, if SW2 and SW8 are put into the ON-state simultaneously as in the conventional case, the residual carriers in SW7 flow through SW8, resulting in large power consumption. In the sixth embodiment, on the contrary, SW2 is put into the ON-state earlier, therefore, a current path is formed from the high-potential power supply in the Y2 electrode drive circuit to the low-potential power supply in the X1 electrode drive circuit via SW7, Cp12, and SW2 and, therefore, the residual carriers in SW7 are reduced. When a time of td elapses after SW2 is put into the ON-state, SW8 is put into the ON-state, and if the potential of the X1 electrode drops from the high potential by Vd and the voltage difference Vd is maintained during the change of the X1 electrode and Y2 electrode, the residual carriers in SW7 are driven by the voltage difference Vd and reduced as a result. Therefore, for example, when the drive voltage is 180 V and the voltage difference is 5 V, the power consumption by the residual carriers in SW7 is reduced to 1/36.
Although the case where SW8 is put into the ON-state after SW2 is put into the ON-state is explained above, this applies to other cases and the power consumption by the residual carriers in IGBTs making up SW3, SW4, SW7 and SW8 can be reduced. By the way, SW1, SW2, SW5, and SW6 are composed of MOSFETs, therefore, the residual carriers are few and no problem will be brought about.
In the conventional ALIS system PDP apparatus, in-phase sustain pulses are applied to the X1 electrode and Y2 electrode, and the X2 electrode and Y1 electrode, respectively, therefore, Cp12 and Cp21 do not act as loads on the drive circuit but, in the sixth embodiment, Cp12 and Cp21 act as loads on the drive circuit because of the delay present between changes in potential. However, if the above-mentioned voltage difference Vd is small, the effect of the reduction in power consumption by the residual carriers is stronger than the effect of the increase in drive power due to Cp12 and Cp21.
Although the switches SW1, SW2, SW5, and SW6 in the odd and even X electrode drive circuits are composed of MOSFETs in the sixth embodiment, these switches can be composed of IGBTs. However, as the residual carriers in SW1, SW2, SW5, and SW6 cannot be reduced, the power consumption by these switches cannot be reduced. Nonetheless, the power consumption by the residual carriers in SW3, SW4, SW7, and SW8 in the odd and even X electrode drive circuits can be reduced, the effect can still be obtained.
The embodiments of the present invention are described as above and the configuration in each of the embodiments can be combined with the other configuration in the other embodiment, and how they are combined is determined appropriately based on the elements that make up the drive circuit and the drive waveforms.
As described above, according to the present invention, the power consumption by the residual carriers, which are formed when the elements such as diodes and IGBT that make up the capacitive load drive circuit are brought into conduction, can be reduced considerably, therefore, it is possible to reduce the heat that accompanies the power consumption as well as reducing the power consumption in the circuit. In the case of the integrated drive circuit, the heat produced in the integrated circuit brings about a big problem and the increase in drive frequency is limited, but according to the present invention, the drive frequency can be increased because the production of heat can be suppressed. In particular, the display luminance of a PDP apparatus can be further improved according to the present invention because the display luminance of a PDP apparatus is limited by the drive frequency (the sustain frequency).
Moreover, according to the present invention, the undesired power consumption by the residual carriers, which occupies a large part of the total power consumption, can be reduced by only changing the drive sequence or additionally providing a simple circuit, therefore, the power consumption can be reduced considerably while the increase in cost can be maintained at minimum.
Still further by applying the present invention to a PDP apparatus, the power consumption can be reduced, therefore, the production of heat in drive elements can be suppressed, the display luminance of the PDP apparatus can be increased, and a flat display apparatus capable of producing a much brighter display can be realized.
Number | Date | Country | Kind |
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2004-044598 | Feb 2004 | JP | national |