Patent Application
20250240986
This application is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2024-0009793, filed on Jan. 22, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.
The disclosure relates to a capacitor and a semiconductor device including the same.
Semiconductor devices such as memory and transistors are used in various household and industrial devices. With the increasingly high performance of household and industrial devices, semiconductor devices have become highly integrated and miniaturized.
Along with the high integration and miniaturization of semiconductor devices, the sizes of semiconductor devices have decreased. Thus, the space occupied by capacitors included in (and/or as part of) the semiconductor devices is also shrinking. As the capacity of capacitors is based on the size of the capacitor, the capacity of capacitors decreases and leakage current increases due to the reduction in size of the capacitors; therefore various methods are proposed to solve such problems.
Provided are a capacitor with a reduced leakage current and an improved dielectric constant and a semiconductor device including the capacitor.
Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the presented embodiments of the disclosure.
According to an aspect of the disclosure, a capacitor includes a first electrode, a second electrode, a dielectric layer between the first electrode and the second electrode, and an interface protection electrode between the dielectric layer and the second electrode, the interface protection electrode including an oxide including molybdenum (Mo) or vanadium (V).
Space groups of the interface protection electrode and the dielectric layer may be shared as a tetragonal system.
Space groups of the interface protection electrode and the dielectric layer may be shared as a cubic system.
The lattice structure of the interface protection electrode and the lattice structure of the dielectric layer may share an oxygen atom with each other.
The interface protection electrode may include a plurality of layers.
The dielectric layer may include an oxide including a perovskite-type crystal structure.
The dielectric layer may include at least one of BaSrTiO3 or SrTiO3.
The dielectric layer may include a metal oxide including ZrO2, HfO2, TiO2, Al2O3, or a combination thereof.
The dielectric layer may include a plurality of layers.
Among the plurality of layers of the dielectric layer, the layer directly contacting the interface protection electrode may include an oxide having a perovskite-type crystal structure.
The first electrode and the second electrode each may independently include a conductive material including at least one of titanium (Ti), nickel (Ni), aluminum (Al), tantalum (Ta), tungsten (W), platinum (Pt), palladium (Pd), gold (Au), iridium (Ir), rhodium (Rh), molybdenum (Mo), vanadium (V) or niobium (Nb), an oxide of Ti, an oxide of Ni, an oxide of Al, an oxide of Ta, an oxide of W, an oxide of Pt, an oxide of Pd, an oxide of Au, an oxide of Ir, an oxide of Rh, an oxide of Mo, an oxide of V or an oxide of Nb, a nitride of Ti, a nitride of Ni, a nitride of Al, a nitride of Ta, a nitride of W, a nitride of Pt, a nitride of Pd, a nitride of Au, a nitride of Ir, a nitride of Rh, a nitride of Mo, a nitride of V, or a nitride of Nb, or a combination thereof.
According to another aspect of the disclosure, a semiconductor device includes a transistor comprising a semiconductor substrate and a gate stack, the semiconductor substrate comprising a source region, a drain region, and a channel region between the source region and the drain region; and a capacitor electrically connected to the transistor, wherein the capacitor comprises a first electrode, a second electrode, a dielectric layer between the first electrode and the second electrode, and an interface protection electrode between the dielectric layer and the second electrode, the interface protection electrode comprising an oxide comprising molybdenum (Mo) or vanadium (V).
Space groups of the interface protection electrode and the dielectric layer may be shared as a tetragonal system.
Space groups of the interface protection electrode and the dielectric layer may be shared as a cubic system.
The lattice structure of the interface protection electrode and the lattice structure of the dielectric layer may share an oxygen atom with each other.
The dielectric layer may include an oxide including a perovskite-type crystal structure.
The dielectric layer may include at least one of BaSrTiO3 or SrTiO3.
The dielectric layer may include a metal oxide including ZrO2, HfO2, TiO2, Al2O3, or a combination thereof.
The dielectric layer may include a plurality of layers, and among the plurality of layers, a layer contacting the interface protection electrode may include an oxide having a perovskite-type crystal structure.
The gate stack may be provided to face the channel region, on the semiconductor substrate, and include a gate insulating layer and a gate electrode.
The above and other aspects, features, and advantages of certain embodiments of the disclosure will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:
Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, the present embodiments may have different forms and should not be construed as being limited to the descriptions set forth herein. Accordingly, the embodiments are merely described below, by referring to the figures, to explain aspects. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list.
Hereinafter, with reference to the accompanying drawings, a capacitor and a semiconductor device including the same according to various embodiments will be described in detail. In the drawings, like reference numerals denote like components, and sizes of components in the drawings may be exaggerated for convenience of explanation. In addition, embodiments to be described are merely examples, and various modifications may be made from such embodiments. Additionally, when the terms “about” or “substantially” are used in this specification in connection with a numerical value and/or geometric terms, it is intended that the associated numerical value includes a manufacturing tolerance (e.g., ±10%) around the stated numerical value. Further, regardless of whether numerical values and/or geometric terms are modified as “about” or “substantially,” it will be understood that these values should be construed as including a manufacturing or operational tolerance (e.g., ±10%) around the stated numerical values and/or geometry. Additionally, whenever a range of values is enumerated, the range includes all values within the range as if recorded explicitly clearly, and may further include the boundaries of the range. Accordingly, the range of “X” to “Y” includes all values between X and Y, including X and Y.
An expression such as “above” or “on” may include not only the meaning of “immediately on in a contact manner”, but also the meaning of “on in a non-contact manner”. Singular forms include plural forms unless apparently indicated otherwise contextually. It will also be understood that such spatially relative terms, such as “above”, “top”, etc., are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures, and that the device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative terms used herein interpreted accordingly. When a portion is referred to as “comprises” a component, the portion may not exclude another component but may further include another component unless stated otherwise.
The use of the terms of “the above-described” and similar indicative terms may correspond to both the singular forms and the plural forms. When there is an explicit description of the order of operations of the method or there is no description contrary thereto, these operations may be performed in an appropriate order and the order is not necessarily limited to the described order.
Connections of lines or connection members between components shown in the drawings are illustrative of functional connections and/or physical or circuit connections, and in practice, may be represented as alternative or additional various functional connections, physical connections, or circuit connections. Also, in the specification, the term “units” or “ . . . modules” denote units or modules that process at least one function or operation, and may be realized by and/or include processing circuitry such as hardware, software, or a combination of hardware and software. For example, the processing circuitry more specifically may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a System-on-Chip (SoC), a programmable logic unit, a microprocessor, application-specific integrated circuit (ASIC), etc. The processing circuitry may include electrical components such as at least one of transistors, resistors, capacitors, etc., and/or electronic circuits including said components.
The use of all examples or exemplary terms is only to describe technical spirit in detail, and the scope is not limited by these examples or terms unless limited by the claims.
Referring to
The first electrode 110 may include a conductive material, such as a metal, a metal nitride, a metal oxide, and/or a combination thereof. For example, the first electrode 110 may include a metal (such as titanium (Ti), nickel (Ni), aluminum (Al), tantalum (Ta), tungsten (W), platinum (Pt), palladium (Pd), and gold (Au), iridium (Ir), rhodium (Rh), molybdenum (Mo), vanadium (V), niobium (Nb), etc.), a nitride of Ti, a nitride of Ni, a nitride of Al, a nitride of Ta, a nitride of W, a nitride of Pt, a nitride of Pd, a nitride of Au, a nitride of Ir, a nitride of Rh, a nitride of Mo, a nitride of V, a nitride of Nb, an oxide of Ti, an oxide of Ni, an oxide of Al, an oxide of Ta, an oxide of W, an oxide of Pt, an oxide of Pd, an oxide of Au, an oxide of Ir, an oxide of Rh, an oxide of Mo, an oxide of V, an oxide of Nb, etc., a combination thereof and/or the like. In at least one embodiment, the first electrode 110 may include a single material layer and/or a multilayer structure including a plurality of material layers.
The dielectric layer 120 may include an oxide having perovskite type crystal structure. The oxide having the perovskite type crystal structure may be, for example, a ternary compound expressed as a chemical equation of ABO3. A may be arranged at eight corners of a unit cell, B may be arranged in the center of the unit cell, and an oxygen atom may be arranged in the center of six sides of the unit cell. In the unit cell, a ratio of A, B, and an oxygen atom may be 1:1:3. The dielectric layer 120 may include, for example, BaSrTiO3 or SrTiO3. The dielectric layer 120 may include a perovskite material including strontium (Sr), barium (Ba), titanium (Ti), hafnium (Hf), yttrium (Y), etc. However, the disclosure is not limited thereto, and the dielectric layer 120 may include various perovskite materials.
The dielectric layer 120 may include a metal oxide. The dielectric layer 120 may include a metal oxide including, for example, ZrO2, HfO2, TiO2, Al2O3, or a combination thereof.
The dielectric layer 120 may have (or define) one or more structures. The structures may include, for example, a flat structure, a trench structure, and a pillar structure, but the disclosure is not limited thereto and any structure used in the art may be possible. As the dielectric layer 120 has this structure, the dielectric layer 120 is applicable to various types of devices.
The dielectric layer 120 may include a single layer or a plurality of layers. The dielectric layer 120 may include a 2-layer structure, a 3-layer structure, a 4-layer structure, etc., without being necessarily limited to such a range, and may have a multi-layer structure including more layers according to required performance. When the dielectric layer 120 includes a plurality of layers, a layer contacting the interface protection electrode 130 among the plurality of layers of the dielectric layer 120 may include an oxide having a perovskite-type crystal structure. For example, in at least one case (e.g., wherein the dielectric layer 120 includes a plurality of layers) at least one of the layers, other than the layer contacting the interface protection electrode 130, may include the metal oxide.
A thickness of the dielectric layer 120 may be, for example, at least about 10 Å but not more than about 100 Å. The thickness of the dielectric layer 120 may be, for example, within a range of about 20 Å to about 50 Å. When the thickness of the dielectric layer 120 is excessively small, a capacity of the capacitor per unit volume may decrease, but when the thickness of the dielectric layer 120 is excessively large, it may be difficult for the capacitor to satisfy a volume required by a memory device.
The interface protection electrode 130 may include an oxide. The interface protection electrode 130 may include an oxide including Mo and/or V. The interface protection electrode 130 may include, for example, MoO2 or VO2. However, the disclosure is not limited thereto, and the interface protection electrode 130 may include an oxide including Ni, Ta, Nb, and/or Fe.
An oxygen atom of the interface protection electrode 130 including an oxide including Mo, V, Ni, Ta, Nb, or Fe may spread to outside the interface protection electrode 130. As the oxygen atom of the interface protection electrode 130 spreads to the outside, the oxygen atom of the dielectric layer 120 may be prevented (and/or mitigated) from being lost to the outside. For example, without being limited to a specific theory, in at least one embodiment, the oxygen atom of the interface protection electrode 130 spreading to the outside may serve to replace an oxygen vacancy in the dielectric layer 120 and/or may introduce lattice strain in the interface between the interface protection electrode 130 and the dielectric layer 120, thereby increasing the energy required for the oxygen atom in the dielectric layer 120 to escape. In this way, the composition (and thereby the crystallinity) of the dielectric layer 120 may be maintained.
Even when the oxygen atom of the interface protection electrode 130 spreads to the outside, the interface protection electrode 130 may have high dielectric property and thus still serve as an electrode.
The interface protection electrode 130 may directly contact the dielectric layer 120. As shown in
The interface protection electrode 130 may include a single layer or a plurality of layers. The interface protection electrode 130 may include a 2-layer structure, a 3-layer structure, a 4-layer structure, etc., without being necessarily limited to such a range, and may have a multi-layer structure including more layers according to required and/or desired performance.
The interface protection electrode 130 may directly contact the second electrode 140. The second electrode 140 directly contacting the interface protection electrode 130 may be an upper electrode as shown. The second electrode 140 may be separated from the first electrode 110 in a vertical direction. Herein, the upper electrode may mean that it is manufactured after the first electrode 110 at a manufacturing stage.
The second electrode 150 may include a conductive material. For example, the conductive material may be the same and/or a similar material as the first electrode 110. For example, the second electrode 140 may include a metal, a metal nitride, a metal oxide, or a combination thereof. The second electrode 140 may include, for example, a metal (such as titanium (Ti), nickel (Ni), aluminum (Al), tantalum (Ta), tungsten (W), platinum (Pt), palladium (Pd), gold (Au), iridium (Ir), rhodium (Rh), Molybdenum (Mo), vanadium (V), niobium (Nb), etc.), a nitride of Ti, a nitride of Ni, a nitride of Al, a nitride of Ta, a nitride of W, a nitride of Pt, a nitride of Pd, a nitride of Au, a nitride of Ir, a nitride of Rh, a nitride of Mo, a nitride of V, or a nitride of Nb, an oxide of Ti, an oxide of Ni, an oxide of Al, an oxide of Ta, an oxide of W, an oxide of Pt, an oxide of Pd, an oxide of Au, an oxide of Ir, an oxide of Rh, an oxide of Mo, an oxide of V, an oxide of Nb, etc., a combination thereof, and/or the like
The capacitor 100 according to at least one embodiment may include the interface protection electrode 130 to prevent the oxygen atom of the dielectric layer 120 from being lost to the outside, thereby suppressing formation of the dielectric layer 120 showing low dielectric characteristics. Moreover, as the space groups of the interface protection electrode 130 and the dielectric layer 120 are shared as a tetragonal system, the crystal structure of the dielectric layer 120 may not be destroyed and reduction of the leakage current and dielectric constant improvement of the capacitor 100 may be achieved at the same time.
Iridium (Ir) is provided as a first electrode. A dielectric layer of BaSrTiO3 is formed on the first electrode, and a second electrode including platinum (Pt) is formed on the dielectric layer to manufacture a capacitor according to Comparative Example 1.
Iridium (Ir) is provided as a first electrode. A dielectric layer including BaSrTiO3 is formed on the first electrode, and an interface protection electrode including MoO2 is formed on the dielectric layer. The second electrode including platinum (Pt) is formed on the interface protection electrode to manufacture a capacitor according to Embodiment 1.
Except that the interface protection electrode including MoO2 is further formed, the capacitor according to Embodiment 1 is manufactured in the same manner as Comparative Example 1.
For the capacitor manufactured in Embodiment 1 and Comparative Example 1, a leakage current is measured for a thickness Toxeq of an equivalent oxide layer, and a result is shown in
In comparison to
Referring to
Referring to
A circuit diagram of a semiconductor device 1000 regards one cell of a memory device (e.g., a dynamic random access memory (DRAM) device), and includes one transistor TR, one capacitor CA, a word line WL, and a bit line BL. The capacitor CA may be the capacitor 100 described above with reference to
A method to write data on a DRAM is as below. After a gate voltage (high) that turns the transistor TR into an ‘ON’ state is applied to a gate electrode through the word line WL, a data voltage VDD (high) or 0 (low) to be input to the bit line BL is applied. When the voltage (high) is applied to the word line and the bit line, the capacitor CA may be charged and data “1” may be recorded, and when the voltage (high) is applied to the word line and a voltage (low) is applied to the bit line, the capacitor CA may be discharged and data “0” may be recorded.
When data is read, the voltage (high) may be applied to the word line WL to turn ON the transistor TR of the DRAM and then a voltage of VDD/2 may be applied to the bit line BL. When data of the DRAM is “1”, that is, the voltage of the capacitor CA is VDD, charges in the capacitor CA may slowly move to the bit line BL such that the voltage of the bit line BL may become slightly higher than VDD/2. On the other hand, when the data of the capacitor CA is “0”, the charges of the bit line BL may move to the capacitor CA such that the voltage of the bit line BL may become slightly lower than VDD/2. An electric potential of the bit line, generated in this way, may be sensed and amplified by a sense amplifier, such that it may be determined whether corresponding data is “0” or “1”.
Referring to
The transistor TR may be a field effect transistor. The transistor TR may include a semiconductor substrate SU, which includes a source region SR, a drain region DR, and a channel region CH, and a gate stack GS, which is provided to face the channel region CH on the semiconductor substrate SU and includes a gate insulating layer GI and a gate electrode GA.
The channel region CH may be a region between the source region SR and the drain region DR and may be electrically connected to the source region SR and the drain region DR. The source region SR may be electrically connected to or contact an end of a side of the channel region CH, and the drain region DR may be electrically connected to or contact an end of the other side of the channel region CH. The channel region CH may be defined as a substrate region between the source region SR and the drain region DR in the semiconductor substrate SU.
The semiconductor substrate SU may include a semiconductor material. The semiconductor substrate SU may include a semiconductor material, for example, silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), indium phosphide (InP), etc. The semiconductor substrate SU may include a silicon-on-insulator (SOI) substrate.
The source region SR, the drain region DR, and channel region CH may be independently formed by injecting impurities to different regions of the semiconductor substrate SU. In this case, the source region SR, the channel region CH, and the drain region DR may include a substrate material as a base material. The source region SR and the drain region DR may be formed of a conductive material. In this case, the source region SR and the drain region DR may include, for example, metal, a metal compound, a conductive polymer, and/or the like.
Unlike what is shown, the channel region CH may be implemented as a separate material layer (thin film). In this case, the channel region CH may include one or more of, for example, Si, Ge, SiGe, III-V semiconductors, oxide semiconductors, nitride semiconductors, oxynitride semiconductors, two-dimensional (2D) materials, quantum dots (QD), and organic semiconductors. The oxide semiconductor may include, for example, InGaZnO, etc. The 2D material may include, for example, transition metal dichalcogenide (TMD) or graphene. The QD may include, for example, a colloidal QD or nanocrystal structure.
The gate electrode GA may be separated from the semiconductor substrate SU to oppose the channel region CH on the semiconductor substrate SU. The gate electrode GA may include at least one of metal, a metal nitride, a metal carbide, and polysilicon. The metal may include at least one of, for example, aluminum (Al), tungsten (W), molybdenum (Mo), titanium (Ti), and tantalum (Ta). The metal nitride may include one or more of, for example, a titanium nitride (TiN) film and a tantalum nitride (TaN) film. The metal carbide may include one or more of, for example, aluminum and a silicon-doped (or contained) metal carbide. The metal carbide may include, for example, TiAlC, TaAlC, TiSiC, or TaSiC.
The gate electrode GA may have a structure in which a plurality of materials are stacked. For example, the gate electrode GA may have a stacked structure of a metal nitride layer/metal layer such as TiN/Al, etc., or a stacked structure of a metal nitride layer/metal carbide layer/metal layer such as TiN/TiAlC/W. The aforementioned materials used in the gate electrode GA are merely examples and the disclosure is not limited thereto.
A gate insulating layer GI may be further arranged between the semiconductor substrate SU and the gate electrode GA. The gate insulating layer GI may include a paraelectric material or a high-k dielectric material. The gate insulating layer GI may have a dielectric constant of, for example, about 20 to about 70.
The gate insulating layer GI may include a silicon oxide, a silicon nitride, an aluminum oxide, a hafnium oxide, a zirconium oxide, etc., and/or include a 2D insulator such as a hexagonal boron nitride (h-BN). The gate insulating layer GI may include, for example, a silicon oxide (SiO2), a silicon nitride (SiNx), etc., and may include a hafnium oxide (HfO2), a hafnium silicon oxide (HfSiO4), a lanthanum oxide (La2O3), a lanthanum aluminum oxide (LaAlO3), a zirconium oxide (ZrO2), a hafnium zirconium oxide (HfZrO2), a zirconium silicon oxide (ZrSiO4), a tantalum oxide (Ta2O5)), a titanium oxide (TiO2), a strontium titanium oxide (SrTiO3), a yttrium oxide (Y2O3), aluminum oxide (Al2O3), a red scandium tantalum oxide (PbSc0.5Ta0.5O3), red zinc niobate (PbZnNbO3), etc. The gate insulating layer GI may include, for example, a metal nitride oxide such as an aluminum oxynitride (AlON), a zirconium oxynitride (ZrON), a hafnium oxynitride (HfON), a lanthanum oxynitride (LaON), an yttrium oxynitride (YON), etc., a silicate such as ZrSiON, HfSiON, YSiON, LaSiON, etc., or an aluminate such as ZrAlON, HfAlON, etc. The gate insulating layer GI may include, for example, the dielectric layer of the above-described capacitor. The gate insulating layer GI may constitute a gate stack together with the gate electrode GA.
One of the electrodes 111 and 141 of the capacitor CA1 and one of the source region SR and the drain region DR of the transistor TR may be electrically connected to each other by one contact 20. The contact 20 may include an appropriate conductive material, e.g., tungsten, copper, aluminum, polysilicon, etc.
An arrangement of the capacitor CA1 and the transistor TR may be changed variously. For example, the capacitor CA1 may be arranged on the semiconductor substrate SU, or may be buried in the semiconductor substrate SU.
Referring to
The transistor TR may include the semiconductor substrate SU including the source region SR, the drain region DR, and the channel region CH therebetween, and the gate stack GS which is arranged to face the channel region CH on the semiconductor substrate SU and includes the gate insulating layer GI and the gate electrode GA.
An interlayer insulating film 25 may be provided to cover the gate stack GS on the semiconductor substrate SU. The interlayer insulating film 25 may include an insulating material. The interlayer insulating film 25 may include an Si oxide (e.g., SiO2), an aluminum oxide (e.g., Al2O3), or a high-k dielectric material (e.g., HfO2). The contact 21 may electrically connect the transistor TR to the capacitor CA1 through the interlayer insulating film 25.
The capacitor CA2 may include a first electrode 112, a dielectric layer 122 provided on the first electrode 112, an interface protection electrode 132 provided on the dielectric layer 121 and including an oxide, and a second electrode 142 provided on the interface protection electrode 132. The first electrode 112 and the second electrode 142 may be provided in a shape enlarging a contact area with the dielectric layer 122 to the maximum, and a material composition of the capacitor CA2 may be substantially the same as (or substantially similar to) the capacitor 100 described with reference to
Referring to
The memory unit 1010, the ALU 1020, and the control unit 1030 may communicate directly by being connected to one another through a metal line on-chip. The memory unit 1010, the ALU 1020, and the control unit 1030 may be monolithically integrated on one substrate to form one chip. An input/output device 2000 may be connected to the electronic device architecture (chip) 1100. The memory unit 1010 may include both a main memory and a cache memory. The electronic device architecture (chip) 1100 may be an on-chip memory processing unit. The memory unit 1010 may include the above-described capacitor and/or the semiconductor device using the same. The ALU 1020 or the control unit 1030 may also include the above-described capacitor and/or the semiconductor device using the same.
Referring to
Depending on a circumstance, the electronic device architecture may be implemented in a form where computing-unit devices and memory-unit devices are adjacent to each other in one chip, without distinction of sub-units.
The capacitor and the semiconductor device including the same according to the disclosure may include the interface protection electrode on the dielectric film, thereby having a high dielectric constant and superior leakage current preventing/reducing characteristics. While the capacitor and the semiconductor device including the same have been described with reference to the embodiments described in the drawings, it will be understood by those of ordinary skill in the art that various modifications and equivalent other embodiments are possible therefrom. Therefore, the disclosed embodiments should be considered in a descriptive sense rather than a restrictive sense. The scope of the present specification is not described above, but in the claims, and all the differences in a range equivalent thereto should be interpreted as being included.
According to a disclosed embodiment, by including an interface protection electrode on a dielectric film, a capacitor having a high dielectric constant and superior leakage current blocking/reducing characteristics may be provided.
The semiconductor device including the capacitor may easily implement high integration, contributing to miniaturization of the electronic device.
It should be understood that the example embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should typically be considered as available for other similar features or aspects in other embodiments. While one or more embodiments have been described with reference to the figures, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined by the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2024-0009793 | Jan 2024 | KR | national |
