Capacitor compensation in miller compensated circuits

Abstract

A Miller-compensated amplifier circuit. The circuit includes an amplifier stage, and a compensation capacitor arranged in parallel with the amplifier stage. A current multiplier circuit path, adapted to multiply a current through the compensation capacitor, includes an inversion stage in the current multiplier circuit path. The inversion stage includes a first current mirror adapted to mirror a first current corresponding to a current through the compensation capacitor, to provide a second current, as well as a second current mirror adapted to mirror and invert the second current to provide a third current and to apply the third current to the amplifier stage. In this way, the circuit is Miller compensated by only a single capacitor that has its capacitance multiplied in accordance with current-mode multiplication.

Description

TECHNICAL FIELD OF THE INVENTION

This invention relates to frequency compensated electronic circuits, and more particularly relates to amplifier circuits having Miller-compensating capacitors.

BACKGROUND OF THE INVENTION

The stability performance of circuits having feedback is improved by providing compensation so as to increase phase margin. A well known technique for improving phase margin takes advantage of the Miller Effect, by adding a Miller-compensating capacitance in parallel with a gain stage, e.g., the output stage of a two stage amplifier circuit. Such a configuration results in the well-known and desirable phenomenon called pole splitting, which advantageously multiplies the effective capacitance of the physical capacitor employed in the circuit. See, e.g., for background on compensation of amplifier circuits using Miller-compensating capacitance, Paul R. Gray and Robert G. Meyer, Analysis and Design of Analog Integrated Circuits, Third Ed., John Wiley & Sons, Inc., New York, 1993, Ch. 9, pp. 607-623.

However, integrated capacitors occupy a relatively large area on an integrated circuit chip, relative to other components such as complementary-metal-oxide-semiconductor (“CMOS”) transistors. The problem becomes worse when the load capacitance seen by a circuit having Miller-compensating capacitance becomes large. This requires the compensating capacitance to increase in value in order to maintain stability. However, the larger compensating capacitance occupies even more physical space. But, this is not a luxury that can be afforded in an environment where more circuits are integrated onto the same die, which, of course, is the trend

A current-mode capacitor multiplier technique has been proposed, in an article entitled, “Active Capacitor Multiplier in Miller-Compensated Circuits,” by Gabriel A. Rincon-Mora, IEEE JSSC, Vol. 35, No. 1, January 2000, at pages 26-32, by which the size of the Miller capacitor can be reduced by a factor equal to the current gain of a new loop added to the circuit.

FIG. 1 is a circuit diagram of a simple amplifier circuit. This circuit has one dominant pole, in the left hand plane, located at: $$ F P1 = - ( g 1 + g 2 ) C c1 , Eq .   ⁢ ( 1 )

where f P1 is the pole frequency, f 01 is the zero frequency, g i is the conductance (i.e., inverse of output resistance 1/R 0 ) of transistor Mi, and C c1 is the value of the compensating capacitor.

FIG. 2 is a circuit diagram of a simple amplifier circuit like that of FIG. 1 , but modified using the technique described in the Rincon-Mora article. The added current gain loop consisting of current source I and transistor M 5 can be seen in the figure. The circuit has one dominant pole and one dominant zero. The pole and the zero are both in the left half plane (“LHP”), and they are located at: $$ f P2 = - gm 5 ⁡ ( g 3 + g 2 ) C c2 ⁡ ( gm 4 + gm 5 ) ⁢   ⁢ and Eq .   ⁢ ( 2 ) f 02 = - gm 5 C c2 , ⁢   Eq .   ⁢ ( 3 )

where f P2 is the pole frequency, f 02 is the zero frequency, gm i is the transconductance of transistor Mi, C c2 is the value of the compensating capacitor, and other values are as defined above. In this circuit, there is an effective capacitor multiplication of: $$ C eq = C c2 ⁡ ( 1 + gm 4 gm 5 ) . Eq .   ⁢ ( 4 )

This is the basic principle of the technique discussed in the Rincon-Mora article.

However, an aspect of the technique discussed in the Rincon-Mora article is that a second capacitor is used to stabilize the amplifier that is discussed in that article, which is more complex than the amplifier discussed above and more typical of amplifiers used in applications such as amplifiers, LDOs and regulators. Another aspect is that the LHP zero reduces the gain margin, and can be a source of long settling time constants. It would therefore be desirable to provide Miller compensation of circuits with capacitor multiplication, but with only a single capacitor. It would also be desirable to provide Miller compensation of circuits with capacitor multiplication, with improved gain margin.

SUMMARY OF THE INVENTION

In accordance with the invention there is provided a Miller-compensated amplifier circuit. The circuit includes an amplifier stage, and a compensation capacitor arranged in parallel with the amplifier stage. A current multiplier circuit path, adapted to multiply a current through the compensation capacitor, includes an inversion stage in the current multiplier circuit path. The inversion staae includes a first current mirror adapted to mirror a first current corresponding to a current throuuh the compensation capacitor, to provide a second current, as well as a second current mirror adapted to mirror and invert the second current to provide a third current and to apply the third current to the amplifier stage. In this way, the circuit is Miller compensated by only a single capacitor that has its capacitance multiplied in accordance with current-mode multiplication. The invention is applicable to single stage amplifiers, as well as multi-stage amplifiers, low drop-outs (“LDOs”) and regular circuits, having Miller compensation.

These and other features of the invention will be apparent to those skilled in the art from the following detailed description of the invention, taken together with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram of a first prior art compensation circuit.

FIG. 2 is a circuit diagram of a second prior art compensation circuit.

FIG. 3 is a circuit diagram of a first prior art amplifier circuit, having Miller compensation.

FIG. 4 is a graph of the gain and phase, with frequency, of the amplifier circuit of FIG. 3 .

FIG. 5 is a circuit diagram of a second prior art amplifier circuit, having Miller compensation.

FIG. 6 is a graph of the gain and phase, with frequency, of the amplifier circuit of FIG. 5 .

FIG. 7 is a circuit diagram of an amplifier circuit according to a first preferred embodiment of the present invention.

FIG. 8 is a graph of the gain and phase, with frequency, of the amplifier circuit of FIG. 7 .

FIG. 9 is a is a circuit diagram of an amplifier circuit according to a second preferred embodiment of the present invention.

FIG. 10 is a graph of the gain and phase, with frequency, of the amplifier circuit of FIG. 9 .

FIG. 11 is a circuit diagram of a preferred design for amplifier 901 of FIG. 9 .

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

The numerous innovative teachings of the present invention will be described with particular reference to the presently preferred exemplary embodiments. However, it should be understood that this class of embodiments provides only a few examples of the many advantageous uses and innovative teachings herein. In general, statements made in the specification of the present application do not necessarily delimit the invention, as set forth in different aspects in the various claims appended hereto. Moreover, some statements may apply to some inventive aspects, but not to others.

In order to more clearly understand the principles applied in constructing the preferred embodiments discussed herein, certain prior art amplifier circuits will now be discussed. FIG. 3 is a circuit diagram of a prior art two-stage, Miller-compensated amplifier circuit 300 , having a Class A output stage. In the amplifier, a bias current I BIAS is provided to the drain of a positive-type metal oxide semiconductor (“PMOS”) transistor M 1 , which is mirrored by PMOS transistors M 2 , M 3 , M 4 , M 5 , M 6 and M 7 , to provide I BIAS currents for sourcing to the circuit. A negative-type metal oxide (“NMOS”) semiconductor transistor M 8 mirrors I BIAS currents to NMOS transistors M 9 and M 10 , for sinking from the circuit. An NMOS semiconductor transistor M 11 also mirrors I BIAS currents, to NMOS transistor M 12 , for sinking from the circuit, and an NMOS semiconductor transistor M 13 also mirrors I BIAS currents, to NMOS transistor M 14 , for sinking from the circuit.

PMOS transistors M 15 and M 16 form an input differential pair, receiving differential input voltages INM and INP. PMOS transistors M 19 , M 20 , M 21 and M 22 , provide a cascoded current mirror that acts as the differential to single ended converter for the first stage. NMOS transistors M 17 and M 18 , are cascoded devices and serve two purposes: first, they function to increase the gain of the stage, and second, they are required in the “folded cascode” architecture to create the current summing junctions at their sources.

PMOS transistor M 27 provides the second, Class A output stage of the amplifier, the output of the amplifier circuit being taken from the drain thereof. Miller compensation is provided by capacitor C 3 and resistor R 3 connected in series between the output of the amplifier circuit and the signal path connection node between the first stage and the second stage, as shown.

In amplifier circuit 300 of FIG. 3 , a typical value for capacitor C 3 could be 15 pF, while a typical value for resistor R 3 in such a circuit could be 1.4 kΩ. Together, the capacitor and resistor could use 3,500 μm of silicon area, in a 0.18 μm process, using a dense linear capacitor structure and a silicide blocked poly resistor.

FIG. 4 is a diagram in which two graphs are superimposed, one of phase, in degrees, and the other of gain, in dB, both versus frequency, in Hertz. The gain plot 41 shows the gain of a typical implementation of amplifier 300 , having the capacitor and resistor values mentioned in the previous paragraph, while the phase plot 42 shows the output phase for the same amplifier. For the amplifier having the parameters shown in FIG. 4 , the unity gain bandwidth (“UGBW”) is 2.16 MHz, the phase margin (“PM”) is 78° and the gain margin (“GM”) is 21 dB.

FIG. 5 is a circuit diagram of an amplifier 500 like that shown in FIG. 3 , but modified in accordance with the technique described in the Rincon-Mora article, mentioned above. Components in FIG. 5 having the same reference labels as those in FIG. 3 function similarly. It can be seen that in FIG. 5 , the resistor has been eliminated and two capacitors, C 5 a and C 5 b , are now provided. Capacitor C 5 a is connected between the signal path connection node between the first stage and the second stage, and the common connection node of the gates of transistors M 13 and M 14 . Capacitor C 5 b is connected between the output node and the output of the amplifier and the common connection node of the gates of transistors M 11 and M 12 . Assuming the common components of the circuits of FIG. 3 and are of the same construction, the sum of the values of capacitors C 5 a and C 5 b could be 9.25 pF, which could use 2,100 μm of silicon area in the process mentioned above, again using a dense linear capacitor structure. This is an improvement over the circuit of FIG. 3 , but the circuit uses multi-path compensation, and the second path, through capacitor C 5 b , is not Miller multiplied.

FIG. 6 shows two graphs like those shown in FIG. 4 , but for amplifier circuit 500 . The effects on the gain 61 and output phase 62 of the LHP zero are shown in circled area 63 .

In general, in applying the principles of the present invention, an additional inversion is provided to one of the feedback paths. Specifically, an inversion is provided in a current-mode capacitor multiplier circuit branch that is in parallel with an amplifier stage. This allows the use of only a single capacitor in applying current-mode capacitor multiplication in Miller-compensated circuits. The principles are applicable to single stage amplifier circuits, as well as multi-stage amplifier circuits.

FIG. 7 is a circuit diagram of an amplifier 700 like that shown in FIG. 3 , but modified in accordance with the principles of the present invention to provide a first preferred embodiment thereof. In the amplifier 700 , only capacitor C 7 is required for comparable compensation to that in amplifier 500 , and the capacitance of capacitor C 7 is both Miller multiplied as well as further multiplied by current-mode capacitor multiplication. Components in FIG. 7 having the same reference labels as those in FIG. 5 function similarly. It can be seen that in FIG. 7 , PMOS transistor M 28 replaces transistor M 7 . However, transistor M 28 does not have its gate connected to the gate of transistor M 1 , but, rather, additional NMOS transistor 29 and additional PMOS transistor M 30 are provided, with transistors M 28 and M 30 having their gates connected together and to the drain of transistor M 30 , with transistor M 29 configured to mirror the I BIAS current in transistor M 8 for sinking from transistor M 30 . The compensation capacitor C 7 is connected between the output of the amplifier circuit 700 and the common connection node of transistors M 29 and M 30 . Thus, an additional inversion has been provided, in the feedback path from the output of the amplifier circuit 700 through transistors M 30 , M 28 , M 13 , M 14 , M 18 , and M 27 , which includes the compensation capacitor C 7 . In other words, an inversion is provided in a current-mode capacitor multiplier circuit branch that is in parallel with an amplifier stage. Note that transistors M 28 , M 29 , and M 30 , can be minimally sized and use minimal current, so this technique is readily useable in low power circuit applications. For example, a total additional current from such an added inversion circuit branch of, say, ten μA, or lower, is readily achievable in integrated circuit processes in use today.

FIG. 8 shows two graphs like those shown in FIG. 4 , but for amplifier circuit 700 . The effect on the gain 81 (and output phase 82 ) of the LHP zero is shown in circled area 83 . It can be seen that the LHP zero still reduces the gain margin of the circuit, as it does in amplifier circuit 500 .

Assuming the common components of the circuits of FIGS. 5 and 7 are of the same construction, the value of capacitor C 7 could be 1.25 pF, which could use merely 300 μm of silicon area in the process mentioned above, again using a dense linear capacitor structure. This is a considerable improvement over the circuit of FIG. 5 , since the additional silicon area required by transistors M 29 and M 30 is much less than the reduction in silicon area required for compensation capacitors, as compared with amplifier 500 .

To further improve the performance of amplifiers constructed in accordance with the inventive principles, especially in high precision applications at high frequencies, it is desirable that the LHP zero of such circuits be placed at a sufficiently high frequency. In accordance with a further preferred embodiment of the present invention, the transconductance, gm, of the current gain path of the amplifier circuit is increased. Recall from Equation (3) that, for the example discussed in connection with FIG. 2 , the frequency of the LHP zero, f 02 , is −gm 5 /C c2 . For amplifier circuit 700 , the frequency, f 07 , of the LHP zero is: $$ f 07 = g ⁢   ⁢ m M13 ⁡ ( gm M30 gm M28 ) C7 , Eq .   ⁢ ( 5 )

where gm Mi is the transconductance of transistor Mi in FIG. 7 , and C 7 is the value of capacitor C 7 .

Now, the transconductance value of transistor M 13 can be increased using conventional techniques, i.e., by increasing power and/or area. However, a more elegant way of increasing the frequency of the LHP zero will now be described. FIG. 9 is a circuit diagram of an amplifier 900 like that shown in FIG. 7 , but showing a second preferred embodiment of the present invention. Components in FIG. 9 having the same reference labels as those in FIG. 7 function similarly. In amplifier circuit 900 , compared with amplifier circuit 700 , it can be seen that a small amplifier 901 has been added, having a non-inverting input connected to the common node of transistors M 29 and M 30 , and having an inverting input connected to the gate of transistor M 1 . An additional PMOS transistor M 31 is also provided, having its gate connected to the gate of transistor M 1 , to source a current bias of I BIAS to amplifier 901 . Here again, amplifier 901 can be very small (e.g., <200 μm 2 ) and be designed to draw very little current (e.g., <50 μA), in integrated circuit processes in use today. The function of amplifier 901 is to allow transistors M 28 and M 30 to operate as a current mirror, while increasing the transconductance of transistor M 30 . From Equation (5), it can be seen that this moves the LHP zero to a higher frequency.

The effect of amplifier 901 on the transconductance gm M30 of transistor M 30 is to increase it by the open loop gain of the amplifier, causing the desired effect. The frequency f 09 of the resulting LHP zero is: $$ f 09 = ( - gm M13 C9 ) · ( gm M30 · A AMP gm M28 ) , Eq .   ⁢ ( 6 )

where C 9 is the value of capacitor C 9 , and A AMP is the voltage gain of amplifier 901 . FIG. 10 shows two graphs like those shown in FIG. 8 , but for amplifier circuit 900 , in which the components in FIG. 9 having the same reference labels as those in FIG. 7 are of the same construction as those in FIG. 7 , and in which the gain A of amplifier 901 is approximately 40 dB. The gain is represented by curve 101 and the output phase by curve 102 . It can be seen that the frequency f 09 of the LHP zero is significantly increased, due to the multiplying factor of the gain of amplifier 901 , as shown in Equation (6). In addition, the unity gain bandwidth is approximately 2.8 MHz, while the phase margin is approximately 90°, with a gain margin <−100 dB.

The amplifier 901 can be of any conventional construction, but preferably is a single-stage, high bandwidth design. FIG. 11 is a circuit diagram of a preferred design for amplifier 901 , comprising transistors Ma through Mf. While preferred in this embodiment, it can be seen that amplifier 901 is of conventional design. In the process mentioned above, using very small devices and approximately 50 μA of current, such an amplifier can be made to occupy approximately 105 μm 2 .

In conclusion, embodiments of the present invention have been shown for use in connection with Miller compensated circuits, in which the value of a Miller-compensating capacitor is not only Miller multiplied, but further multiplied, as well, but only using a single compensating capacitor. Significant improvements over the prior art in use of silicon area are possible, while providing comparable, or even improved performance. Significant improvements in high frequency performance are possible in some embodiments, requiring the additional consumption of only a small current, which can be of the order of tens of ramps.

Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. An operational amplifier circuit; comprising:a first amplifier stage; a second amplifier stage; a compensation capacitor arranged in parallel with the second amplifier stage; a current multiplier circuit path, adapted to multiply a current through the compensation capacitor; and an inversion stage in the current multiplier circuit path, comprising a first current mirror adapted to mirror a first current corresponding to a current through the compensation capacitor, to provide a second current; and a second current mirror adapted to mirror and invert the second current to provide a third current and to apply the third current to the amplifier stage.

2. An operational amplifier according to claim 1, further comprising an amplifier adapted to increase the transconductance of the first current mirror, to thereby increase the frequency of a left half plane zero of the operational amplifier circuit.

3. An operational amplifier circuit, comprising:an amplifier stage; a compensation capacitor arranged in parallel with the amplifier stage; a current multiplier circuit path, adapted to multiply a current through the compensation capacitor; and an inversion stage in the current multiplier circuit path, comprising a first current mirror adapted to mirror a first current corresponding to a current through the compensation capacitor, to provide a second current; and a second current mirror adapted to mirror and invert the second current to provide a third current and to apply the third current to the amplifier stage.