Claims
- 1. A buffer circuit having an input signal lead for receiving an input signal, an output signal lead for providing an output signal, a first voltage supply terminal, and a second voltage supply terminal, comprising:
- first, second and third transistors;
- said first transistor having a first current handling terminal, a control terminal, and a second current handling terminal connected to the second voltage supply terminal;
- load means connecting the first voltage supply terminal and first current handling terminal of the first transistor;
- said second transistor having a first current handling terminal connected to said first voltage supply terminal, a control terminal connected to the first current handling terminal of the first transistor, and a second current handling terminal;
- said third transistor having a first current handling terminal connected to the second current handling terminal of the second transistor, a control terminal, and a second current handling terminal connected to the second voltage supply terminal;
- the control terminals of the first and third transistors being connected to the input signal lead;
- a capacitor having a pair of terminals, one terminal connected to the first current handling terminal of the third transistor, and the other terminal connected to the output signal lead; and
- a load device coupled between the respective second current handling terminals of the first and third transistors and the second voltage supply terminal.
- 2. The structure as in claim 1 and further comprising a load device connected between the one terminal of the capacitor and the output signal lead, in parallel with the capacitor.
- 3. The structure of claim 1 and further comprising a third voltage supply terminal, and a load device as part of the connection between the third voltage supply terminal and output signal lead.
- 4. A buffer circuit having an input signal lead for receiving an input signal, an output signal lead for providing an output signal, a first voltage supply terminal, and a second voltage supply terminal, comprising:
- first, second and third transistors;
- said first transistor having a first current handling terminal, a control terminal, and a second current handling terminal connected to said second voltage supply terminal;
- load means connecting said first voltage supply terminal and said first current handling terminal of said first transistor;
- said second transistor having a first current handling terminal connected to said first voltage supply terminal, a control terminal connected to the first current handling terminal of the first transistor, and a second current handling terminal;
- said third transistor having a first current handling terminal connected to the second current handling terminal of the second transistor, a control terminal, and a second current handling terminal coupled to the second voltage supply terminal;
- the control terminals of the first and third transistors being connected to the input signal lead;
- a first load device connecting the first current handling terminal of the third transistor and the output signal lead; and
- further comprising a second load device connected between the respective second current handling terminals of the first and third transistors, and the second voltage supply terminal.
Parent Case Info
This application is a continuation of application Ser. No. 07/051,986, filed 05/19/87 now U.S. Pat. No. 4810905.
US Referenced Citations (8)
Continuations (1)
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51986 |
May 1987 |
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