Claims
- 1. A capacitor structure, comprising:a bottom plate and a top plate, said top plate having a perimeter wherein an area of said top plate is less than an area of said bottom plate; a dielectric layer in between said bottom plate and said top plate; and at least one insulating sidewall spacer placed against said perimeter of said top plate and overlaying a portion of said dielectric layer.
- 2. The capacitor structure of claim 1, and further comprising:a substrate underlying said bottom plate; and a conductor embedded in said substrate and underlying said bottom plate.
- 3. The capacitor structure of claim 2, wherein said conductor comprises copper damascene.
- 4. The capacitor structure of claim 3, said bottom plate further comprising a conductive barrier layer in contact with said conductor.
- 5. The capacitor structure of claim 1, wherein each of said bottom plate and said top plate comprises a metal plate.
- 6. The capacitor structure of claim 1, wherein said dielectric layer comprises silicon dioxide.
- 7. The capacitor structure of claim 1, and further comprising an insulating cap overlaying said top plate.
- 8. The capacitor structure of claim 7, wherein said insulating cap has a perimeter coextensive with said top plate, and wherein said at least one insulating sidewall spacer is placed against said perimeter of said insulating cap.
- 9. The capacitor structure of claim 1, wherein said dielectric layer has a top surface on which said at least one insulating sidewall spacer is formed.
- 10. The capacitor structure of claim 9, wherein said at least one insulating sidewall spacer overlays a portion of said bottom plate.
- 11. The capacitor structure of claim 1, wherein said dielectric layer has a top surface on which said at least one insulating sidewall spacer is formed.
- 12. The capacitor structure of claim 1, wherein said at least one insulating sidewall spacer overlays a portion of said bottom plate.
- 13. A capacitor structure, comprising:a bottom plate and a top plate, said top plate having a perimeter; a dielectric layer in between said bottom plate and said top plate; at least one insulating sidewall spacer placed against said perimeter of said top plate and overlaying a portion of said dielectric layer; a substrate underlying said bottom plate; and a copper damascene conductor embedded in said substrate and underlying said bottom plate.
CROSS-REFERENCE TO RELATED APPLICATION
This application is related to Ser. No. 09/298,122, “Metal-Insulator-Metal Capacitor for Copper Damascene Process and Method of Forming the Same,” filed Apr. 23, 1999, and incorporated herein by reference.
US Referenced Citations (12)
Non-Patent Literature Citations (2)
Entry |
IBM Technical Disclosure Bulletin, “Single-Device DRAM Cell Using Butted Plate,” vol. 27, No. 12, May 1985, pp. 7270-7271.* |
IBM Technical Disclosure Bulletin, “Single-Device DRAM Cell Using Butted Plate,” vol. 27, No. 12, May 1985, pp. 7270-7271. |