Patent Application
20080054310
Other advantages and features will become more clearly apparent from the following description of particular embodiments of the invention given as non-restrictive examples only and represented in the accompanying drawings, in which:
The capacitor-less DRAM memory cell comprises a partially-depleted MOSFET device 1 represented in
As represented in
The source and drain electrodes 4 and 5 are doped by the first type of dopant. The source and drain electrodes 4 and 5 and the channel 2 are for example formed in an active layer laterally delimited by insulating elements 9.
The gate insulator 8 comprises a first part 8a corresponding to the first doped zone 3a and a second part 8b corresponding to the second doped zone 3b of the gate 3.
In the particular embodiment represented in
For example, the first part 8a of the gate insulator 8 has a thickness Ea comprised between 1.2 nm and 7 nm, and preferably between 2 nm and 5 nm, and the second part 8b of the gate insulator 8 has a thickness Eb comprised between 1 nm and 2.2 nm.
The first and second parts 8a and 8b of the gate insulator 8 can for example be formed by the same material, for example by a material comprised in the group containing silicon oxide SiO2, carbonaceous silicon oxides SiOC, hydrocarbonaceous silicon oxides SiOCH and nitrided silicon oxide SiON or hafnium oxide HfON.
The first part 8a of the gate insulator 8 therefore has a higher tunnel resistance than the second part 8b of the gate insulator 8. Due to the larger thickness Ea of the first zone 8a of the gate insulator 8, higher voltages can be used, in particular for analog applications, without causing tunnel currents through the first part 8a of the gate insulator, whereas the tunnel junction corresponding to the second doped zone 3b of the gate 3 is adjusted by the thickness Eb of the second part 8b of the gate insulator 8 to enhance the tunnel current, independently from the first part 8a.
The direct tunnel effect between the second doped zone 3b of the gate 3 and the channel 2 is enhanced by the reduction of the thickness Eb of the second part 8b of the gate insulator 8 or by the choice of a dielectric with a weaker dielectric constant or a smaller barrier height for the second part 8b of the gate insulator 8 than the dielectric of the first part 8a of the gate insulator 8.
In prior art devices, if the supply voltage is high, the thickness of the dielectric has to be increased for the latter not to be damaged, but there is then no longer any conduction by tunnel effect as the dielectric is too thick.
The first part 8a of the gate insulator 8 can have a higher dielectric constant than the second part 8b of the gate insulator 8. The first part 8a of the gate insulator 8 can for example be made of a material with a high dielectric constant (high K type), for example a material comprised in the group containing hafnium oxide HfO2, hafnium silicates HfSiOx (x being comprised between 1 and 3) and nitrided silicon oxide SiON. The second part 8b of the gate insulator 8 can for example be made of a material comprised in the group containing silicon oxide SiO2, carbonaceous silicon oxides SiOC and hydrocarbonaceous silicon oxides SiOCH.
In a preferred embodiment, the first part 8a of the gate insulator 8 is made of SiO2 and has a thickness comprised between 2 nm and 3 nm, and the second part 8b of the gate insulator 8 is also made of SiO2 and has a thickness comprised between 1 nm and 1.5 nm.
In another embodiment, the first part 8a of the gate insulator 8 is made of a high dielectric constant material and has a thickness comprised between 2 nm and 6 nm and preferably 2.5 nm, and the second part 8b of the gate insulator 8 is made of SiO2 and has a thickness comprised between 1 nm and 2.2 nm and preferably 1.5 nm.
Depending on the supply voltages used, different choices can be envisaged for the materials and their thicknesses. For a supply voltage of the circuits of 1V, the first part 8a of the gate insulator 8 can for example be made of HfO2 with a thickness of 3 nm, and the second part 8b of the gate insulator 8 can be made of SiO2 with a thickness of 1.9 nm.
For a supply voltage of the circuits of 1.2V, the first part 8a of the gate insulator 8 can for example be made of SiON with a thickness of 2.7 nm, and the second part 8b of the gate insulator 8 can be made of SiO2 with a thickness of 1.9 nm.
For a supply voltage of the circuits of 2.5V, the first part 8a of the gate insulator 8 can for example be made of SiO2 with a thickness of 5 nm, and the second part 8b of the gate insulator 8 can be made of SiO2 with a thickness of 2.2 nm. The SiO2 can contain a small quantity of nitrogen (a few %) in order to increase the quality of the dielectric.
The thicknesses Ea and Eb and/or the materials of the first (8a) and second (8b) part of the gate insulator 8 can for example be determined by means of simulations or theoretical calculations, known to the person skilled in the art. Theoretical calculations can for example be made from direct tunnel effect or Fowler-Nordheim tunnel effect conduction models. It is also possible to determine the thicknesses Ea and Eb and/or the materials of the first (8a) and second (8b) part of the gate insulator 8 by means of experimental tests based on assemblies of capacitor or transistor type by measuring current-voltage or capacitance-voltage characteristics. For example, a leakage current density of 800 pA/μm2 is sufficient under a voltage of 1V to regulate the channel potential from a tunnel current through a nitrided silicon oxide with a thickness of 1.9 nm arranged between an N type monocrystalline silicon layer and N+ type polysilicon. This tunnel current is generated by the electrons accumulated in the N+ type polysilicon passing into the N type monocrystalline silicon layer.
In the particular embodiment represented in
For example, the first part 8a can be made from silicon oxide SiO2 and the second part 8b can be made from an oxide with a high dielectric constant, for example HfO2, the two parts 8a and 8b having the same thickness, for example 2 nm. The conduction by direct tunnel effect of the second part 8b is in this case several decades greater than that of the first part 8a. The first part 8a of the gate insulator 8 therefore has a higher tunnel resistance than the second part 8b of the gate insulator 8.
The common element of the different embodiments is the fact that the first part 8a and the second part 8b of the gate insulator 8 are distinct. They are in fact differentiated in particular by their thickness and/or by their material. The device according to the invention can be fabricated by means of the techniques usually used in microelectronics, such as resist depositions, lithographies and ion implantations.
Such a device is partially known from the document U.S. Pat. No. 6,693,328 which describes the use of the gate in order to introduce an electron leakage tunnel current to the channel. This document does not discloses or suggest the use of a MOSFET device as a memory cell.
The MOSFET device according to the invention constitutes a capacitor-less DRAM memory cell (or “1T DRAM”). In this memory cell, data storage within the device is performed by means of the floating substrate effect of the MOS transistors achieved with a partially-depleted SOI technology.
Conventionally, this type of capacitor-less memory cell, is preferably achieved by means of NMOS transistors. In this type of memory cell, charge carriers (holes for an NMOS transistor) are injected into the neutral zone of the floating substrate. These carriers, confined in a region bounded by the buried oxide, the gate oxide and the source and drain junctions, accumulate in the floating substrate and modify its potential. This potential increases in the case of an NMOS transistor, directly connecting the source/floating substrate junction. The threshold voltage of the transistor is thus reduced and the drain current increases. In this case, the floating substrate is used as a memory charge storage zone. This stored charge (1 state of the memory) can be evacuated by forward biasing of the drain/substrate junction. The 0 state of the memory corresponds to the absence of charge in the floating substrate.
Unlike capacitor-less memory cells of known type where charge creation in the floating substrate is performed by collision ionization (“A SOI capacitor-less 1T-DRAM Concept”, S. Okhonin et al. Proc. of the IEEE International SOI Conf, p. 153, 2001) thus favoring the use of NMOS transistors, the use of a transistor comprising a zone having a lower tunnel resistance easily allows charges to be introduced into the floating substrate by this zone. With the device according to the invention on the other hand, it is preferable to use a PMOS device.
The read phase is typically performed by turning the transistor to the On state, i.e. for example, for a PMOS device, by applying a potential of about −0.1V to the drain and a potential of about −0.6V to the gate, the source being arbitrarily fixed at 0. The potential difference existing between the gate and source is lower than the threshold potential difference above which a sufficient direct tunnel current is created to introduce charges into the floating substrate. This threshold potential difference is linked to the tunnel resistance of the gate insulator 8 and translates the potential difference for which the direct tunnel current presents an important effect on the characteristics of the device. In general manner, the sign of the potential differences between the transistor electrodes and the precise amplitudes of these differences depend on the type of device (NMOS or PMOS) and on the technological node used.
Write of a “1” is performed by introducing charges, here electrons, originating from the second doped zone 3b of the gate 3 into the floating substrate through the second part of the gate insulator 8b. The second doped zone 3b is preferably used as it presents a lower tunnel resistance than the first doped zone. This write phase of a “1” is performed for example by applying a potential of about −1V to the gate, and of −0.1V to the drain, the source being arbitrarily fixed at 0, i.e. by applying a voltage Vgs of −1V between the gate and source and a voltage Vds of −0.1V between the drain and source. In schematic manner, the potential conditions taken are as for a read, but the amplitude of the potential difference between the source and gate is increased, for example by about 50%, or by applying a potential difference about 10 times greater between the gate and drain than between the source and drain which is also equivalent in this configuration by applying a potential difference about 10 times greater between the gate and source than between the source and drain. This increase of the potential difference enables a potential difference to be obtained between the gate and source that is greater than the threshold potential difference, thereby enabling a sufficient direct tunnel current to be created, from the gate 3, to induce charges in the floating substrate.
Moreover, for a PMOS device, write of a “0” is performed for example by fixing the source and gate at the same potential, for example 0, and fixing the drain at 0.1V. In general manner, write of a “0” is performed by applying a potential difference of the same amplitude between the source and drain but of opposite sign to that of read or write of a “1”. The drain/floating substrate junction is therefore forward biased. The charges stored in the floating substrate are therefore evacuated.
The retention phase is performed in conventional manner without applying a potential difference between the different electrodes.
| Number | Date | Country | Kind |
|---|---|---|---|
| 06/07691 | Sep 2006 | FR | national |
| 07/03486 | May 2007 | FR | national |
