Patent Application
20080173864
The present invention relates generally to nanoscale electronic devices. More particularly, the preferred embodiments relate to a carbon nanotube transistor in which portions of the CNT close to source and drain electrodes are coated with a highly conductive material (e.g. metallic-conducting nanotubes). The conductive material reduces the electrical resistance of the nanotube transistor.
In recent years, nanoscale transistors made of carbon nanotubes (CNTs) have attracted intense interest. CNT transistors have the potential to dramatically reduce the size, cost and operating power of electronic devices. An exemplary conventional CNT transistor is illustrated in
The performance of the CNT transistor is strongly affected by a gate-source fringe capacitance 28 and a drain-gate fringe capacitance 30. These fringe capacitances 2830 reduce the switching speed of the transistor, which of course is undesirable. The fringe capacitances 2830 depend greatly upon the shapes of the gate, source and drain electrodes, and the spacing between them. In CNT transistor devices, the fringe capacitances tend to be very large because the gate, source and drain are located very close together. For example, even though carbon nanotubes have intrinsically higher electron and hole mobilities than silicon, the electrical performance of carbon nanotube transistors tends to be worse than silicon transistors because of the fringe capacitances 2830. Hence, for CNT transistors to have superior performance compared to silicon devices (a benchmark for economic viability), the fringe capacitances must be reduced.
Another problem with the device of
It would be an advance in the art of CNT transistors and nanoscale electronic devices to provide a CNT transistor structure that avoids the described tradeoffs between fringe capacitance and CNT resistance. Such a device could have very low values of both fringe capacitance and CNT resistance, and therefore exceptionally fast switching speeds and high performance generally. Such a device could exceed the performance characteristics of silicon transistors.
The preferred embodiments of the present invention provide a carbon nanotube (CNT) transistor having source and drain electrodes, and a semiconducting CNT connected between the source and drain. A gate electrode is disposed proximate to the semiconducting CNT, for modulating the resistance thereof. The gate is spaced apart from the source and drain; the source and gate define a first gap, and the drain and gate define a second gap. The semiconducting CNT spans both gaps. Significantly, in the present invention, the transistor has a source extension extending from the source, and/or a drain extension extending from the drain. The extensions span at least a portion of the gaps (e.g. at least ½ way across the gaps). The extensions are electrically conductive, and tend to shunt current away from the semiconducting CNT. The extensions reduce the source-drain resistance of the present transistor, and allow the source and drain to be spaced far from the gate thereby decreasing the fringe capacitance.
The extensions preferably comprise metallic conductive carbon nanotube surrounding and coaxial with the semiconducting CNT. The semiconducting CNT comprises a single-walled carbon nanotube (SWNT); the extensions can comprise 1-30 nanotubes coaxial with the semiconducting CNT, for example.
The extensions can also comprise deposited metal, such as copper, aluminum or the like.
Preferably, the extensions are narrow in a direction perpendicular to the semiconducting CNT (i.e. the Y-direction, see
The above and/or other aspects, features and/or advantages of various embodiments will be further appreciated in view of the following description in conjunction with the accompanying figures. Various embodiments can include and/or exclude different aspects, features and/or advantages where applicable. In addition, various embodiments can combine one or more aspect or feature of other embodiments where applicable. The descriptions of aspects, features and/or advantages of particular embodiments should not be construed as limiting other embodiments or the claims.
The preferred embodiments of the present invention are shown by a way of example, and not limitation in the accompanying figures, in which:
a-4d illustrate a preferred method for fabricating the CNT transistor from a multiwalled carbon nanotube;
a-5e illustrate a method for fabricating the CNT transistor with extensions made of metal; and
While the present invention may be embodied in many different forms, a number of illustrative embodiments are described herein with the understanding that the present disclosure is to be considered as providing examples of the principles of the invention and that such examples are not intended to limit the invention to preferred embodiments described herein and/or illustrated herein.
In relation to the preferred embodiments the following terminology is employed.
Carbon nanotube (CNT): An approximately 1-dimensional nanostructure comprising one or more coaxial graphite tubes. Carbon nanotubes in the present invention can have diameters of about 1-100 nanometers, and 1-50 graphite layers. The diameter and number of graphite layers of the carbon nanotube may vary over its length. Also, a carbon nanotube in the present transistor structure may comprise a plurality or many parallel (i.e., non-coaxial) carbon nanotubes (i.e., a nanotube ‘rope’).
The preferred embodiments of the present invention provide a CNT transistor with relatively low values of fringe capacitance (i.e., gate-source capacitance, and gate-drain capacitance) and source-drain resistance (i.e., CNT resistance). The present transistor structure has source and drain electrodes and a semiconducting CNT connected between the source and drain. A gate is disposed close to the CNT and controls the resistance of the CNT, as known in the art. In the preferred present transistor structure, there is a gap between the gate and source and a gap between the gate and drain. The CNT spans both gaps. In the gap regions, the CNT is covered with conductive extensions (e.g. additional carbon nanotubes) extending from the source or drain (a source extension and a drain extension). The source and drain extensions shunt electrical current and thereby reduce the electrical resistance of the CNT in the gap region, without significantly increasing the fringe capacitance. Hence, the present CNT transistor structure has exceptionally low values of both fringe capacitance and electrical resistance.
In the preferred present transistor structure, a first gap 35a and a second gap 35b are relatively large (compared to similar prior art devices), which provides low fringe capacitance 2830 values. For example, the gaps can be about 0.1 microns or less wide (in the X-direction). Significantly, in the present invention, a source extension 36a extends from the source 22 and covers a portion of the CNT 20 in the first gap 35a; also, a drain extension 36b extends from the drain 24 and covers a portion of the CNT 20 in the second gap 35b. The extensions 36a 36b are electrically conductive and electrically connected to the source and drain, respectively.
The extensions 36a 36b are made of a highly conductive material such as metallic carbon nanotubes, or sputtered or electroplated metal such as Ti, W, or Pt. In a preferred embodiment, the extensions 36a 36b comprise multi-walled carbon nanotubes surrounding and coaxial with the semiconducting CNT 20. In other words, the semiconducting CNT 20 can be a central single-walled nanotube extending from the center of the extensions 36a 36b. The CNT 20 can be a single-walled nanotube that is highly doped with N-type dopant or P-type dopant so that contact between the extension 36a/36b and the CNT 20 is ohmic contact. In this case, the semiconducting CNT 20 has fewer numbers of walls of nanotubes than the extensions 36a 36b. Since the extensions 36a 36b are metal and the CNT 20 is semiconductor, the extensions 36a 36b have a resistance per unit length much lower than the CNT 20. For example, the extensions 36a 36b can have a resistance per unit length less than 1/50, 1/100, or 1/500 the resistance per unit length of the CNT 20. For example, each extension 36a 36b can have a resistance of about 50-500 ohms, and the semiconducting CNT (between the extensions) can have a resistance of about 10 k-30 k ohms.
The extensions 36a 36b at least partially cover the CNT in the gaps 35a 35b. Preferably, the extensions 36a 36b are at least ¼, ½ or ⅔ as long as the width of the gaps 35a 35b. The extensions 36a 36b can extend the full length of the gaps 35a 35b, provided that the extensions do not touch the gate electrode 26. However, making the extensions very close to the gate electrode may increase the fringe capacitance to undesirable levels. Even with the source and drain extensions 36a 36b, there still exists a tradeoff between fringe capacitance and CNT resistance, though the tradeoff is relaxed compared to transistors of the prior art.
The extensions are necessarily limited in width (i.e., in the Y-direction). Preferably, the extensions 36a 36b are less than 2, 5 or 10 times the width of the CNT 20. Increasing the extension width (in the Y-direction) tends to increase the fringe capacitances 2830; decreasing the extension width tends to decrease the fringe capacitances 2830. For example, if the extensions 36a 36b are as wide as the source and drain, then no reduction in fringe capacitance is provided by the extensions 36a 36b. Hence, it is preferable for the extensions 36a 36b to have a width of less than ½, ¼, 1/10 a width (in the Y-direction) of the source 22 or drain 24. Generally, the extensions 36a 36b should be as narrow (in the Y-direction) as possible.
In operation, the conductivity of the semiconducting CNT 20 is controlled by voltage applied to the gate electrode 26 as known in the art. Current flowing between the source and drain is shunted through the extensions 36a 36b, which will typically have a resistance lower than the CNT 20. Also, the fringe capacitance is greatly reduced because the extensions 36a 36b are very narrow in the Y-direction. Hence, the present CNT transistor structure has exceptionally low values of both fringe capacitance and resistance.
It is noted that the substrate can be used as the back gate electrode, as known in the art.
a-4d illustrate a preferred method for making the present CNT transistor starting with a multi-walled carbon nanotube. The fabrication steps proceed as follows:
a: A multiwalled carbon nanotube 40 is disposed on a substrate surface. The substrate can comprise a silicon wafer, with an oxide or nitride coating, for example. Source 22 and drain 24 electrodes are fabricated, and the multiwalled nanotube is electrically connected between the source and drain. The source and drain can be made of sputtered or electroplated metal, for example. The multi-walled nanotube can be embedded in the source and drain, for example.
The multiwalled nanotube 40 can have 2-30 or more coaxial carbon nanotubes surrounding the central semiconducting CNT 20, for example. Typically, the multiwalled nanotube 40 will be made by a catalytic process, or by carbon arc discharge, as known in the art. The multiwalled nanotube can be deposited on the substrate by a solvent carrier, catalytically grown on the substrate or other methods known in the art.
a also shows a magnified view of the multi-walled carbon nanotube, illustrating individual graphitic tubes 42. The central semiconducting CNT 20 (an SWNT) is also indicated.
b: A mask 44a 44b is deposited and pattered. The size of the mask 44a 44b determines the length of the extensions 36a 36b. A central portion 45 of the multiwalled carbon nanotube 40 is exposed. The mask can be made of any conventional mask material, including photoresist and hard mask materials such as SiO2 or metals. Hard mask materials may better tolerate the high temperatures produced in the following ohmic heating step.
c: The source 22 and drain 24 electrodes are connected to an electrical power supply 46, which flows current through the multiwalled nanotube 40. Simultaneously, the multiwalled nanotube is exposed to an oxygen atmosphere 48. The atmosphere can comprise pure oxygen, or oxygen mixed with other gases. Current from the power supply 46 creates a resistive heating effect in the multiwalled nanotube 40, causing the outermost tubes of the multiwalled nanotube to become oxidized by the oxygen atmosphere. With time, the outer tubes of the original multiwalled nanotube are peeled away one by one like layers of an onion. Typically, the multiwalled nanotube 40 can have about 5-30 concentric nanotubes.
Preferably, the power supply 46 provides an approximately constant voltage. The constant voltage is selected to provide adequate current for ohmic heating and oxidation of metallic-conducting nanotubes, but insufficient current for ohmic heating and oxidation of semiconducting nanotubes. It is noted that in multiwalled carbon nanotubes, the larger-diameter, outer nanotubes are almost always metallic conductors. Hence, the outer nanotubes are most susceptible to ohmic heating and consequent oxidation. The innermost single nanotube 20 is much more likely to be semiconducting and therefore it will not be heated by the constant voltage provided by the power supply 46. In some multiwalled nanotubes, one or more outer tubes will be semiconducting. In this case, the undesired semiconducting nanotubes can be oxidized and removed by temporarily increasing the applied voltage from the power supply 46.
The magnified inset in
If the central carbon nanotube happens to have metallic conducting properties, then it will be ohmically heated, oxidized, destroyed and entirely removed. In this case, there will be no electrical connection between the source 22 and drain 24 electrodes (unless multiple parallel nanotubes are provided). This is a desirable effect because metallic nanotubes are inoperable in a CNT transistor. However, if only a single nanotube is present, the transistor will be inoperable in this case. For this reason, it will be preferred for each transistor to have multiple nanotubes connected in parallel. If one nanotube happens to have a metallic conducting central nanotube then the other, parallel semiconducting nanotubes will remain.
The resistance of the multiwalled nanotube 40 should be monitored during heating. A sudden step-like increase in resistance indicate the destruction of the outermost carbon nanotube.
The above-described process of diameter-reduction of multiwalled carbon nanotubes by ohmic heating in an oxygen atmosphere is further explained in “Engineering Carbon Nanotubes and Nanotube Circuits Using Electrical Breakdown” by P. Collins et al., Science, Vol. 292, 27 Apr. 2001, pp. 706-709, which is hereby incorporated by reference in its entirety.
d: The mask 44a 44b is removed. The gate insulator 27 and gate electrode 26 are deposited on top of the CNT 20 by deposition, etching and masking steps as known in the art. The nanotube will typically bend toward the substrate (as shown) and adhere to the substrate by Van der Waals forces.
It is noted that the present nanotube transistor can have one (as illustrated) or a plurality of nanotubes (arranged in parallel) connected between the source and drain electrodes. The fabrication process for transistors having a plurality of nanotubes is the same as the process illustrated in
Alternatively, oxidizing gases other than oxygen can be used to remove the outer carbon nanotubes. For example, chlorine, fluorine, water vapor or other gases known to remove the outer carbon nanotubes can be used.
In an alternative embodiment, the extensions comprise deposited metal (e.g., electrodeposited or sputtered metal). In this case, the metal may be disposed only on a top surface of the semiconducting carbon nanotube.
The present nanotube transistor can also be fabricated by depositing metal to form the extensions 36a 36b.
a: The semiconducting CNT 20 is deposited on the substrate 21. Source 22 and drain 24 electrodes are deposited and electrically connected to the CNT 20. The CNT 20 can be catalytically grown on the substrate 21 or can be grown elsewhere and transferred to the substrate (e.g., in a solvent carrier). The semiconducting CNT 20 is a single-walled carbon nanotube.
b/5c:
d: Metal 50 is deposited on the semiconducting CNT 20 in regions where extensions 36a 36b are desired. For example, the metal can be deposited by sputtering, chemical vapor deposition, electrodeposition or other deposition processes. In some embodiments, the metal can be Ti, W, Ni, Co, Cr, Ta, V, Fe, Al, Cu, Pt or alloys thereof for example. Preferably, the mask 48 is shaped so that the metal is deposited in a region having a very limited width (in the Y-direction). This aspect is illustrated in the top view of
Optionally after removing mask 40 the substrate is heated at several hundred degrees C. The CNT 20 deposited with metal is thereby changed to metal carbide that is very stable and durable. The metal outside the metal carbide can be chemically removed (ex. by HF solution) so that the extension is composed of only metal carbide. Conversion to metal carbide will thereby assure that the extensions are limited in width.
e: The mask 48 is removed. The gate insulator 27 and gate electrode 26 are deposited on top of the CNT 20 by deposition, etching and masking steps as known in the art. The extensions 36a 36b comprise the deposited metal.
The preferred embodiments of the present invention provide a carbon nanotube transistor having reduced fringe capacitance and reduced “channel” resistance compared to the prior art. The extensions 36a 36b reduce the source-drain resistance of the transistor and simultaneously reduce the fringe capacitance. Of course, greater reductions in source-drain resistance can be achieved by tolerating a larger fringe capacitance, and vice-versa.
The preferred present transistor structure can be used in a wide range of microelectronic circuits and devices, such as memory circuits, microprocessors and the like. In such devices, similar multiwalled nanotubes can be used to fabricate the transistors, and the same applied voltage (from power supply 46) can be used to obliterate the outer carbon nanotubes in all the transistors.
In some applications, it may be preferable for each transistor to have multiple semiconducting carbon nanotubes connected in parallel.
In a microelectronic device having millions of carbon nanotube transistors, it will be important to assure that every transistor has an appropriate applied voltage during the nanotube burnoff (in oxygen) step. In order to assure that proper voltages are applied to every transistor, each source and drain can be connected to tentative voltage supplying networks formed before the device fabrication process. The tentative voltage supplying networks are substantially the same with the voltage supplying networks of conventional large scale integrated circuits. After device fabrication, the tentative voltage source network can be removed partially or completely by conventional etching process once Additionally: redundant circuit design can be employed to mitigate the effect of defective transistor devices.
While illustrative embodiments of the invention have been described herein, the present invention is not limited to the various preferred embodiments described herein but includes any and all embodiments having modifications, omissions, combinations (e.g., of aspects across various embodiments), adaptations and/or alterations as would be appreciated by those in the art based on the present disclosure. The limitations in the claims are to be interpreted broadly based on the language employed in the claims and not limited to examples described in the present specification or during the prosecution of the application, which examples are to be construed as non-exclusive. For example, in the present disclosure, the term “preferably” is non-exclusive and means “preferably, but not limited to.” Means-plus-function or step-plus-function limitations will only be employed where for a specific claim limitation all of the following conditions are present in that limitation: a) “means for” or “step for” (i.e., not step of) is expressly recited; b) a corresponding function is expressly recited; and c) structure, material or acts that support that structure are not recited. In this disclosure and during the prosecution of this application, the terminology “present invention” or “invention”, may be used as a reference to one or more aspect within the present disclosure. The language present invention or invention should not be improperly interpreted as an identification of criticality, should not be improperly interpreted as applying across all aspects or embodiments (i.e., it should be understood that the present invention has a number of aspects and embodiments), and should not be improperly interpreted as limiting the scope of the application or claims. In this disclosure and during the prosecution of this application, the terminology “embodiment” can be used to describe any aspect, feature, process or step, any combination thereof, and/or any portion thereof, etc. In some examples, various embodiments may include overlapping features.
