Patent Application
20220021139
Embodiments related to card edge connectors.
Data rates of electrical signals sent via Peripheral Component Interconnect Express (PCIe)-based communications in accordance with PCIe specifications have increased over time. For example, PCIe data rates have octupled from Gen3 (8 gigabits per second (Gbps)) to Gen6 (64 Gbps pulse amplitude modulation 4-level (PAM4)) in less than a decade. In many applications, desirable electrical signal integrity in platform interconnects have become increasingly stringent. Many PCIe-based communications occur between devices that are coupled together using a card edge connector, such as for example, a card electromechanical (CEM) connector. Surface mount technology (SMT) CEM connectors are often used to accommodate desirable electrical performance.
Card edge connectors typically includes two sets of pins disposed on either side of the card edge connector. The pins are used to electrically connect the card edge connector to a printed circuit board (PCB). Some card edge connectors include pins having an end that extends through the bottom of the card edge connector and includes a heel portion and a toe portion that extends from the heel portion in a direction away from a centerline of the card edge connector. In instances where congestions issues are present on the PCB, the heel portion of one or more of the pins are often coupled to heel-routed signal lines on the PCB. When a pin is coupled to a heel-routed signal line via the heel portion as opposed being coupled to a toe-routed signal line to via the toe portion, the toe portion of the pin is left floating. The floating toe portion is called a stub. The stub associated with heel-based signal routing is typically larger than a stub associated with toe-based signal routing The stub associated with heel-based signal routing may result in higher resonance and degradation in signal performance than the relatively smaller stub associated with toe-based signal routing.
Card edge connectors are often used to provide electrical connection between contacts of a first circuit board, such as for example, an add-in card and contacts of a second circuit board, such as for example, a motherboard of a system. An example of a card edge connector is a Peripheral Component Interconnect Express (PCIe) connector. The card edge connector includes a housing with a slot that is configured to receive the first circuit board. Two sets of pins are typically disposed on opposing sides of the slot and extend from within the slot through a bottom of the housing. Each of the pins include a first end that is configured to mate with a contact of the first circuit board disposed within the slot and a second end that is configured to mate with a contact of the second circuit board. Each of the contacts on the second circuit board are coupled to a toe-routed signal line on the second circuit board.
The second end of each of the pins includes a heel portion and a toe portion that extends from the heel portion. The first set of pins are configured in an orientation such that the toe portion of each pin extends from the heel portion in a direction away from a centerline of the slot. The second set of pins are configured in a flipped pin foot orientation where the toe portion of each pin extends from the heel portion in a direction towards the centerline of the slot.
When the card edge connector is coupled to the second circuit board, the toe portion of the second end of each of the pins is electrically coupled a toe-routed signal line via a contact on the second circuit board. A stub length associated with toe-based signal routing is relatively smaller than a stub length associated with heel-based signal routing. A card edge connector including a flipped pin orientation enables both sets of pins on opposing sides of the slot to be used for toe-based signal routing in cases where there is congestion on the second circuit board. The use of toe-based signal routing typically results in relatively lower resonance and lower degradation in signal performance than the use of heel-based signal routing in high-speed communications.
Referring to
The card edge connector 100 includes a housing 102, a slot 104. The slot 104 is configured to receive a first circuit board. In an embodiment, the card edge connector 100 is configured to be connected to an edge portion of a second circuit board. An example of a second circuit board is a motherboard of a system. In an embodiment, the first circuit board is a PCIe circuit board. In an embodiment, the first circuit board is an add-in card. Examples of add-in cards include, but are not limited to, a networking card of a network interface circuit (NIC), a graphics card that provides video/graphics functionality by way of one or more graphics processing units (GPUs), and an accelerator card. In alternative embodiments, the slot 104 may be configured to receive other types of first circuit boards. The first circuit board includes a plurality of contacts, such as for example, finger contacts. An example of a finger contact is a gold-plated finger contact.
The card edge connector 100 includes a first plurality of pins 106 and a second plurality of pins 108. The first and second plurality of pins 106, 108 extend from within the slot 104 through a bottom of the housing 110. Each of the first plurality of pins 106 includes a first end that is configured to mate with a corresponding contact of the first circuit board that is inserted into the slot 104 of the card edge connector 100 and a second end that extends through the bottom of the housing 110. The second end of the first plurality of pins 106 includes a heel portion 112 and a toe portion 114. The toe portion 114 extends from the heel portion 112 in a direction away from a centerline 116 of the slot 104.
Each of the second plurality of pins 108 includes a first end that is configured to mate with a corresponding contact of the second circuit board that is inserted into the slot 104 of the card edge connector 100 and a second end that extends through the bottom of the housing 110. The second end of the second plurality of pins 108 includes a heel portion 118 and a toe portion 120. The toe portion 120 extends from the heel portion 118 in a direction towards the centerline 116 of the slot 104. The second plurality of pins 108 are arranged in a flipped pin foot orientation. In an embodiment, the first plurality of pins 106 are disposed along a first side of the slot 104 and the second plurality of pins 108 are disposed along a second side of the slot 104 opposite the first side of the slot 104. In an embodiment, one of the first and second plurality of pins 106, 108 are configured to be transmit pins and the other one of the first and second plurality of pins 106, 108 are configured to be receive pins.
In alternative embodiments, the card edge connector 100 may include a fewer or greater number of first and second plurality of pins 106, 108 than shown in
Referring to
As mentioned above, the card edge connector 100 includes a slot 104 configured to receive the first circuit board 208. Each of the first plurality of pins 106 includes a first end that is configured to mate with a corresponding contact 210 of the first circuit board 208 and the second end including the toe portion 114 that extends from the heel portion 112 in a direction away from the centerline of the slot 116. The toe portion 114 is configured to be coupled a corresponding contact 204 of the second circuit board 202. When the first circuit board 208 is inserted into the slot 104, one or more of the contacts 210 of the first circuit board 208 are electrically coupled to a corresponding toe-routed signal line via the toe portion 114 of one of the first plurality of pins 106 and the contact 204 on the second circuit board 202.
Each of the second plurality of pins 108 includes a first end that is configured to mate with a corresponding contact 212 of the first circuit board 208 and the second end including the toe portion 120 that extends from the heel portion 118 in a direction towards the centerline of the slot 104. The toe portion 120 is configured to be coupled a corresponding contact 206 of the second circuit board 202. When the first circuit board 208 is inserted into the slot 104, one or more of the contacts 212 of the first circuit board 208 are electrically coupled to a corresponding toe-routed signal line via the toe portion 120 of one of the second plurality of pins 108 and the contact 206 on the second circuit board 202. The system 200 enables routing of signals between components of the first circuit board 208 and components of the second circuit board 202.
Referring to
A stub length 306 associated with toe-based signal routing is relatively smaller than a stub length associated with heel-based signal routing. A card edge connector 100 including a flipped pin foot orientation enables both the first plurality of pins 106 and the second plurality of pins 108 on opposing sides of the slot 104 to be used for toe-based signal routing in cases where there is congestion on the second circuit board 202. The use of toe-based signal routing typically results in relatively lower resonance and lower degradation in signal performance than the use of heel-based signal routing in high-speed communications.
Referring to
The second pin 402 includes a first end 408 configured to mate with a corresponding contact 212 of the first circuit board 208 and a second end 410 configured to mate with a corresponding contact 206 of the second circuit board 202. The second end 410 includes the heel portion 118 and the toe portion 120 that extends from the heel portion 118 in a direction towards the centerline 116 of the slot 104. The second end 410 of the second pin 402 is electrically coupled to a corresponding contact 206 of the second circuit board 202 via the toe portion 120.
Referring to
In an embodiment, each of the first plurality of pins 106 includes multiple differential pairs of pins 500a, 500b, 500c, 500d. Each of the second plurality of pins 108 includes multiple differential pairs of pins 502a, 502b, 502c, 502d. The differential pin configuration that may be used in PCIe communications. In alternative embodiments, the pins may be configured to facilitate single-ended signal communication.
To understand the impact of the flipped pin foot orientation of the second plurality of pins 108 in the overall platform performance, a full link level analysis was performed in PCIe 6.0 one connector topology with 13-inch mother board routing with base spec assumptions for equalizations. Table 1 lists the eye-opening comparison of cases with toe entry and heel entry in current design and with toe entry in new design. With heel entry, the current connector makes 13-inch channel the eye spec. The eye difference between heel entry and toe entry is about 4.1 my/4.8% UI. With the flipped pin foot orientation of the second plurality of pins 108, no channel performance change was observed. Overall, surface mount card edge connectors 100 with a flipped pin foot orientation has negligible impact on PCIe 6.0 channel performance but brings routing flexibility, allows routing under the card edge connector 100 to directly connect to pin foot with toe-entry, and save routing space on the board.
In alternative embodiments, the flipped pin foot connector technology can be applied to card edge connectors such as for example, high speed input/output (TO) (HSIO) connectors as well such as Ethernet, Intel® Ultra Path Interconnect (UPI), universal serial bus (USB) and serial attachment technology (SATA).
The flipped pin foot orientation may be implemented in a PCIe 5.0/6.0 SMT edge connector. The connector footprint on the second circuit board 202 is be positioned to mate with the flipped pin foot orientation of the card edge connector 100. The flipped pin foot orientation of the card edge connector 100 enables an input/output (I/O) signal line on a side of the card edge connector 100 to be routed under the card edge connector 100 and directly connect to the pin foot of one of the second plurality of pins 108 with a toe entry. This may solve routing congestion problems with respect to the second circuit board 202 and reduce the space that the card edge connector 100 occupies on the second circuit board 202 while maintaining signal performance of the card edge connector 100.
In PCIe 5.0/6.0, SMT card edge connectors are often used to minimize the stub caused by long via in through hole mount (THM) connector. Heel-based signal routing typically leaves a stub length of about 1.63 mm (64 mil) while toe-based signal routing typically leaves a stub length of about 0.37 mm (15 mil). In many instances the SI performance may be significantly degraded with heel-based signal routing because a significant portion of the connector pad is not in the signal path. In PCIe 5.0/6.0, a 64 mil stub may be detrimental to signal integrity.
In many board designs of the second circuit board 202, such as for example, a half width board, a high-density small board, and a riser card design, the PCIe card edge connector is placed at the edge of a second circuit board 202, such as for example, of a motherboard, because of mechanical limitations. In addition, depending on the placement of the card edge connector, in instances where signal routing space is available, the use of heel-based signal routing may lead to lengthened signal trace routing and potentially increase the cost of PCB materials.
The use of a card edge connector 100 with a flipped foot pin orientation may address routing congestion problems on a second circuit board 202, such as for example a motherboard, and provide signal routing flexibility. In an embodiment, a first plurality of pins 106 where the toe portion 114 extends from the heel portion 112 in a direction away from the centerline of the slot, may be one of signal transmit pins and signal receive pins and a second plurality of pins 108 where the toe portion 120 extends from the heel portion 118 in a direction towards the centerline 116 of the slot 104 may be the other one of the signal transmit pins and the signal receive pins.
Embodiments may be implemented in a wide variety of interconnect structures. Referring to
System memory 610 includes any memory device, such as random access memory (RAM), non-volatile (NV) memory, or other memory accessible by devices in system 600. System memory 610 is coupled to controller hub 615 through memory interface 616. Examples of a memory interface include a double-data rate (DDR) memory interface, a dual-channel DDR memory interface, and a dynamic RAM (DRAM) memory interface.
In one embodiment, controller hub 615 is a root hub, root complex, or root controller in a PCIe interconnection hierarchy. Examples of controller hub 615 include a chipset, a memory controller hub (MCH), a northbridge, an interconnect controller hub (ICH), a southbridge, and a root controller/hub. Often the term chipset refers to two physically separate controller hubs, i.e. a memory controller hub (MCH) coupled to an interconnect controller hub (ICH). Note that current systems often include the MCH integrated with processor 605, while controller hub 615 is to communicate with I/O devices, in a similar manner as described below. In some embodiments, peer-to-peer routing is optionally supported through root complex 615.
Here, controller hub 615 is coupled to switch/bridge 620 through serial link 619. Input/output modules 617 and 621, which may also be referred to as interfaces/ports 617 and 621, include/implement a layered protocol stack to provide communication between controller hub 615 and switch 620. In one embodiment, multiple devices are capable of being coupled to switch 620.
Switch/bridge 620 routes packets/messages from device 625 upstream, i.e., up a hierarchy towards a root complex, to controller hub 615 and downstream, i.e., down a hierarchy away from a root controller, from processor 605 or system memory 610 to device 625. Device 625 includes any internal or external device or component to be coupled to an electronic system via a card edge connector having a flipped pin foot orientation in accordance with an embodiment, such as an I/O device, a NIC, an add-in card, an audio processor, a network processor, a memory expander, a hard-drive, a storage device such as a solid state drive, a CD/DVD ROM, a monitor, a printer, a mouse, a keyboard, a router, a portable storage device, a Firewire device, a Universal Serial Bus (USB) device, a scanner, and other input/output devices. To this end, device 625 may be implemented on a circuit board to be adapted within an embodiment of a card edge connector as described herein.
Graphics accelerator 630 is also coupled to controller hub 615 through serial link 632. In one embodiment, graphics accelerator 630 is coupled to an MCH, which is coupled to an ICH. Switch 620, and accordingly I/O device 625, is then coupled to the ICH. I/O modules 631 and 618 are also to implement a layered protocol stack to communicate between graphics accelerator 630 and controller hub 615. A graphics controller or the graphics accelerator 630 itself may be integrated in processor 605.
Turning next to
Interconnect 712 provides communication channels to the other components, such as a Subscriber Identity Module (SIM) 730 to interface with a SIM card, a boot ROM 735 to hold boot code for execution by cores 706 and 707 to initialize and boot SoC 700, a SDRAM controller 740 to interface with external memory (e.g., DRAM 760), a flash controller 745 to interface with non-volatile memory (e.g., flash 765), a peripheral controller 750 to interface with peripherals, video codec 720 and video interface 725 to display and receive input (e.g., touch enabled input), GPU 715 to perform graphics related computations, etc. In addition, the system illustrates peripherals for communication, such as a Bluetooth module 770, 3G modem 775, GPS 780, and WiFi 785, one or more of which may be implemented on a circuit board to be adapted within the card edge connector having the flipped pin foot orientation as described herein.
Also included in the system is a power controller 755. Further illustrated in
Referring now to
Still referring to
Furthermore, chipset 890 includes an interface 892 to couple chipset 890 with a high performance graphics engine 838, by a P-P interconnect 839. As shown in
Various devices may be coupled to second bus 820 including, for example, a keyboard/mouse 822, communication devices 826 and a data storage unit 828 such as a disk drive or other mass storage device which may include code 830, in one embodiment. Further, an audio I/O 824 may be coupled to second bus 820.
The following examples pertain to further embodiments.
In one example, a card edge connector includes: a housing including a slot to receive a first circuit board; a first plurality of pins extending from within the slot through a bottom of the housing, each of the first plurality of pins comprising a first end to mate with a corresponding contact of the first circuit board and a second end to mate with a corresponding one of a first plurality of contacts of a second circuit board, the second end comprising a heel portion and a toe portion extending from the heel portion in a direction away from a centerline of the slot; and a second plurality of pins extending from within the slot through the bottom of the housing, each of the second plurality of pins comprising a first end to mate with a corresponding contact of the first circuit board and a second end to mate with a corresponding one of a second plurality of contacts of the second circuit board, the second end comprising a heel portion and a toe portion extending from the heel portion in a direction toward the centerline of the slot.
In an example, the first plurality of pins are disposed along a first side of the slot and the second plurality of pins are disposed along a second side of the slot opposite the first side of the slot.
In an example, the card edge connector includes a Peripheral Component Interconnect Express (PCIe) connector to receive the first circuit board comprising a PCIe circuit board.
In an example, the card edge connector is to be connected to an edge portion of the second circuit board.
In an example, each of the first and second plurality of contacts of the second circuit board are connected to a corresponding toe-routed signal line and each of the first and second plurality of pins are to be coupled to the corresponding toe-routed signal line via the toe portion and the corresponding one of the first and second plurality of contacts of the second circuit board.
In an example, the card edge connector is to enable communication between at least one memory device adapted to the first circuit board and a processor adapted to the second circuit board.
In an example, the first plurality of pins are one of a plurality of transmit pins and a plurality of receive pins and the second plurality of pins are the other one of the plurality of transmit pins and the plurality of receive pins.
In one example, a system includes: a first circuit board including: a processor; first and second plurality of contacts on a surface of the first circuit board; one or more signal lines to couple the processor to one or more of the first and second plurality of contacts; and a card edge connector. The card edge connector includes: a housing including a slot to receive a second circuit board; a first plurality of pins extending from within the slot through a bottom of the housing, each of the first plurality of pins comprising a first end to mate with a corresponding contact of the second circuit board and a second end to mate with a corresponding one the first plurality of contacts of the first circuit board, the second end comprising a heel portion and a toe portion extending from the heel portion in a direction away from a centerline of the slot; and a second plurality of pins extending from within the slot through a bottom of the housing, each of the second plurality of pins comprising a first end to mate with a corresponding contact of the second circuit board and a second end to mate with a corresponding one of the second the plurality of contacts of the first circuit board, the second end comprising a heel portion and a toe portion extending from the heel portion in a direction toward the centerline of the slot.
In an example, each of the first and second plurality of contacts comprises a conductive pad having a first end and a second end, the second end of the first plurality of conductive pads disposed in a direction away from the centerline of the slot with respect to the first end and the second end of the second plurality of conductive pads disposed in a direction towards the centerline of the slot with respect to the first end.
In an example, the second plurality of contacts are disposed on the surface of an edge portion of the first circuit board.
In an example, one or more memory devices are adapted to the second circuit board.
In an example, the card edge connector is to communicate signals at one of a data rate of at least 32 gigabits per second and a data rate of at least 64 gigabits per second.
In an example, the card edge connector is a surface mount Peripheral Component Interconnect Express (PCIe) connector and the second circuit board is a PCIe circuit board.
In an example, the second circuit board is a network interface circuit.
In an example, each of the first and second plurality of pins are to be coupled to a corresponding signal line via the toe portion and a corresponding one of the first and second plurality of contacts of the second circuit board.
In an example, the first circuit board is one of a half width board, high density small board, and a riser card.
In one example, a card electromechanical (CEM) connector includes: a housing comprising a slot into to receive a first circuit board; a first plurality of pins extending from within the slot through a bottom of the housing, each of the first plurality of pins comprising a first end to mate with a corresponding contact of the first circuit board and a second end to mate with a corresponding one of a first plurality of conductive pads of a motherboard, the second end comprising a heel portion and a toe portion extending from the heel portion in a direction away from a centerline of the slot; and a second plurality of pins extending from within the slot through the bottom of the housing, each of the second plurality of pins comprising a first end to mate with a corresponding contact of the first circuit board and a second end to mate with a corresponding one of a second plurality of conductive pads of the motherboard, the second end comprising a heel portion and a toe portion extending from the heel portion in a direction toward the centerline of the slot.
In an example, the CEM connector is a Peripheral Component Interconnect Express (PCIe) connector to receive the first circuit board comprising a PCIe circuit board.
In an example, each of the first and second plurality of conductive pads of the motherboard are connected to a corresponding toe-routed signal line and each of the first and second plurality of pins are to be coupled to the corresponding toe-routed signal line via the toe portion and the corresponding one of the first and second plurality of conductive pads of the motherboard.
In an example, the first plurality of pins are disposed along a first side of the slot and the second plurality of pins are disposed along a second side of the slot opposite the first side.
Note that the terms “circuit” and “circuitry” are used interchangeably herein. As used herein, these terms and the term “logic” are used to refer to alone or in any combination, analog circuitry, digital circuitry, hard wired circuitry, programmable circuitry, processor circuitry, microcontroller circuitry, hardware logic circuitry, state machine circuitry and/or any other type of physical hardware component. Embodiments may be used in many different types of systems. For example, in one embodiment a communication device can be arranged to perform the various methods and techniques described herein. While an embodiment of a communication device has been described, alternative embodiments can be directed to other types of apparatus for processing instructions, or one or more machine readable media including instructions that in response to being executed on a computing device, cause the device to carry out one or more of the methods and techniques described herein.
Embodiments may be implemented in code and may be stored on a non-transitory storage medium having stored thereon instructions which can be used to program a system to perform the instructions. Embodiments also may be implemented in data and may be stored on a non-transitory storage medium, which if used by at least one machine, causes the at least one machine to fabricate at least one integrated circuit to perform one or more operations. Still further embodiments may be implemented in a computer readable storage medium including information that, when manufactured into a SoC or other processor, is to configure the SoC or other processor to perform one or more operations. The storage medium may include, but is not limited to, any type of disk including floppy disks, optical disks, solid state drives (SSDs), compact disk read-only memories (CD-ROMs), compact disk rewritables (CD-RWs), and magneto-optical disks, semiconductor devices such as read-only memories (ROMs), random access memories (RAMs) such as dynamic random access memories (DRAMs), static random access memories (SRAMs), erasable programmable read-only memories (EPROMs), flash memories, electrically erasable programmable read-only memories (EEPROMs), magnetic or optical cards, or any other type of media suitable for storing electronic instructions.
While a limited number of embodiments have been described, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations.
