Card reader comprising an energy-saving system

Abstract

A smart card reader includes a housing for receiving a smart card, a microprocessor, and a connector for connecting the microprocessor to the received smart card for establishing communications therebetween. A voltage source provides a power supply voltage to the microprocessor based upon the smart card being received in the housing. The smart card reader further includes a first switch interposed between the voltage source and a power supply terminal of the microprocessor. The first switch is closed when the received smart card is at an end of travel in the housing so that the power supply voltage is provided to the microprocessor, and is opened when the received smart card is no longer at the end of travel in the housing so that the power supply voltage is not provided to the microprocessor.

Description

FIELD OF THE INVENTION

[0003] The present invention relates to electronic devices, and more particularly, to a smart card reader.

BACKGROUND OF THE INVENTION

[0004] An example smart card reader 1 known as a viewer is illustrated in FIG. 1. A viewer type card reader 1 generally comprises a small size case or housing 2, a display 3 and a slot 4 for receiving the smart card 5. Due to the reduced size of the case 2, only an end of the card 5 is received. This type of reader enables, for example, the number of remaining units in a phone card to be displayed, and the amount of money available in a smart card of the electronic purse type to be displayed. The reader 1 may be in the form of a key ring, as shown in FIG. 1.

[0005] As illustrated in FIG. 2, inside of such a reader 1 is generally a printed circuit board 10 on which a microprocessor 11, the display 3, a smart card connector 12, a travel end detector 13, and an electrical battery 14 providing electrical power to the microprocessor 11 are laid out on.

[0006] The microprocessor 11 is generally of the microcontroller type and includes on the same silicon chip various peripheral components such as an oscillator, a ROM type program memory, a RAM and/or EEPROM type data memory, and display drive circuits, etc. The connector 12, which is generally a friction type connector, for example, comprises metal pads 12-i configured so that they coincide with the contact pads 5-i of the smart card 5 when inserted in the reader 1.

[0007] The travel end detector 13 enables the microprocessor 11 to know whether a card 5 is inserted in the housing to initialize communication with the card. Since there is no protection in this type of reader against the card 5 being pulled out, conventionally, the microprocessor 11 is programmed so that it stops communicating with the card in a clean way, particularly when the card is suddenly removed from the reader. For this, the microprocessor 11 has a few milliseconds during which the metal pads 12-i of the connector 12 are still in contact with the pads 5-i of the card 5. The removal rate of the card 5 is on the order of 2 m/s. Stopping communications in a clean way includes sending a reset signal (RST) to the card 5 according to the ISO 7816 standard, for example.

[0008] Operation of reader 1 will now be discussed below. For periods of non-use, the microprocessor 11 places itself in an idle or standby state wherein its consumption is very low. This consumption is typically on the order of 1 to 10 μA according to the structure and complexity of the microprocessor 11.

[0009] When a card 5 is inserted into the housing and is at the end of travel therein, the closing of detector 13 triggers an interrupt in the microprocessor 11, which then initializes communication with the card 5 and displays the information contained therein. When the card 5 is removed, the opening of the detector 13 triggers a new interrupt and the microprocessor 11 switches back to the standby state. If the microprocessor 11 is still in communication with the card 5 at the instant of its removal, it interrupts communication with the card before placing itself in the idle state.

[0010] The main drawback of such a reader 1 is that it has a non-zero consumption of current when not in use, and a limited battery life time. Since the period of use of the reader 1 is insignificant with respect to the period of being idle, the consumption of the microprocessor 11 in the idle state, although minimal, has a significant influence on the life of the battery 14.

[0011] A smart card reader comprising a system for reducing the electrical power supply of the reader when a smart card is removed therefrom is disclosed in European Patent No. 762,307. This system comprises a switch detecting the presence of a smart card, which delivers an active signal to a circuit providing the power supply voltage for the reader. The system stops delivering the electrical power to the reader when this signal is emitted. However, the system requires a certain degree of complexity for having the power supply circuit react to the active signal delivered by the card detector.

[0012] A microprocessor provided with a system for detecting power supply voltage drops is also disclosed in U.S. Pat. No. 5,428,252. The power supply voltage is provided by a battery, and the detection system delivers an interrupt signal for a large drop in the power supply voltage. The interrupt signal enables the microprocessor to back up data before switching over to a sleep mode. Moreover, European Patent No. 803,831 describes a smart card reader comprising two switching means, one for activating the reader when a card is inserted therein and the other for detecting card removal to allow the reader to finish a current transaction.

Summary of the Invention

[0013] An object of the present invention is to provide a straightforward and low cost approach for suppressing power consumption of a microprocessor in a smart card reader when a smart card is not in the reader.

[0014] Another object of the present invention is to suppress power consumption of the microprocessor while being able to properly interrupt communication with a smart card when the card is abruptly removed.

[0015] These objects are achieved by providing a smart card reader comprising a housing for receiving a smart card, a microprocessor, means for connecting the microprocessor to the smart card inserted in the housing, a voltage source, and means for not delivering to the microprocessor the voltage provided by the voltage source when the smart card is not in the housing. The means for not delivering to the microprocessor the voltage provided by the voltage source comprises a first switching means of the normally open type, interposed between the voltage source and a power supply terminal of the microprocessor. The first switching means is configured to close when a card is at the end of travel in the housing, and is configured to open when the card is no longer at the end of travel.

[0016] According to one embodiment, the microprocessor comprises means for detecting the opening of the first switching means, means for ending communication with a smart card if the first switching means opens during such a communication, and a capacitor for maintaining the power supply voltage of the microprocessor above a threshold when the first switching means switches from the closed state to the open state. This is done at least during the time necessary for the microprocessor to end a current communication.

[0017] According to one embodiment, the means for detecting opening of the first switching means comprise a comparator for comparing the power supply voltage of the microprocessor with a reference voltage. The reference voltage may be generated by the voltage delivered by the voltage source without passing through the first switching means. The reference voltage may be delivered by a voltage divider powered by the voltage source. The voltage divider may be connected to ground by a switch that is in the open state when the microprocessor is not powered.

[0018] According to one embodiment, the means for ending a communication comprise means for generating an interrupt signal when the comparator output changes its value as a result of the opening of the first switching means. The means for detecting an opening of the first switching means may comprise a second switching means that closes when a card is at the end of travel in the housing, and opens when the card is no longer at the end of travel in the housing. The second switching means has a first terminal connected with the voltage source, and a second terminal monitored by the microprocessor. The means for ending a communication may comprise means for generating an interrupt signal when the second switching means switches from the closed state to the open state.

[0019] The present invention also relates to a comparator including two input branches each comprising at least one ballast transistor and a control transistor for receiving the aforementioned power supply voltage and reference voltage. For example, the comparator may comprise an additional ballast transistor connected in parallel with a ballast transistor of one of the input branches, and means for connecting the control input of the additional ballast transistor to the control inputs of:the other ballast transistors when the output voltage of the comparator is in a first state.

[0020] The comparator may further comprise means for blocking the additional ballast transistor when the output voltage of the comparator is in a second state. The comparator has a switching hysteresis depending on the state of its output. According to one embodiment, the comparator further comprises means for causing the additional ballast transistor to conduct during a transition period when the output voltage of the comparator switches from the second state to the first state.

[0021] The comparator may further comprise means for blocking the ballast transistors during a transition period when the output voltage of the comparator switches from the first state to the second state. The means for blocking or for causing the additional ballast transistor to conduct during a transition period may comprise means for delaying, during the transition period, the application of control signals that depend on the new state of the output of the comparator to the additional ballast transistor.

BRIEF DESCRIPTION OF THE DRAWINGS

[0022] These objects, features and advantages of the present invention will be discussed in more detail in the following description of two exemplary embodiments of a smart card reader according to the invention, made as non-limiting, with reference to the enclosed figures wherein:

[0023] FIG. 1 illustrates an external view of a smart card reader of the viewer type according to the prior art;

[0024] FIG. 2 is an electrical diagram of the smart card reader illustrated in FIG. 1;

[0025] FIG. 3 is an electrical diagram of a first embodiment of a smart card reader comprising an energy-saving system according to the invention;

[0026] FIGS. 4A-4F illustrate different electrical signals for operation of the smart card reader illustrated in FIG. 3;

[0027] FIG. 5 is an electrical diagram of a second embodiment of a smart card reader according to the invention;

[0028] FIG. 6 is an electrical diagram of a comparator according to the prior art;

[0029] FIG. 7 is an electrical diagram of a first comparator with hysteresis according to the invention; and

[0030] FIG. 8 is an electrical diagram of a second comparator with hysteresis according to the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0031] FIG. 3 illustrates the electrical diagram of a smart card reader 20 including an energy-saving system according to the invention. The general structure of the reader 20 complies with that of the conventional reader 1 illustrated in FIG. 1. The reader 20 comprises a case including a housing for receiving the card (not shown), an electrical battery 21, a microprocessor 30, as well as a display and a card connector which are not shown so that the figure may be simplified. Other peripheral components, notably a keyboard, may also be provided.

[0032] The right hand portion of FIG. 3, as separated by the dotted line, illustrates components of the energy-saving system according to the invention that are included in the microprocessor 30 for practical reasons, as well as the main hardware components of the microprocessor participating in the operation of the system. The other components of the microprocessor 30 are not illustrated for reasons of simplicity, as well as the peripheral components like the memory plane and the drivers for the display.

[0033] The microprocessor 30 conventionally comprises a power supply terminal 31 and a ground terminal 32 respectively connected to an internal power supply line 33 and to a ground plane 34. External the microprocessor, terminals 31 and 32 are respectively connected to the anode and cathode of the electrical battery 21. Battery 21 is illustrated by its equivalent circuit diagram, and comprises an ideal generator 22 delivering a voltage VE and a resistor 23 in series therewith. Resistor 23 is the internal resistance of the battery 21.

[0034] According to a first aspect of the invention, the power supply terminal 31 of the microprocessor is connected to the anode of the battery 21 via a travel end switch 24, which is normally open in the absence of a smart card. The switch 24 is of any known type, such as a flexible lever or a push button, for example.

[0035] Thus, the microprocessor 30 is only powered provided that a card is inserted into the reader and that it is pushed into its housing properly. Under these conditions, switch 24 is closed and the microprocessor receives a power supply voltage VDD substantially equal to voltage VE, except in the case of high current consumption. When the card is removed from the housing or begins to be removed, switch 24 opens and the microprocessor 30 is no longer powered. The card reader 20 according to the invention thus has zero current consumption when not in use, and maximizes the life of the battery 21 or provides an optimum discharge time in the case of a rechargeable battery.

[0036] The reader 20 also comprises a capacitor 25 that is preferably external to the microprocessor 30, and is connected between the power supply terminal 31 and the ground terminal 32. The capacitor 25 enables the voltage VDD to be gradually applied to the microprocessor 30 upon the closing of the switch 24. Upon opening of the switch 24, the capacitor:25 maintains the voltage VDD for a few milliseconds or tens of milliseconds above a voltage threshold V2 during which the microprocessor 30 stops operating, as this will be seen later on. According to the invention, the microprocessor 30 also comprises means for detecting opening of the switch 24, and means for cleanly interrupting a communication with a smart card if the card is removed during such a communication.

[0037] A first embodiment of the detection means will now be discussed with reference to FIG. 3. The detection means comprises a comparator 35, the negative input of which is connected to the power supply terminal 31 and receives the power supply voltage VDD. The positive input of the comparator 35 receives a reference voltage VREF.

[0038] Advantageously, the reference voltage VREF is produced by the voltage VE, without passing through switch 24, using a special terminal 36 of the microprocessor 30 directly connected to the anode of battery 21. Here, the reference voltage VREF is picked up at the middle point of a voltage divider bridge comprising two resistors 37 and 38. Resistor 37 is connected to terminal 36 and resistor 38 is connected to ground via a switch 39, for example, a MOS transistor. This switch 39 is driven by a reset signal RST from the microprocessor 30, as described later on.

[0039] The output of the comparator 35 is applied to the D input of a synchronous D flip-flop 40. The clock input CK of the flip-flop 40 receives the clock signal H from the microprocessor 30 and the RESET input receives an IRST signal. The Q output of the flip-flop 40 is applied to the clock input CK of a second synchronous D flip-flop 41. The D input of the flip-flop 41 is permanently held at 1 (voltage VDD) and the RESET input receives a WR0 signal (zero write). The Q output of the flip-flop 41 delivers a power down flag PDF bit or flag so that the microprocessor 30 may know that a voltage cutoff is occurring as a result of switch 24 opening. Flip-flop 41 is a cell of a flag register 42, and the PDF flag may be sent onto the data bus 43 of the microprocessor 30 via a tristate buffer 44 controlled by a read signal RD. The PDF flag is also applied to an input of an interrupt decoder 45 via an AND gate 46 receiving on its other input an interrupt mask bit BIM.

[0040] When the PDF flag is 1 and when the AND gate is transparent (BIM bit is 1), the interrupt decoder 45 delivers to the central processing unit (CPU) 47 of the microprocessor 30 an interrupt vector giving the address of a subprogram, which is conventional, and contains the necessary instructions for interrupting a current communication with a smart card.

[0041] Other components of the microprocessor 30 participating in the operation of the system according to the invention are illustrated at the bottom of FIG. 3. A conventional low voltage detector 48 with hysteresis receives as inputs the power supply voltage VDD, and two reference voltages V1 and V2. The output of detector 48 delivers the RST signal for resetting the microprocessor 30 and is accessible through a terminal 49 for external resets. The output of detector 48 is applied to the input of a delay circuit 50, for example, a counter driven by the clock signal H. When the RST signal switches to 1, the delay circuit 50 delivers an RST1 signal set to 1 with a shift corresponding to a determined number of clock cycles. Signals RST and RST1 are combined in an AND gate 51, the output of which delivers an IRST signal for an internal reset of the microprocessor 30, well known to one skilled in the art.

[0042] Operation of the reader 20 according to the invention-will now be described with reference to FIGS. 4A-4F. These figures respectively illustrate the curve: of the power supply VDD, the timing diagram of the RST signal, the timing diagram of the IRST signal, the curve of voltage VREF, the curve of the differential voltage VREF-VDD applied to the comparator 35, and the timing diagram of the PDF flag.

[0043] When a smart card is inserted, switch 24 closes at instant Ti. Voltage VDD rises slowly (FIG. 4A) because of the charging of capacitor 25. Simultaneously, voltage VREF switches to 0 and increases to voltage VDD (FIG. 4B). At an instant T2, voltage VDD reaches the threshold V1 and the detector 48 sets the RST signal to 1 (FIG. 4B). Switch 39 conducts (FIG. 3), the divider bridge 37 and 38 conducts and voltage VREF is lowered substantially (FIG. 4D).

[0044] The differential voltage VREF-VDD becomes less than 0 (FIG. 4E) and the output of the comparator 35 is held at 0. At an instant T3, occurring a few clock pulses H after the switching of signal RST to 1, circuit 50 sets the RST1 signal to 1 and the internal reset signal IRST switches to 1 (FIG. 4C). This instant T3 corresponds to all the components of the microprocessor 30 being put into service, which will then execute a procedure for querying and reading the smart card.

[0045] As compared with the prior art, switching on of the microprocessor triggers a communication with a smart card and not an interrupt generated by the closing of a travel end switch.

[0046] Now let us assume that the card is suddenly removed from its housing at an instant T4 when communication between the microprocessor 30 and the card is not finished. Switch 24 opens and the power supply voltage VDD starts to decrease slowly (FIG. 4A) because of the discharge of the capacitor 25. Also, the reference voltage VREF increases substantially because the microprocessor 30 no longer consumes the current delivered by the battery 21.

[0047] At an instant T5 very close to instant T4, voltage VDD becomes less than voltage VREF and the differential voltage VREF-VDD becomes positive (FIG. 4E). With reference to FIG. 3, the output of the comparator 35 thus switches to 1. At the first next clock pulse H, the Q output of flip-flop 40 switches to 1 and enables the clock input CK of flip-flop 41, the Q output (PDF flag) of which also switches to 1. With the assumption that bit BIM was set to 1 at the beginning of the communication with the card, the PDF flag is transmitted to the input of the interrupt decoder 45. The latter then directs the microprocessor to the aforementioned communication interrupt subprogram.

[0048] Referring again to FIGS. 4A-4F, the microprocessor stops operating at instant T6 when voltage VDD reaches threshold V2. At that instant, detector 48 resets the RST signal to 0 and the IRST signal also switches to 0. The internal time Tsc which elapses between instant T5 and T6, during which the PDF flag is set to 1 (FIG. 4F), thus determines the time available to the microprocessor 30 for interrupting a current communication with a smart card. This time interval is at least equal to the friction time of the contact pads of the cards on the connector of reader 20.

[0049] A second embodiment of the detection means will now be discussed with reference to FIG. 5. The illustrated reader 60 comprises different means for detecting opening of the switch 24. The comparator receiving the reference voltage VREF is not used. The terminal 36 of the microprocessor 30 is connected to the anode of the battery 21 via a second travel end switch 61, which opens and closes at the same instant as the switch 24. For example, switch 61 is placed adjacent to the switch 24 in the housing.

[0050] Terminal 36 is connected to the D input of flip-flop 40 via an inverter circuit 62, such as an inverting gate or a trigger with hysteresis. When switch 61 is open, the input of the inverter circuit 62 is held in the low state by a resistor 63. The resistor 63 has a very high value and is connected to ground. Except for these differences, the other components of reader 60 are the same as those of reader 20 of FIG. 3, and will not be further described.

[0051] When switch 61 opens, the output of the inverter circuit 62 switches to 1. The Q output of flip-flop 40 switches to 1 at the first next clock pulse H, causing the switching of flag PDF to 1 at the output of flip-flop 41, and the triggering of an interrupt sending the microprocessor 30 to the aforementioned subprogram.

[0052] It will be clearly apparent to one skilled in the art that the present invention is open to various other alternatives and embodiments. Although the invention was designed for meeting the need of saving energy in small readers of the viewer type powered by a battery, the invention may however be applied to any type of reader. Also, it will be noted that the present invention is applicable to contactless smart card readers, i.e., proximity contactless readers. Proximity contactless readers require insertion of a card into a housing and differ simply from contact readers by the fact that the means for connecting the microprocessor to the card assumes the form of an inductive coupling interface using an antenna coil, instead of assuming the form of a friction connector. In the present application, the term connection means should therefore not be interpreted in a restrictive way.

[0053] Exemplary embodiments of a comparator will now be discussed. The first embodiment of the invention described above with reference to FIG. 3 involves a comparator 35 for detecting a drop of the power supply voltage: VDD under the threshold VREF. This comparator 35 should provide characteristics which conventional comparators do not have, notably good stability of its output voltage. The output of the comparator 35 should be prevented from oscillating between 0 and 1 when the voltage VDD slowly approaches voltage VREF after the switch 24 opens.

[0054] FIGS. 1, 2 and 8 respectively illustrate the electrical diagram of a conventional comparator 35-1, the electrical diagram of a comparator with hysteresis 35-2, and the electrical diagram of a preferred embodiment of a comparator with hysteresis 35-3 according to the invention.

[0055] Tables 1, 2 and 3 describe the structure of comparators 35-1, 35-2, 35-3 by showing their components and the interconnection of these components. Components referenced as NMi are NMOS transistors and components referenced as PMi are PMOS transistors. Components referenced as ni are interconnection nodes, and components IG1, IG2 are current generators configured as current mirrors. Components referenced as IVi are inverting gates. Transistors NM7 and PM8 form an inverting gate IV1 delivering the output voltage Vout of the comparator.

[0056] A same basic structure is found in the three comparators, which comprises an input stage and an output transistor PM5 driving the input of the inverting gate IV1. The input stage comprises two branches with each branch including a respective ballast transistor PM2, PM4 and a control transistor NM1, NM3.

[0057] In the conventional comparator 35-1 of FIG. 6, transistors PM2 and PM4 have the same W/L ratio (gate width over length). This comparator has the drawback of being unstable when voltage VDD decreases and approaches voltage VREF. In this case, both input branches are actually balanced and the voltage VDOUT, which controls the output transistor PM5 is able to oscillate.

TABLE 1
Comparator 35-1 (FIG. 6)
Transistors	Source	Drain	Gate
NM1	n1	n2	VDD
PM2	VDD	n1	n1
NM3	n3/VDOUT	n2	VREF
PM4	VDD	n3/VDOUT	n1
PM5	VDD	n4/VGO	n3/VDOUT
PM6	VDD	n5/VOUT	n4/VGO
NM7	n5	GND (ground)	n4/VGO
Other components	Input	Output
IG1	n2	GND
IG2	n4	GND
IV1 (NM7 + PM8)	n4	n5/VOUT

[0058]

TABLE 2
Comparator 35-2 (FIG. 7)
Transistors	Source	Drain	Gate
NM1	n1	n2	VDD
PM2	VDD	n1	n1
NM3	n3/VDOUT	n2	VREF
PM4	VDD	n3/VDOUT	n1
PM5	VDD	n4/VGO	n3/VDOUT
PM6	VDD	n5/VOUT	n4/VGO
NM7	n5	GND (ground)	n4/VGO
PM8	VDD	n3/VDOUT	n6
PM9	VDD	n6	n5/VDOUT
PM10	n6	n1	n7/NOT
			VDOUT
Other components	Input	Output
IG1	n2	GND
IG2	n4	GND
IV1 (NM7 + PM8)	n4	n5/VOUT
IV2		n7

[0059]

TABLE 3
Comparator 35-3 (FIG. 8)
Transistors	Source	Drain	Gate
NM1	n1	n2	VDD
PM2 VDD	n1	n1
NM3	n3/VDOUT	n2	VREF
PM4	VDD	n3/VDOUT	n1
PM5	VDD	n4/VGO	n3/VDOUT
PM6	VDD	n5/VOUT	n4/VGO
NM7	n5	GND (ground)	n4/VGO
PM8	VDD	n3/VDOUT	n6
PM9	VDD	n6	n5/VDOUT
PM10	n6	n1	n7/NOT
			VDOUT
NM11	n6	n8	n7 NOT
			VDOUT
NM12	n8	GND	n5/VDOUT
Other components	Input	Output
IG1	n2	GND
IG2	n4	GND
IV1 (NM7 + PM8)	n4	n5/VOUT
IV2′	n5/VOUT	n7

[0060] In the comparator 35-2 of FIG. 7, the ballast transistor PM8 is added in parallel with the ballast transistor MP4 of the second branch. Transistors PM2, PM4 and PM8 are designed in such a way that their respective gate widths W2, W4 and W8 meet the following relationship:

W 2 =W4+W8  (1)

[0061] Accordingly, the differential voltage which should be applied at the input of the comparator in order to balance both input branches is different according to whether VOUT switches from VDD to 0 or from 0 to VDD The first balance differential voltage is greater than 0 when transistor PM8 is blocked, as the gate of transistor PM4 is not as wide as the gate of transistor PM2. Transistor PM8 is blocked when the output voltage VOUT is equal to 0. The transistor PM9 then conducts and the gate of the transistor PM8 is brought to voltage VDD. The second balance differential voltage is equal to 0 when transistor PM8 is conducting because of the above relationship (1). Transistor PM8 is conducting when the output voltage VOUT is equal to VDD, transistor PM10 then conducts (node n7 set to 0) and node n6 is connected to node n1.

[0062] Thus, the comparator 35-2 has the advantage of providing a switching hysteresis, i.e., a differential voltage VREF-VDD for switching to the high state (VOUT=VDD) different from the differential voltage for switching to the low state (VOUT=0). The output voltage VOUT, once it has switched to the high state, remains stable as long as voltage VDD continues to decrease.

[0063] In the comparator 35-3 of FIG. 8, the inverting gate IV2 is replaced with an inverting gate IV2′ with a longer switching time and transistors NM11 and NM12 are added. When the output voltage VOUT is equal to VDD, transistor PM9 is blocked and transistor PM10 is conducting. Node n1 is connected to node n6. The ballast transistors PM2, PM4 and PM8 have the same gate voltage.

[0064] When voltage VOUT then switches from VDD to 0, transistor PM9 conducts and transistor PM10 remains conducting as long as the output of the inverting gate IV2′ is not at VDD. Voltage VOUT is therefore applied back on the node n1 of the input branch of the comparator during the transition period. The result is that the output VOUT is further forced towards zero when the comparator is not stabilized. Transistors NM11 and NM12 remain blocked during this transition period.

[0065] When the output voltage VOUT switches from 0 to VDD, the stabilization of the comparator during the transition period is provided by transistors NM11 and NM12. Transistor NM12 conducts and transistor NM11 remains conducting as long as the output of gate IV2′ does not switch to 0. As both transistors NM11 and NM12 are conducting, the node n6 which controls the transistor PM8 is forced to 0 and transistor PM8 is conducting. Transistors PM9 and PM10 remain blocked during this transition period.

[0066] The comparator 35-3 provides the advantage of being very stable when the differential voltage changes very slowly, as this may be the case when the capacitor 25 of FIG. 3 has a high electrical capacitance. As comparators 35-2, 35-3 have for practical reasons, an output voltage inverted with respect to that of the comparator 35 described above, an inverting gate may be added between the output of these comparators and the flip-flop 40 of FIG. 3. As another solution, the inverted output/Q of the flip-flop 40 may be connected to the flip-flop 41 rather than to its Q output.

[0067] Comparators 35-2, 35-3 are open to alternative embodiments which are within the reach of one skilled in the art by applying the principles which have just been described. They are also open to different applications, other than the one corresponding to the implementation of the smart card reader illustrated in FIG. 3, and may thus form an independent invention.

Claims

1-32. (Cancelled)

33. A comparator circuit comprising: two input branches for receiving a power supply voltage and a first reference voltage, each input branch comprising at least one ballast transistor and a control transistor connected thereto; an additional ballast transistor connected in parallel with one of said at least one ballast transistors; a connection circuit for connecting a control input of said additional ballast transistor to a control input of said at least one ballast transistor in each branch when an output of the comparator circuit is in a first state; and a blocking circuit for blocking said additional ballast transistor when the output of the comparator circuit is in a second state, said blocking circuit having a switching hysteresis.

34. A comparator according to claim 33, wherein said additional ballast transistor conducts during a transition period when the output of said comparator circuit switches from a second state to the first state.

35. A comparator according to claim 34, wherein at least one ballast transistor in each branch is blocked during the transition period when the output of said comparator circuit switches from the first state to the second state.

36. A comparator according to claim 34, wherein application of control signals to said additional ballast transistor are delayed during the transition period.

37. A comparator according to claim 33, wherein each of said at least one ballast and control transistors comprises a MOS transistor.

38. A comparator according to claim 37, wherein a sum of the gate widths of the additional ballast transistor and the at least one ballast transistor connected in parallel therewith is equal to a gate width of the other at least one ballast transistor.

39. A comparator according to claim 33, wherein each of said at least one ballast transistors comprises a PMOS transistor, and each of said control transistors comprises an NMOS transistor.

40. A comparator circuit comprising: a first input branch comprising at least one first ballast MOS transistor and a first control transistor connected thereto; a second input branch connected to said first input branch and comprising at least one second ballast MOS transistor and a second control transistor connected thereto; an additional ballast MOS transistor connected in parallel with said at least one second ballast MOS transistor; a connection circuit for connecting a control input of said additional ballast MOS transistor to control inputs of said at least one first and second ballast MOS transistors when an output of the comparator circuit is in a first state; and a blocking circuit for blocking said additional ballast MOS transistor when the output of the comparator circuit is in a second state, said blocking circuit having a switching hysteresis.

41. A comparator according to claim 40, wherein said additional ballast MOS transistor conducts during a transition period when the output of the comparator circuit switches from a second state to the first state.

42. A comparator according to claim 41, wherein at least one ballast MOS transistor in each branch is blocked during the transition period when the output of the comparator circuit switches from the first state to the second state.

43. A comparator according to claim 41, wherein application of control signals to said additional ballast MOS transistor are delayed during the transition period.

44. A comparator according to claim 33, wherein a sum of the gate widths of the additional ballast transistor and the at least one second ballast MOS transistor is equal to a gate width of the at least one first ballast MOS transistor.

45. A method for making a comparison using a comparator circuit comprising two input branches for receiving a power supply voltage and a first reference voltage, each input branch comprising at least one ballast transistor and a control transistor connected thereto; and an additional ballast transistor connected in parallel with one of said at least one ballast transistors; the method comprising: connecting a control input of said additional ballast transistor to a control input of said at least one ballast transistor in each branch when an output of the comparator circuit is in a first state; and blocking said additional ballast transistor when the output of the comparator circuit is in a second state, said blocking circuit having a switching hysteresis.

46. A method according to claim 45, wherein the additional ballast transistor conducts during a transition period when the output of said comparator circuit switches from a second state to the first state.

47. A method according to claim 46, wherein blocking further comprises blocking at least one ballast transistor in each branch during the transition period when the output of said comparator circuit switches from the first state to the second state.

48. A method according to claim 46, wherein application of control signals to said additional ballast transistor are delayed during the transition period.

49. A method according to claim 45, wherein each of said at least one ballast and control transistors comprises a MOS transistor.

50. A method according to claim 49, wherein a sum of the gate widths of the additional ballast transistor and the at least one ballast transistor connected in parallel therewith is equal to a gate width of the other at least one ballast transistor.

51. A method according to claim 45, wherein each of said at least one ballast transistors comprises a PMOS transistor, and each of said control transistors comprises an NMOS transistor.