NSF Award
1149654
The objective of the research is to develop an innovative spin-transfer torque random access memory (STT-RAM) based memory hierarchy to meet the demands of modern embedded systems for low-power, fast-speed and high-density on-chip data storage. <br/>Three integrated components are included in our research to address the major technical concerns in STT-RAM designs: (1) Application-driven STT-RAM cell design and optimization to target different embedded system specifications. (2) Thermal resilient adaptive STT-RAM memory hierarchy to tolerate the temperature instability of STT-RAM incurred by ambient temperature and self-heating. (3) Probabilistic STT-RAM design methodology to improve the run-time stability and/or the performance. <br/><br/>This research provides a comprehensive design package for efficiently integrating STT-RAM into modern embedded system designs and offers unparalleled performance and power advantages. The system architects and the circuit designers can be well bridged and educated by the research innovations. The developed techniques can be directly transferred to industry applications under the close collaborations with several industry partners, and directly impact the future embedded systems. The activities in the collaboration also include the tutorials in the major conferences on the technical aspects of the projects and new course development. <br/><br/>The educational components of this project will introduce the students to the implementation and optimization techniques of embedded systems and train the students? problem solving ability by leveraging challenge based instruction technique.
