Carrying tray for semiconductors

Abstract

Description

FIG. 1 is a front elevational view of a carrying tray for semiconductors showing our new design.

FIG. 2 is a reference view taken from line 2-2 of FIG. 1.

FIG. 3 is a reference view taken from line 3-3 of FIG. 1.

FIG. 4 is a rear elevational view of the carrying tray for semiconductors.

FIG. 5 is a reference view taken from line 5-5 of FIG. 4.

FIG. 6 is a reference view taken from line 6-6 of FIG. 4.

FIG. 7 is a top plan view of the carrying tray for semiconductors.

FIG. 8 is a reference view taken from line 8-8 of FIG. 7.

FIG. 9 is a reference view taken from line 9-9 of FIG. 7.

FIG. 10 is a bottom plan view of the carrying tray for semiconductors.

FIG. 11 is a reference view taken along line 11-11 of FIG. 10.

FIG. 12 is a reference view taken along line 12-12 of FIG. 10.

FIG. 13 is a left-side view of the carrying tray for semiconductors.

FIG. 14 is a right-side view.

FIG. 15 is a partial enlarged view of FIG. 9, designated by area 15.

FIG. 16 is a partial enlarged view of FIG. 8, designated by area 16.

FIG. 17 is a partial enlarged view of FIG. 11, designated by area 17.

FIG. 18 is a partial enlarged view of FIG. 12, designated by area 18.

FIG. 19 is a partial enlarged view of FIG. 9, designated by area 19.

FIG. 20 is a partial enlarged view of FIG. 8, designated by area 20.

FIG. 21 is a cross sectional view of the carrying tray for semiconductors, taken along line 21-21 of FIG. 10.

FIG. 22 is a reference view taken along line 22-22 of FIG. 21.

FIG. 23 is a reference view taken along line 23-23 of FIG. 21.

FIG. 24 is a cross sectional view of FIG. 8, taken along line 24-24.

FIG. 25 is a partial enlarged view of FIG. 23, designated by area 25.

FIG. 26 is a partial enlarged view of FIG. 22, designated by area 26.

FIG. 27 is a partial enlarged view of FIG. 24, designated by area 27; and,

FIG. 28 is a partial enlarged view of FIG. 24, designated by area 28.

The evenly-spaced broken lines illustrate environmental structure and the dash-dot-dash lines illustrate a boundary of the claimed design for those figures, and both of them form no part of the claimed design.

Claims

The ornamental design for a carrying tray for semiconductors, as shown and described.