CASCODE POWER AMPLIFICATION CIRCUITS, INCLUDING VOLTAGE PROTECTION CIRCUITS

FIELD OF THE DISCLOSURE

The technology of the disclosure relates generally to power amplifiers and particularly to cascode power amplifiers.

BACKGROUND

Mobile wireless communication and data transfer technologies continue to evolve from second generation (2G), third generation (3G), and 4G fourth generation (4G) long-term evolution (LTE) to, most recently, the fifth generation new radio (5G NR) standard. Each generation accesses different frequencies and has increased requirements for bandwidth and range. Since network infrastructures may not be immediately updated in all geographical areas as technologies emerge, a mobile device may encounter networks of different technology generations. Wireless devices must be designed to adapt to these different networks and their respective requirements. Consumers impose additional demands on the most common wireless mobile devices, including longer battery life, smaller device size, and lower cost. Meeting the conflicting demands of evolving technologies and consumers presents many challenges.

SUMMARY

Aspects disclosed in the detailed description include cascode power amplification circuits, including environmental voltage protection circuits. Related methods of protecting cascode power amplifiers from environmental voltages are also disclosed. A power amplification circuit includes an amplifier circuit and a circuit for protecting transistors in the amplifier circuit from a destructive output voltage on an output node generated by either the amplifier circuit itself in operation or the environment of the amplifier circuit in an off-state. The amplifier circuit includes a series of transistors, including a first cascode transistor coupled to the output node, a last cascode transistor coupled to a reference voltage node (e.g., ground), and one or more middle cascode transistors coupled between the first cascode transistor and the last cascode transistor.

In normal operation, the output node is coupled to a power supply node, and the output voltage is distributed across the series of transistors. The output voltage is determined by an input signal on an input terminal coupled to a control terminal of the last cascode transistor and a gain of the last cascode transistor. The circuit protecting the amplifier circuit in normal operation may include one or both of a protection circuit and a stress control circuit. The protection circuit determines when the output voltage exceeds a threshold and provides a feedback signal to the bias circuit to reduce the bias voltage on at least the last cascode transistor. The stress control circuit is coupled to a control terminal of the first transistor to increase a bias voltage on the control terminal to “float up” the first cascode transistor to avoid a destructive voltage.

In an off-state, a destructive voltage may be provided to the output node from an environment of the amplifier circuit. An integrated circuit (IC) containing the amplifier circuit is powered off and may receive a static charge from the external environment in a first off-state condition. In a second off-state condition, while the IC is powered on and one or more amplifier circuit segments of a segmented power amplifier circuit are coupled in parallel and actively generating an output voltage on an output node, another amplifier circuit segment coupled to the output node may be inactive. Without off-state protection circuits, the series of transistors are deactivated, subjecting the first transistor, coupled to the output node, to a destructive voltage on the output node. In this regard, the power amplifier further includes first and second off-state protection circuits that each detect an output voltage on the output node and use the output voltage to bias the series of transistors to an active state to dissipate the output voltage.

In one exemplary aspect, a power amplification circuit is disclosed. The power amplification circuit comprises an amplifier circuit comprising a plurality of cascode transistors coupled in a series between an output node and a reference voltage node, the series comprising a last cascode transistor coupled to the reference voltage node and determining a current in the output node. The power amplification circuit comprises a protection circuit configured to generate a feedback signal in response to an output voltage on the output node exceeding a threshold. The power amplification circuit comprises a bias circuit configured to reduce a bias voltage of the last cascode transistor based on the feedback signal.

In another exemplarity aspect, a power amplification circuit comprising an amplifier circuit and a stress control circuit is disclosed. The power amplification circuit comprises an amplifier circuit comprising a plurality of cascode transistors coupled in a series between an output node and a reference voltage node, the series comprising a first cascode transistor coupled to the output node. The power amplification circuit comprises a stress control circuit comprising a variable capacitor and a fixed capacitor coupled in series between the output node and the reference voltage node and configured to increase a bias voltage on the first cascode transistor in response to the output voltage exceeding a threshold. A control terminal of the first cascode transistor is coupled to a node between the variable capacitor and the fixed capacitor

In another exemplary aspect, a power amplification circuit is disclosed. The power amplification circuit comprises an amplifier circuit comprising a plurality of cascode transistors coupled in a series between an output node and a reference voltage node, the series comprising a first cascode transistor coupled to the output node and a last cascode transistor coupled to the reference voltage node, the last cascode transistor determining a current in the output node. The power amplification circuit comprises a protection circuit generating a feedback signal in response to an output voltage on the output node exceeding a first threshold and a bias circuit reducing a bias voltage of the last cascode transistor based on the feedback signal. The power amplification circuit comprises a stress control circuit comprising a variable capacitor and a fixed capacitor coupled in series between the output node and the reference voltage node and increasing a bias voltage on the first cascode transistor in response to the output voltage exceeding a second threshold. A control terminal of the first cascode transistor is coupled to a node between the variable capacitor and the fixed capacitor.

In another exemplary aspect, a power amplification circuit is disclosed. The power amplification circuit comprises an output node, a reference voltage node, and a plurality of amplifier circuits. Each of the amplifier circuits comprises a plurality of cascode transistors coupled in series between the output node and the reference voltage node, an on-state bias circuit configured to provide, in an on-state, a bias voltage to each of the plurality of cascode transistors of the amplifier circuit and suspend, in an off-state, the bias voltage to each of the plurality of cascode transistors, and an off-state protection circuit configured to distribute an output voltage on the output node across the plurality of cascode transistors in an off-state.

Those skilled in the art will appreciate the scope of the disclosure and realize additional aspects thereof after reading the following detailed description in association with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings incorporated in and forming a part of this specification illustrate several aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

FIG. 1 is a schematic diagram of a cascode transistor amplifier;

FIG. 2 is a schematic diagram of a power amplification circuit, including an amplifier circuit, a protection circuit, and a bias circuit coupled to the power amplification circuit;

FIG. 3 is a schematic diagram of the cascode transistor amplifier in FIG. 1 and a first example of a stress control circuit;

FIG. 4A is a graph of output voltages of signals on an output node of the cascode transistor amplifier of FIG. 1;

FIG. 4B is a graph of a capacitance of a variable capacitor in the stress control circuit of FIG. 3 in response to the output voltages in FIG. 4A;

FIG. 5 is a schematic diagram of the cascode transistor amplifier in FIG. 1 with a second example of the stress control circuit;

FIG. 6 is a schematic diagram of the power amplification circuit of FIG. 2 and the stress control circuit as shown in FIG. 3;

FIG. 7 is a schematic diagram of a two-stage power amplification circuit, including the power amplification circuit of claim 6 as a first stage;

FIG. 8 is a schematic diagram of the cascode transistor amplifier in FIG. 3 in which the bias circuit includes an on-state bias circuit, a first off-state bias circuit, and a second off-state bias circuit;

FIG. 9 is a schematic diagram of the cascode transistor amplifier in FIG. 8 and illustrates sub-circuits of the first off-state bias circuit;

FIG. 10A is a block diagram of one of the sub-circuits in the first off-state bias circuit in FIG. 9;

FIG. 10B is a schematic diagram illustrating details of a first example of the bias control circuit of FIG. 10A;

FIG. 10C is a schematic diagram of a second example of the bias control circuit of FIG. 10A;

FIG. 10D is a schematic diagram of one of the bias control circuits of the first parallel bias circuit; and

FIG. 11 is a schematic diagram of the cascode transistor amplifier in FIG. 8, including details of the second off-state protection circuit in the bias circuit.

DETAILED DESCRIPTION

The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

It will be understood that, although the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element, or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

Relative terms such as “over” or “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Aspects disclosed in the detailed description include cascode power amplification circuits, including environmental voltage protection circuits. Related methods of protecting cascode power amplifiers from environmental voltages are also disclosed. A power amplification circuit includes an amplifier circuit and a circuit for protecting transistors in the amplifier circuit from a destructive output voltage on an output node generated either by the amplifier circuit itself in operation or by the environment of the amplifier circuit in an off-state. The amplifier circuit includes a series of transistors, including a first cascode transistor coupled to the output node, a last cascode transistor coupled to a reference voltage node (e.g., ground), and one or more middle cascode transistors coupled between the first cascode transistor and the last cascode transistor.

In the on-state, the output node is coupled to a power supply node, and the output voltage is distributed across the series of transistors. The output voltage is determined by an input signal on an input terminal coupled to a control terminal of the last cascode transistor and a gain of the last cascode transistor. The circuit protecting the amplifier circuit in operation may include one or both of a protection circuit and a stress control circuit. The protection circuit determines when the output voltage exceeds a threshold and provides a feedback signal to the bias circuit to reduce the bias voltage on at least the last cascode transistor. The stress control circuit is coupled to a control terminal of the first transistor to increase a bias voltage on the control terminal to “float up” the first cascode transistor to avoid a destructive voltage.

A destructive voltage may be provided to the output node from outside the amplifier circuit in an off-state. An integrated circuit (IC) containing the amplifier circuit is powered off and may receive a static charge from the external environment in a first off-state condition. In a second off-state condition, while the IC is powered on and one or more amplifier circuit segments of a segmented power amplifier circuit are coupled in parallel and actively generating an output voltage on an output node, another amplifier circuit segment coupled to the output node may be inactive. Without off-state protection circuits, the series of transistors are deactivated, subjecting the first transistor, coupled to the output node, to a destructive voltage on the output node. In this regard, the power amplifier further includes first and second off-state protection circuits that each detect an output voltage on the output node and use the output voltage to bias the series of transistors to an active state to dissipate the output voltage.

Telecommunications networks are not immediately and simultaneously updated in all geographical areas as a new generation of telecommunication technology emerges. Therefore, mobile devices may need to include transmitters and receivers that operate in a variety of networks. In the evolution from second generation (2G) to third generation (3G), fourth generation long-term evolution (4G LTE), and fifth generation new radio (5G NR), the power demands of transmitters in mobile devices has changed. At the same time, the consumer market has continued to demand smaller and cheaper devices. Both the size and cost of power amplifiers in a wireless transmitter can be reduced by transitioning from amplifier circuits with larger and more expensive transistors, such as bipolar junction transistors (BJTs) made of gallium arsenide (GaAs), for example, lower-voltage transistors. As an example, the lower voltage transistors may be silicon transistors, such as field-effect transistors (FETs) (e.g., metal-oxide-semiconductor (MOS) FETs (MOSFETs)). FETs comprises a gate, a first source/drain, and a second source/drain. A bias voltage on the gate controls flow of current between the first source/drain and the second source/drain.

Previous amplifier circuits made with GaAs BJTs require one or a few transistors that can handle large voltages. However, such large voltages would be destructive to the lower voltage transistors. An amplifier circuit can include a plurality of voltage transistors with a lower voltage limit coupled in series between an output node and a reference voltage node to overcome this problem. The output voltage of a cascode amplifier circuit is distributed across multiple transistors, such that voltage stresses to each transistor is reduced, and damage to the individual transistors may be avoided. With this type of amplifier circuit, the output voltage levels needed in each different generation of telecommunication technology may be achieved at a lower cost and in a smaller package.

FIG. 1 is an illustration of an example of a cascode amplifier circuit 100 (“amplifier circuit 100”). The amplifier circuit 100 includes an input terminal 102 on which an input radio-frequency (RF) signal RF_IN is received through a capacitor C₁₀₂in an on-state during which the amplifier circuit may be operating normally. The input RF signal RF_IN is an analog signal amplified by cascode transistors 104(1)-104(5) based on a gain of the last cascode transistor 104(5) to generate an RF output signal RF_OUT having an output voltage V_OUTon output node 106. The cascode transistors 104(1)-104(5) are coupled in series between the output node 106 and a reference voltage node (e.g., ground voltage node) GND. Although the amplifier circuit 100 in this example includes only five of the cascode transistors 104(1)-104(5), an amplifier circuit in a power amplification circuit as disclosed herein may include fewer or more cascode transistors 104(X) (where X>3) coupled in series. The amplifier circuit 100 may include cascode transistors 104(1)-104(5) that are all of a first type, such as all N-channel FETs (NFETs) or all P-channel FETs (PFETs). Alternatively, an amplifier circuit of a power amplification circuit as disclosed herein may be a complementary circuit including both NFETs and PFETs.

In the on-state (e.g., operation), the amplifier circuit 100 is powered by a power supply 108, such as a battery 108 providing a supply voltage V_BAT. The amplifier circuit 100 includes an inductor 112 coupled between the power supply 108 and the output node 106. A current I₁₀₀through the cascode transistors 104(1)-104(5) increases and decreases in response to changes in a voltage V_INon the input terminal 102. Control terminals 114(1)-114(5) (e.g., gates) of the cascode transistors 104(1)-104(5) are biased to keep the cascode transistors 104(1)-104(5) activated (e.g., in a saturation region) to conduct the current I₁₀₀. An inductor voltage V₁₁₂is induced across the inductor 112 in response to changes in the current I₁₀₀. Thus, the output voltage V_OUTon the output node 106 is equal to the supply voltage V_BATplus the inductor voltage V₁₁₂(V_OUT=V_BAT+V₁₁₂). In this manner, the output voltage V_OUTcan exceed twice the supply voltage V_BAT(i.e., V_OUT>2×V_BAT). Since the output voltage V_OUTis distributed across source-to-drain voltages V_SD1-V_SD5, in the case of the cascode transistors 104(1)-104(5) comprising FETs, the output voltage V_OUTis the total of the source-to-drain voltages V_SD1-V_SD5. In some cases, the output voltage V_OUTmay not be equally divided among the source-to-drain voltages V_SD1-V_SD5. Thus, at a peak in magnitude of the output voltage V_OUT, a destructive voltage level may be applied across one or more of the cascode transistors 104(1)-104(5).

FIGS. 2, 3, 5-9, and 11 are illustrations of examples of power amplification circuits, including circuits that protect the cascode transistors 104(1)-104(5). FIGS. 2, 3, and 5-7 include circuits that protect the amplifier circuit 100 in the on-state by adjusting bias voltages on at least one of the control terminals 114(1)-114(5) upon detecting that the output voltage V_OUTexceeds a threshold. FIGS. 8, 9, and 11 illustrate circuits that protect the amplifier circuit 100 in an off-state, which includes a state in which an integrated circuit (IC) containing the amplifier circuit 100 is powered off (i.e., disconnected from a supply voltage) and a state in which the amplifier circuit 100 is an inactive circuit in a segmented power amplifier circuit.

FIG. 2 is an illustration of a power amplification circuit 200, including the amplifier circuit 100 of FIG. 1 and a protection circuit 202. Details of the amplifier circuit 100 are shown in FIG. 1. FIG. 2 also includes a bias circuit 204 coupled to the power amplification circuit 200. The bias circuit 204 is an example of a circuit that is coupled to control terminals 114(1)-114(5) to provide bias voltages for controlling the cascode transistors 104(1)-104(5) during on-state (i.e., operation) and off-state when the amplifier circuit 100 is inactive and/or disconnected from a power source. The protection circuit 202 provides one or more feedback signals 206 to the bias circuit 204 in response to detecting that the output voltage V_OUTexceeds a threshold. The protection circuit 202 provides the one or more feedback signals 206 to control the bias circuit 204 to adjust the bias voltages provided to the control terminals 114(1)-114(5). In particular, the one or more feedback signals 206 reduces the bias voltage on at least the control terminal 114(5). In some examples, the one or more feedback signals 206 cause other control terminals 114(1)-114(4), such as the control terminal 114(4), to also be adjusted. Providing feedback to adjust the bias voltage(s) on one or more of the control terminals 114(1)-114(5) reduces the current I₁₀₀through the amplifier circuit 100, which reduces the possibility of destructive voltages being applied to the cascode transistors 104(1)-104(5).

Before providing details of each of the features of the protection circuit 202, a brief description of the operation of the protection circuit 202 is provided. The protection circuit 202 includes a peak voltage circuit 208 coupled to the output node 106. The peak voltage circuit 208 generates a peak voltage V_PEAK, which indicates a highest magnitude of the output voltage V_OUT. The peak voltage V_PEAKis provided to a voltage-to-current circuit 210 that generates an output current I_OUTbased on the peak voltage V_PEAK. The protection circuit 202 also includes a threshold current circuit 212 that generates a threshold current I_THbased on a threshold value. The output current I_OUTis compared to the threshold current I_THto determine whether the output voltage V_OUTis above a desired (i.e., threshold) level. Specifically, the protection circuit 202 includes a feedback circuit 214 and an acceleration circuit 216 that respond to the output current I_OUTbeing higher than the threshold current I_TH. The feedback circuit 214 generates the one or more feedback signals 206. The acceleration circuit 216 increases the responsiveness of the protection circuit 202, so the feedback circuit 214 will respond more quickly and/or to a stronger degree when, for example, the output current I_OUTis significantly higher than the threshold current I_TH. The features of the protection circuit 202 and their individual operation details are described further below.

The peak voltage circuit 208 includes diodes D1-D4 coupled in series with the anode of the first diode D1 coupled to the output node 106 and the cathode of the last diode D4 coupled to the voltage-to-current circuit 210. The peak voltage circuit 208 also includes a capacitor C₂₀₈with one terminal coupled to the power supply 108. The other terminal of the capacitor C₂₀₈is coupled to the cathode of diode D2 and the anode of diode D3. The peak voltage V_PEAKis a voltage on the cathode of the last diode D4. The peak voltage V_PEAKprovided to the voltage-to-current circuit 210 is lower than the actual output voltage V_OUTdue to voltage drops across the diodes D1-D4 but is based on the output voltage V_OUT. In some examples, the diodes D1-D4 are MOS diodes (e.g., P-channel MOS diodes).

The voltage-to-current circuit 210 includes a first resistor R1 in series with a second resistor R2. The first resistor R1 may be much larger than the second resistor R2, the same size, or smaller than the second resistor R2. The voltage-to-current circuit 210 generates the output current I_OUTon a comparison node 218 based on the peak voltage V_PEAK. The output current I_OUTmay be proportional to the peak voltage V_PEAK. In some examples, the output current I_OUTis determined by a difference in voltage between the peak voltage V_PEAKand a voltage V_COMPon the comparison node 218 and also on the total resistance of the resistors R1 and R2. In this way, the magnitude of the output current I_OUTon the comparison node 218 corresponds to the magnitude of the peak voltage V_PEAKand, therefore, corresponds to the output voltage V_OUT.

The threshold current circuit 212 conducts a threshold current I_THthat corresponds in magnitude to the output current I_OUTgenerated when the output voltage V_OUThas reached a desired maximum. Beyond the desired maximum of the output voltage V_OUT, destructive voltages may be applied to the cascode transistors 104(1)-104(5). In other words, if the output current I_OUTis greater than the threshold current I_TH, the output voltage V_OUTmay be high enough to cause destructive voltages on at least one of the cascode transistors 104(1)-104(5). In this context, a destructive voltage can cause permanent physical damage. In this example, the threshold current circuit 212 includes a threshold register 226 configured to store the threshold value. The threshold register 226 is coupled to a digital-to-analog converter (DAC) 228 that generates an analog control signal based on the threshold value. The analog control signal controls a current generator circuit 230 to conduct the threshold current I_THfrom the comparison node 218.

The protection circuit 200 also includes resistor R3 coupled to the comparison node 218 and a capacitor C₂₁₈coupled between the resistor R3 and the reference voltage node GND. The resistor R3 and the capacitor C₂₁₈create a zero in the response of the feedback circuit 214. Current through the comparison node 218 that is not conducted through the threshold current circuit 212 may be conducted through the resistor R3 and the capacitor C₂₁₈.

The output current I_OUTmay be compared to the threshold current I_THto determine whether the output voltage V_OUThas exceeded the desired maximum. In addition, when the output current I_OUTexceeds the threshold current I_TH, the voltage V_COMPon the comparison node 218 increases. In this manner, the feedback circuit 214 detects whether the output current I_OUTexceeds the threshold current I_TH. If an increase of the voltage V_COMPis detected by the feedback circuit 214, the feedback circuit 214 generates the one or more feedback signals 206 to the bias circuit 204 to reduce the bias voltage(s) on one or more of the control terminals 114(1)-114(5). In more detail, the feedback circuit 214 includes at least one transistor 220(1)-220(X) coupled to a circuit 234, where X is an integer value. In some examples, the integer X may correspond to the number of cascode transistors in the amplifier circuit 100. Thus, in the example of cascode transistors 104(1)-104(5), X may be any integer from 1 to 5. In some examples, the circuit 234 may control a power supplied to the at least one transistor 220(1)-220(X). Gate terminals 222(1)-222(X) of the at least one transistor 220(1)-220(X) may be coupled to the comparison node 218 and receive the voltage V_COMP. The voltage V_COMPof the comparison node 218 remains at a known level while the output current I_OUTis less than or equal to the threshold voltage I_TH. If the output current I_OUTincreases above the threshold voltage I_TH, the voltage v_COMPwill increase, and the bias voltage(s) on the gate terminals 222(1)-222(X) will increase, which causes the current of the one or more feedback signals 206 provided to the bias circuit 204 to also increase. In response, the bias circuit 204 reduces a bias voltage on the control terminal 114(5) of the last cascode transistor 104(5) and may also reduce a bias voltage on one or more of the cascode transistors 104(1)-104(4).

The acceleration circuit 216 includes a bypass transistor 224 that couples to terminals of the resistor R2 of the voltage-to-current circuit 210 to bypass the resistor R2 when the acceleration circuit 216 detects that the output current I_OUTexceeds a predetermined stress level. In some examples, the stress level may be determined by a voltage between the resistors R1 and R2 of the voltage-to-current circuit 210. In some examples, the stress level may be determined by a current through the resistor R3. In this regard, the acceleration circuit 216 may be coupled to the resistor R3 and the capacitor C₂₁₈. The stress level may be indicated by a stress value stored in a register 232. The acceleration circuit 216 may activate the bypass transistor 224 when either the voltage V_COMPincreases or when the acceleration circuit 216 determines that the output current I_OUTis greater than the stress current. In some examples, the acceleration circuit 216 activates the bypass transistor 224 when it is determined that the output current I_OUTexceeds the threshold current I_THby a predetermined margin. Activating the bypass transistor 224 reduces a resistance in the voltage-to-current circuit 210, which increases the output current I_OUTfor a given voltage. A lower resistance between the peak voltage circuit 208 and the comparison node 218 increases the current to the comparison node 218, which increases the speed and/or magnitude of the response by the feedback circuit 214.

FIG. 3 is an illustration of a power amplification circuit 300, including the amplifier circuit 100 of FIG. 1 and a stress control circuit 302 that protects the cascode transistors 104(1)-104(5) by adjusting bias voltages on at least one of the control terminals 114(1)-114(5) upon detecting that the output voltage V_OUTexceeds a threshold. The threshold to which the stress control circuit 302 responds may be the same threshold or a different threshold than the threshold discussed above, to which the feedback circuit 214 responds. FIG. 3 also includes a bias circuit 304 that provides bias voltages for controlling the cascode transistors 104(1)-104(5). The stress control circuit 302 adjusts the bias voltage on at least one of the control terminals 114(1)-114(5) in response to the output voltage V_OUTexceeding a threshold.

The stress control circuit 302 includes a variable capacitor 308 and a fixed capacitor 310 coupled in series between the output node 106 and the reference voltage node GND. The variable capacitor 308 may also be a varactor 308. The control terminal 114(1) of the first cascode transistor 104(1) is coupled to a bias node 312 between the variable capacitor 308 and the fixed capacitor 310. For example, in FIG. 3, the variable capacitor 308 is coupled between the output node 106 and the bias node 312. In addition, in the example shown in FIG. 3, the variable capacitor 308 may be a MOS varactor. The fixed capacitor 310 is coupled between the bias node 312 and the reference voltage node GND. As the output voltage V_OUTon the output node 106 increases, the variable capacitor 308 coupled to the output node 106 increases in capacitance. As the variable capacitor 308 increases in capacitance, a ratio of capacitance between the variable capacitor 308 and the fixed capacitor 310 increases, causing a bias voltage at the bias node 312 to increase. The bias node 312 is coupled to the control terminal 114(1) of the first cascode transistor 104(1). In the example in which the first cascode transistor 104(1) is an N-channel MOSFET (NFET), the control terminal 114(1) is a gate 114(1), and the output node 106 is a drain terminal 106. Raising the bias voltage on the gate 114(1) raises the voltage on a source terminal SRC of the NFET cascode transistor 104(1) based on a gate-to-source voltage. Raising the voltages on the gate 114(1) and the source terminal SRC as the drain terminal 106 of the first cascode transistor 104(1) increases is referred to herein as “floating up” the first cascode transistor. By increasing the voltage on the source terminal SRC, the voltage drop from the drain terminal 106 to the source terminal SRC is reduced, which avoids a destructive voltage being applied between the drain terminal 106 and the source terminal SRC of the first cascode transistor 104(1). In some examples, the stress control circuit 302 may include a second varactor 308 and a second fixed capacitor 310 coupled in series between the output node 106 and the reference voltage node GND with the control terminal 114(2) coupled to a node between the second variable capacitor 308 and the second fixed capacitor 310 to adjust the bias voltage of the cascode transistor 104(2). Although not shown here, the stress control circuit 302 may also include a signal or signals provided to the bias circuit 304 to prevent the bias circuit 304 from reducing the bias voltage on the control terminal 114(1), and possibly one or more other control terminals 114(2)-114(5), in conflict with the stress control circuit 302.

An illustration of the effect of the stress control circuit 302 is provided in FIGS. 4A and 4B. FIG. 4A is a graph 400 illustrating the output voltage V_OUTfor signals 402, 404, and 406, whose voltages vary in time with respect to a direct current (DC) voltage V_DC. A maximum voltage V_MAXis also shown in FIG. 4A. If the output voltage V_OUTis above the maximum voltage V_MAX, the output voltage V_OUTwill cause a destructive voltage across one or more of the cascode transistors 104(1)-104(5) in the amplifier circuit 100 in FIG. 1. Voltages below the DC voltage V_DCdo not cause destructive voltages in the amplifier circuit 100. Therefore, when the signals 402, 404, and 406 have low values that cannot cause destructive voltages to the cascode transistors 104(1)-104(5), there is no need to change the capacitance C₃₀₈with the output voltage V_OUTbelow the DC voltage V_DC. As shown, the signals 402 and 404 do not reach a high enough voltage to cause a destructive voltage. However, the signal 406 exceeds the maximum voltage V_MAX. The stress control circuit 302 of FIG. 3 responds to increases in the output voltage V_OUTby increasing a capacitance of the variable capacitor 308 to raise a bias voltage on the control terminal 114(1) of the first cascode transistor 104(1).

FIG. 4B is an illustration of the capacitance C₃₀₈of the variable capacitor 308 as it changes relative to an unbiased capacitance C_UNBin response to the rise and fall of the signal 406 due to the stress control circuit 302 (not shown here). As shown, the capacitance of the variable capacitor 308 is non-linear, meaning that the response to the output voltage V_OUTabove the DC voltage V_DCdiffers from the response to the output voltage V_OUTbelow the DC voltage V_DC. Specifically, the decrease to the capacitance C₃₀₈caused by the stress control circuit 302 due to a drop in the signal 406 below the DC voltage V_DCis much less than a corresponding increase of the capacitance C₃₀₈due to a rise in the signal 406 above the DC voltage V_DC. In this manner, the stress control circuit 302 changes the bias voltage on the first cascode transistor 104(1) as needed and does not change the bias voltage on the first cascode transistor 104(1) when none is needed.

FIG. 5 illustrates an alternative example of a power amplification circuit 500, including the amplifier circuit 100 and a stress control circuit 502. FIG. 5 also includes a bias circuit 504 that provides bias voltages for controlling the cascode transistors 104(1)-104(5). The stress control circuit 502 adjusts the bias voltage on at least one of the control terminals 114(1)-114(5) in response to the output voltage V_OUTexceeding a threshold. The stress control circuit 502 includes a fixed capacitor 506 and a variable capacitor 508 coupled in series between the output node 106 and the reference voltage node GND. The variable capacitor 508 may also be a varactor 508. The control terminal 114(1) of the first cascode transistor 104(1) is coupled to a bias node 510 between the variable capacitor 508 and the fixed capacitor 506. In the example in FIG. 5, the fixed capacitor 506 is coupled between the output node 106 and the bias node 510. The variable capacitor 508 is coupled between the bias node 510 and the reference voltage node GND. In addition, in the example shown in FIG. 5, the variable capacitor 508 may be a varactor diode. As the output voltage V_OUTon the output node 106 increases, raising the bias voltage on the control terminal 114(1), the variable capacitor 508 decreases in capacitance. As the capacitance of the variable capacitor 508 decreases, the ratio of the fixed capacitor 506 and the variable capacitor 508 decreases, and the bias voltage is further increased.

FIG. 6 is an example of the power amplification circuit 600, including the amplifier circuit 100, a protection circuit 602 corresponding to the protection circuit 202 in FIG. 2, and a stress control circuit 604 corresponding to one of the stress control circuits 302 and 502 in FIGS. 3 and 5, respectively. FIG. 6 also includes a bias circuit 606. In response to the output voltage V_OUTrising above a voltage at which destructive voltages may be supplied to the cascode transistors 104(1)-104(5), the protection circuit 602 provides a feedback signal 206 that reduces a bias voltage of at least the last cascode transistor 104(5) and the stress control circuit 604 raises a bias voltage of the first cascode transistor 104(1). The feedback circuit 602 reduces the bias voltage of at least the last cascode transistor 104(5) to a bias voltage closer to the reference voltage of the reference voltage node GND (e.g., ground). In contrast, the stress control circuit 604 increases the bias voltage of at least the first cascode transistor 104(1) to a level closer to a supply voltage (V_BAT).

FIG. 7 is an example of a power amplification circuit 700 to show that the power amplification circuit 600 of FIG. 6, including the amplifier circuit 100, the protection circuit 602, and the stress control circuit 604, coupled to the bias circuit 606, may be a first stage 702 of a multi-stage amplifier. FIG. 7 also shows that the power amplification circuit 700 can include a second stage 704. In this example, the second stage 704 includes an amplification stage 706 and the protection circuit 602 coupled to a bias circuit 606. The second stage 704 may also or alternatively include the stress control circuit 604(corresponding to the stress control circuit 302 in FIG. 3 or the stress control circuit 502 in FIG. 5). Thus, as disclosed herein, cascode amplifiers and amplifier stages may be protected from destructive voltages.

FIGS. 2-7 are directed to protection of the amplifier circuit 100 from output voltages generated by the amplifier circuit 100 in the on-state (e.g., during operation). FIGS. 8-11 are directed to circuits included in a power amplification circuit for protecting the amplifier circuit 100 during an off-state. As noted above, an off-state may be a first off-state state in which an IC containing a power amplification circuit, including the amplifier circuit 100, is disconnected from a supply voltage node that would power the amplifier circuit 100. The off-state may alternatively be a second off-state state in which a power amplification circuit, including the amplifier circuit 100, is operating, but the amplifier circuit 100 is inactive (e.g., decoupled from a supply voltage node).

FIG. 8 is an illustration of an amplifier circuit 800 in a power amplification circuit 802. The power amplification circuit 802 also includes a bias circuit 804. The amplifier circuit 800 and the bias circuit 804 may correspond, respectively, to the amplifier circuit 100 in FIG. 1 and the bias circuit 606 in FIG. 6, for example. The bias circuit 804 includes an on-state bias circuit 806, a first off-state bias circuit 808, and a second off-state bias circuit 810. The on-state bias circuit 806 provides, in an on-state, bias voltages V_ON(1)-V_ON(X) (to control terminals 812(1)-812(X) of cascode transistors 814(1)-814(X) (where X>3). The bias voltages V_ON(1)-V_ON(X) may be adjusted based on the feedback signals 206 in FIG. 6 (not shown here) to reduce an output voltage V_OUTgenerated on an output node 816 during operation if the output voltage V_OUTis determined to be high enough to be destructive to the cascode transistors 814(1)-814(X). The first off-state bias circuit 808 and the second off-state bias circuit 810 each distribute an environmental voltage V_ENVbetween the output node 816 and the reference voltage node GND through the plurality of cascode transistors 814(1)-814(X).

In an off-state, the on-state bias circuit 806 may not be powered or may be disconnected from the amplifier circuit 800 and, therefore, does not generate the bias voltages V_ON(1)-V_ON(X) that control operation of the cascode transistors 814(1)-814(X). In other words, without the bias voltages V_ON(1)-V_ON(X) or any other source of a bias voltage on the control terminals 812(1)-812(X), the cascode transistors 814(1)-814(X) would be deactivated, preventing current flow in the amplifier circuit 800. Under this condition, there would be no voltage drop between a source terminal and a drain terminal of the first cascode transistor 814(1), and an environmental voltage V_ENVon the output node 816 can be destructive to at least the cascode transistor 814(1). To prevent damage to the cascode transistors 814(1)-814(X), the first off-state bias circuit 808 and the second off-state bias circuit 810 provide bias voltages to activate the cascode transistors 814(1)-814(X) to dissipate the potentially destructive voltage under two off-state conditions.

The first off-state bias circuit 808 is described with reference to FIGS. 9-10D. FIG. 9 is a schematic diagram of the amplifier circuit 800 in FIG. 8 and illustrates bias control circuits 902(1)-902(X) of the first off-state bias circuit 808. The bias control circuits 902(1)-902(X) protect the amplifier circuit 800 from destructive voltage on the output node 816 in the first off-state in which an IC is disconnected from a supply voltage node or another power source for operation. In the first off-state, an electrostatic charge may be imparted onto the IC and specifically onto the output node 816 from the environment. This may happen due to, for example, handling of the IC during manufacturing or testing of the IC or a device containing the IC. The electrostatic charge may be positive or negative relative to the reference voltage V_GNDon the reference voltage node GND and may produce a positive or negative voltage V_ENVof high magnitude (e.g., >500 volts) on the output node 816. A voltage of this magnitude could be destructive to the cascode transistors 814(1)-814(X) (e.g., by exceeding a breakdown voltage) even though the current created by the electrostatic charge may be small.

When a negative electrostatic charge causes a negative voltage V_ENVon the output node 816, this charge can be dissipated by a diode 818 coupled to the output node 816 and the reference voltage node GND. Specifically, an anode AN of the diode 818 is coupled to the reference voltage node GND, and a cathode CT of the diode 818 is coupled to the output node 816. However, since the IC is not connected to a power supply node in the first off-state, a positive charge cannot be dissipated similarly.

Instead, in an exemplary aspect described below, a positive electrostatic charge creating a positive environmental voltage V_ENVon the output node 816 can be dissipated to the reference voltage node GND through the plurality of cascode transistors 814(1)-814(X). The electrostatic charge itself may be used as the power source for providing bias voltages V_OFF1(1)-V_OFF1(X) on the control terminals 812(1)-812(X) to activate the cascode transistors 814(1)-814(X), and allow the charge on the output node 816 to be conducted to the reference voltage node GND, as explained below. The off-state protection circuit 808 is configured to, in the off-state, supply one of the bias voltages V_OFF1(1)-V_OFF1(X) on the control terminals 812(1)-812(X) of each of the plurality of cascode transistors 814(1)-814(X), based on the charge on the output node 816 to dissipate the charge on the output node 816 through the plurality of cascode transistors 814(1)-814(X).

The first off-state bias circuit 808 includes a plurality of bias control circuits 902(1)-902(X), each coupled to one of the control terminals 812(1)-812(X)). Together, the plurality of bias control circuits 902(1)-902(X) activates the cascode transistors 814(1)-814(X) to allow the amplifier circuit 800 to conduct the charge on the output node 816 to the reference voltage node GND. The bias control circuit 902(1) is coupled to the output node 816 and uses the charge on the output node 816 to provide a bias voltage V_OFF1(1) on the control terminal 812(1) of the first cascode transistor 814(1). The bias voltage V_OFF1(1) activates the first cascode transistor 814(1), which causes a current I₈₀₀to flow through the first cascode transistor 814(1), providing a voltage to the next bias circuit (e.g., the bias control circuit 902(2) to activate the next cascode transistor 814(2). In this manner, each of the plurality of cascode transistors 814(1)-814(X) is activated and powers the plurality of bias control circuits 902(1)-902(X).

A representative bias control circuit 902(N), which corresponds to each of the bias control circuits 902(1)-902(X), is described with reference to FIG. 10A. Although each of the bias control circuits 902(1)-902(X) functions the same internally, external connections of the bias control circuit 902(1) differ slightly from those of the bias control circuits 902(2)-902(X), as will be explained.

FIG. 10A illustrates the bias control circuit 902(N) coupled to an upper cascode transistor 1000(U) and to a lower cascode transistor 1000(L) next to the upper cascode transistor 1000(U), which represent any two consecutive ones of the plurality of cascode transistors 814(1)-814(X) shown in FIG. 8. FIG. 10A shows an example in which a source/drain terminal 1002(U) of the upper cascode transistor 1000(U) is coupled to a drain/source terminal 1004(L) of the lower cascode circuit 1000(L). The bias control circuit 902(N) includes a first connection C1 to a control terminal 1006(L) and a second connection C2 to the drain/source terminal 1004(L) of the lower cascode transistor 814(L). The bias control circuit 902(N) also includes a third connection C3 to the control terminal 1006(U) of the upper cascode transistor 1000(U). However, since there is no cascode transistor prior to the first cascode transistor 814(1) in the series shown in FIG. 8, the third connection C3 of the bias control circuit 902(1) is coupled to the output node 816.

FIG. 10B is a schematic diagram illustrating details of a first example of the bias control circuit 902(N) that generates the off-state bias circuit V_OFF1(N) on the control terminal 1006(L). Assuming that the upper cascode transistor 1000(U) is activated as described above due to a charge on the output node 816, the source/drain terminal 1002(U) provides a voltage to the drain/source terminal 1004(L). A voltage on the drain/source terminal 1004(L) provides a voltage to the control terminal 1006(L). That is, the bias control circuit 902(N) couples the drain/source terminal 1004(L) to the control terminal 1006(L). The bias control circuit 902(N) includes a plurality of diode circuits 1008(1)-1008(D) coupled in series (e.g., cathode of a first diode circuit to anode of a next diode circuit) between the drain/source terminal 1004(L) and the control terminal 1006(L). An anode AN1 of the diode circuit 1008(1) of the first plurality of diode circuits 1008(1)-1008(D) is coupled to the drain/source terminal 1004(L) of the lower cascode transistor 1000(L) and a cathode CTD of the diode circuit 1008(D) is coupled to the control terminal 1006(L) of the lower cascode transistor 1000(L). The diode circuits 1008(1)-1008(D) may be FET diodes, for example, in which the control terminals 1006(1)-1006(D) are gates. The diode circuits 1008(1)-1008(D) may all be a first type of FET (e.g., N-type or P-type) or a combination of a first type and a second type.

The number D of diodes circuits 1008(1)-1008(D) is determined as follows. Whenever a drain-to-gate voltage V_DGon the lower cascode transistor 1000(L) exceeds a predetermined level (e.g., 2.0 volts), it would be desirable to activate the lower cascode transistor 1000(L) to allow charge on the drain/source terminal 1004(L) to be distributed through the lower cascode transistor 1000(L) to avoid a destructive voltage being applied to the lower cascode transistor 1000(L). In this regard, it would be desirable for the bias control circuit 902(N) to include a number D (e.g., 3) of diode circuits 1008(1)-1008(D) across which a voltage drop would correspond to the predetermined level of the drain-to-gate voltage V_DG. However, a bias control circuit 902(N) limited to too few diode circuits 1008(1)-1008(D) can allow a large leakage current through the amplifier circuit 800 in a standby mode, causing the amplifier circuit 800 to exceed standby leakage specifications. To minimize the leakage current in the standby mode and meet or exceed standby leak current requirements, the number D (e.g., 4) of diode circuits 1008(1)-1008(D) should be increased.

However, increasing the number D of diode circuits 1008(1)-1008(D) creates a drain-to-gate voltage V_DGthat is higher than the predetermined level that is determined as destructive. That is, if the number D is too high, there could be a destructive drain-to-gate voltage V_DGapplied to the lower cascode transistor 1000(L). And if the number D is too low, the leakage current of the device in standby mode will exceed specifications. To overcome this conflict, the bias control circuit 902(N) further includes a diode bypass switch 1010 that can be activated to bypass a number B of the diode circuits 1008(1)-1008(D).

In this regard, the number D of diode circuits 1008(1)-1008(D) in the bias control circuit 902(N) may be high enough to avoid exceeding a leakage current specification in the standby mode, and the diode bypass switch 1010 can bypass a number B of the diode circuits 1008(1)-1008(D) to reduce the drain-to-gate voltage V_DGto a non-destructive level during operation in the on-state. In FIG. 10B, there are D=4 of the diode circuits 1008(1)-1008(D), and the diode bypass switch 1010 bypasses B=1 of the diode circuits 1008(1)-1008(D). It should be understood that a bias control circuit 902(N) may include any number D of the diode circuits 1008(1)-1008(D), and the diode bypass switch 1010 may bypass any one or more of the consecutive diode circuits 1008(1)-1008(D) and any number B of the diode circuits 1008(1)-1008(D), where B<D.

The diode bypass switch 1010 in this example may be implemented by a transistor, such as a FET, of which a drain/source terminal 1012 is coupled to an anode of one of the diode circuits 1008(1)-1008(D), such as the anode AN1. A source/drain terminal 1014 of the diode bypass switch 1010 is coupled to a cathode of one of the diode circuits 1008(1)-1008(D) to be bypassed. A control terminal 1016(e.g., a gate) of the diode bypass switch 1010 is coupled to the control terminal 1006(U) of the upper cascode transistor 1000(U). The bias voltages V_ON(1)-V_ON(X) provided on the control terminals 812(1)-812(X) in FIG. 8 will activate the diode bypass switches 1010 in the on-state. In the first off-state, an electrostatic charge creating an environmental voltage V_ENVin the amplifier circuit 800 will be distributed provided to the control terminal 1006(U) and will activate the diode bypass switch 1010 of the bias control circuit 902(N) coupled to the control terminal 1006(L) of the lower cascode transistor 1000(L).

In the case of the bias control circuit 902(1) coupled to the first cascode transistor 814(1) (not shown here), the control terminal 1016 of the diode bypass switch 1010 is coupled to the output node 816. Therefore, the diode bypass switch 1010 will bypass one (or more) of the diode circuits 1008(1)-1008(D) in either the on-state or in case of an electrostatic charge on the output node 816 during the first off-state.

FIG. 10C is a schematic diagram illustrating another example of the bias control circuit 902(N). The bias control circuit 902(N) in this example includes the plurality of diode circuits 1008(1)-1008(D). In this example, the diode bypass switch 1010, shown in FIG. 10B, is omitted. Referring back to FIG. 9, one of the bias control circuits 902(1)-902(X), is coupled to each of the control terminals 812(1)-812(X). Thus, the control terminal 1006(U) of the upper cascode transistor 1000(U) also has a bias control circuit 902(N−1) (not shown) coupled between the drain/source terminal 1004(U) and the control terminal 1006(U). A current I₉₀₂is conducted through the diode circuits 1008(1)-1008(X) to produce the bias voltage V_OFF1(N) on the control terminal 1006(L). A similar current also provides a charge on the control terminal 1006(U). The control terminal 1006(U) may be further coupled to the on-state bias circuit 806, as described above, through a large resistance R1. This large resistance on the control terminal 1006(U) provides a path through which the charge on the control terminal 1006(L) can dissipate. However, a current flow through a large resistance can increase a voltage on the control terminal 1006(L). An alternative path for sinking the charge is needed to dissipate charge from the control terminal 1006(U) without increased voltage on the control terminal 1006(U). In this regard, the bias control circuit 902(N) in FIG. 10C includes a charge sink circuit 1018.

As an example, the charge sink circuit 1018 may be implemented as a transistor having a drain/source terminal 1020 coupled to the control terminal 1006(U). A control terminal 1024 of the charge sink circuit 1018 may be coupled to an anode AN2 of one of the diode circuits 1008(1)-1008(D) and a source/drain terminal 1022 of the charge sink circuit 1018 may be coupled to a cathode CT2 of the one of the diode circuits 1008(1)-1008(D). Passing the current I₉₀₂through the diode circuits 1008(1)-1008(D) provides a voltage on the anode AN2, which activates the charge sink circuit 1018. Once activated, the charge sink circuit 1018 provides a lower resistance path to sink the charge from the control terminal 1006(U). This charge is added to the current I₉₀₂of the bias control circuit 902(N) provided to the control terminal 1006(L).

In turn, due to a high resistance R2 coupling the control terminal 1006(L) to the on-state bias circuit 806, as described above, the charge accumulated on the control terminal 1006(L) is also sinked via another charge sink circuit 1018 (not shown) to provide a lower resistance path to avoid a high voltage on the control terminal 1006(L).

FIG. 10D is a schematic diagram of another example of the bias control circuit 902(N), including both the diode bypass switch 1010 of FIG. 10B and the charge sink circuit 1018 of FIG. 10C coupled to an upper cascode transistor 1000(U) and a lower cascode transistor 1000(L). The diode bypass switch 1010 and the charge sink circuit 1018 operate independently and function in the same manner in FIG. 10D as described above with reference to FIGS. 10B and 10C, respectively. Therefore, no additional description of the function and features of FIG. 10D is provided.

FIG. 11 is a schematic diagram of the second off-state bias circuit 810 which is provided to protect the plurality of cascode transistors 814(1)-814(X) from destructive voltages in the second off-state. In the second off-state, the second off-state bias circuit 810 activates the cascode transistors 814(1)-814(X−1) in an amplifier circuit 1100 to distribute the voltage V_OUTgenerated on the output node 816 by another amplifier circuit 1102 coupled in parallel to the output node 816, as described below.

The second off-state can occur in the amplifier circuit 1100 in a segmented power amplification circuit 1100 in which there is at least one other amplifier circuit 1102 coupled in parallel with the amplifier circuit 1100, and the amplifier circuit 1102 is configured to generate an output voltage V_OUTin an on-state (as described above). The amplifier circuit 1102 includes a plurality of cascaded transistors 1103 (1)-1103 (Y) controlled by a bias circuit 1105. The power amplification circuit 1100 may include additional amplifier circuits (segments), though they are not shown here. As the demand for output power increases in the segmented power amplification circuit, the amplifier circuit 1102 and the amplifier circuit 800(and any additional amplifier circuits) can be activated. As the demand for output power declines, the amplifier circuit 800 may be deactivated. Deactivating the amplifier circuit 800 in this regard may include disconnecting the amplifier circuit 800 from a supply voltage V_DD, which may be, for example, the battery voltage V_BATprovided by a battery 108 in FIG. 1. In one example of the second off-state, the on-state bias circuit 806 may be disconnected from the supply voltage V_DD. In another example, the on-state bias circuit 806 may be decoupled from the control terminals 812(1)-812(X−1) in the second off-state by second off-state switches 1104(1)-1104(X−1). In the second off-state, the on-state bias circuit 806 does not generate the on-state bias voltages V_ON(1)-V_ON(X) on the control terminals 812(1)-812(X). Consequently, the plurality of cascode transistors 814(1)-814(X) are deactivated.

However, in the second off-state, the output voltage V_OUTmay be generated on the output node 816 by active amplifier circuits while the plurality of cascode transistors 814(1)-814(X) of the amplifier circuit 800 are inactive. In this manner, the output voltage V_OUTmay create a destructive voltage on at least the first cascode transistor 814(1). To reduce or avoid this problem, the second off-state bias circuit 809 includes a plurality of diode circuits 1106(1)-1106(X) coupled in series between a supply voltage node 1108 and the reference voltage node GND. Each of the control terminals 812(1)-812(X−1) is coupled to one of a plurality of nodes 1110(1)-1110(X−1). Each of the plurality of nodes 1110(1)-1110(X−1) is coupled to a cathode of a first one of the diode circuits 1106(1)-1106(X) and an anode of a second one of the diode circuits 1106(1)-1106(X). The plurality of nodes 1110(1)-1110(X−1) provide second off-state bias voltages V_OFF2(1)-V_OFF2(X−1) to the control terminals 812(1)-812(X−1), respectively, to activate the cascode transistors 814(1)-814(X−1). The control terminal 812(X) may be coupled to an input terminal 1112 (e.g., the input terminal 102 in FIG. 1) on which the input RF signal RF_IN is provided. The input RF signal RF_IN causes the amplifier circuit 1102 to generate a voltage V_OUTand may also activate the last cascode transistor 814(X). Thus, in the second off-state, the output voltage V_OUTmay be distributed across all of the cascode transistors 814(1)-814(X) to reduce a potentially destructive voltage across at least the first cascode transistor 814(1).

The diode circuits 1106(1)-1106(X) may be implemented as FET diodes. In some examples, all of the diode circuits 1106(1)-1106(X) may be a first type of FET diode (e.g., N-type or P-type). In some examples, the diode circuits 1106(1)-1106(X) may alternate in the sequence between a first type (e.g., N-type) and a second type (e.g., P-type). For example, the diode circuit 1106(1) may be an N-type FET diode, and the diode circuit 1106(2) may be a P-type FET diode, and so on. An anode AN3 of the diode circuit 1106(1) may be coupled to the supply voltage node 1108, and a cathode CT3 of the diode circuit 1106(X) is coupled to the reference voltage node GND.

In the on-state, with the second off-state switches 1104(1)-1104(X−1) closed, coupling the on-state bias circuit 806 to the control terminals 812(1)-812(X−1), there may be some conflict between the on-state bias voltages V_ON(1)-V_ON(X−1) and the second off-state bias voltages V_OFF2(1)-V_OFF2(X−1) but the diode circuits 1106(1)-1106(X) may be downsized to allow the on-state bias voltages V_ON(1)-V_ON(X−1) to control the voltages on the control terminals 812(1)-812(X−1) in the on-state.

It should be understood by persons skilled in the art that N-type and P-type refer to a type of channel formed in a FET, which is based on a type of dopant in a semiconductor material (e.g., silicon) from which the FET is made. A dopant may be a trivalent dopant or a pentavalent dopant, for example.

Those skilled in the art will recognize improvements and modifications to the embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.

CASCODE POWER AMPLIFICATION CIRCUITS, INCLUDING VOLTAGE PROTECTION CIRCUITS

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