Cascoded NPN electrostatic discharge protection circuit

Abstract

The electrostatic discharge protection circuit includes: at least two bipolar transistors Q1-Qn coupled in series; a top one Qn of the at least two bipolar transistors coupled to a protected node 10; a bottom one Q1 of the at least two bipolar transistors coupled to a common node 12; at least two resistors R1-Rn coupled in series; each of the at least two resistors is coupled to a corresponding base of one of the at least two bipolar transistors; and a bottom one R1 of the at least two resistors coupled between a base of the bottom one Q1 of the at least two bipolar transistors and the common node 12.

Description

FIELD OF THE INVENTION

This invention generally relates to electronic systems and in particular it relates to electrostatic discharge (ESD) protection.

BACKGROUND OF THE INVENTION

Achieving latch-up-free ESD protection (with minimum trigger voltage) for a pin when the only components available (including NPN transistors) individually snapback below the pin's operation voltage has been a problem in the prior art. Prior art high-voltage ESD circuits rely on stacking lower voltage 2-terminal ESD circuits. For these prior art devices, the trigger voltage of the total circuit is the sum of the individual circuit trigger voltages.

SUMMARY OF THE INVENTION

An electrostatic discharge protection circuit includes: at least two bipolar transistors coupled in series; a top one of the at least two bipolar transistors coupled to a protected node; a bottom one of the at least two bipolar transistors coupled to a common node; at least two resistors coupled in series; each of the at least two resistors is coupled to a corresponding base of one of the at least two bipolar transistors; and a bottom one of the at least two resistors coupled between a base of the bottom one of the at least two bipolar transistors and the common node.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings:

FIG. 1 is a schematic circuit diagram of a preferred embodiment cascoded NPN ESD protection circuit;

FIG. 2 is a schematic circuit diagram of a first alternative embodiment ESD protection circuit with a silicon controlled rectifier;

FIG. 3 is a schematic circuit diagram of a second alternative embodiment ESD protection circuit without the diode of FIG. 1 ;

FIG. 4 is a schematic circuit diagram of a third alternative embodiment ESD protection circuit with two diodes in place of the one diode of FIG. 1 ;

FIG. 5 is a schematic circuit diagram of a fourth alternative embodiment ESD protection circuit with NMOS transistors in place of the bipolar transistors of FIG. 1 ;

FIG. 6 is a schematic circuit diagram of a fifth alternative embodiment ESD protection circuit with a capacitor in parallel with the diode of FIG. 1 .

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

FIG. 1 shows a preferred embodiment schematic representation of the cascoded NPN ESD protection circuit. The preferred embodiment circuit of FIG. 1 includes NPN transistors Q 1 , Q n-1 , and Q n ; resistors R 1 , R n-1 , and R n ; diode D 1 ; ESD protected pin 10 ; and ground node 12 . The stack of NPN transistors Q 1 -Q n (which may have different sizes and styles) is connected from pin 10 to ground 12 to carry the bulk of positive ESD current. The holding/snapback voltage of this circuit is therefore the sum of the individual transistor holding/snapback voltages. These transistors Q 1 -Q n are triggered through the stack of resistors R 1 -R n by diode D 1 whose breakdown voltage determines the trigger voltage of the circuit.

In the preferred embodiment, the topmost transistor Q n is often sized larger than the other transistors since it must provide the base current to the other transistors Q 1 -Q n-1 after snapback. Also, since the top resistors carry more current prior to triggering, resistors are usually sized geometrically beginning with R 2 : R i =R 2 /(i−1) for i>2. R 1 is chosen as large as possible under transient constraints for normal circuit operation. R 2 is chosen as small as possible under ESD constraints involving the current-handling capabilities of the diode D 1 and topmost transistor Q n .

A first alternative embodiment ESD protection circuit with a silicon controlled rectifier (SCR) is shown in FIG. 2 . The SCR 16 replaces some of the transistors and the diode D 1 of FIG. 1 . In the circuit of FIG. 2 , the resistor R SCR is a parasitic resistance built into the SCR 16 . Alternatively, the resistor R SCR could be external to the SCR 16 . Also, a 2-terminal circuit, such as a diode, could be placed between R SCR and R N to achieve lower voltage triggering.

A second alternative embodiment ESD protection circuit without the diode is shown in FIG. 3 . The Circuit of FIG. 3 is the same as FIG. 1 with diode D 1 removed. The circuit of FIG. 3 is triggered by the collector-base breakdown of the top transistor Q n . A third alternative embodiment ESD protection circuit with a stack of diodes is shown in FIG. 4 . The circuit of FIG. 4 is the same as the circuit of FIG. 1 with the addition of diode D 2 . The additional diode D 2 increases the trigger voltage of the circuit.

A fourth alternative embodiment ESD protection circuit with NMOS transistors is shown in FIG. 5 . In the circuit of FIG. 5 , the transistors Q 1 -Q n of FIG. 1 have been replaced by NMOS transistors T 1 -T n . The parasitic NPN of each of the NMOS transistors T 1 -T n is used in place of each bipolar transistor Q 1 -Q n of FIG. 1 . In FIG. 5 , the gates of the NMOS transistors T 1 -T n are connected to the corresponding source of each transistor. Alternatively, all of the gates of transistors T 1 -T n can be connected to ground node 12 , or the gates can be connected to the corresponding back gate of each transistor.

A fifth alternative embodiment ESD protection circuit with a capacitor is shown in FIG. 6 . The circuit of FIG. 6 is the same as the circuit of FIG. 1 with the addition of capacitor C in parallel with diode D 1 . Capacitor C enhances the transient triggering.

An advantage of the preferred embodiment circuit of FIG. 1 over the prior art is that it uses a single triggering device to simultaneously turn on all NPN transistors. Without effecting the DC holding voltage (e.g. latch-up), the trigger voltage of the ESD circuits of FIGS. 1-6 is lower than that of the conventional prior art circuits which have trigger voltages determined by the sum of the individual circuit trigger voltages. Therefore, better ESD clamping is achieved because the internal circuit to be protected experiences lower over-voltage stress during ESD.

While this invention has been described with reference to an illustrative embodiment, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiment, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. For example, in the circuit of FIG. 1 , the emitter and collector of some of the transistors Q 1 -Q n can be reversed to provide a lower trigger or holding voltage. It is therefore intended that the appended claims encompass any such modifications or embodiments.

Claims

1. An electrostatic discharge protection circuit comprising:at least two bipolar transistors coupled in series; a top one of the at least two bipolar transistors coupled to a protected node; a bottom one of the at least two bipolar transistors coupled to a common node; at least two resistors coupled in series; each of the at least two resistors is coupled to a corresponding base of one of the at least two bipolar transistors; and a bottom one of the at least two resistors coupled between a base of the bottom one of the at least two bipolar transistors and the common node.

2. The circuit of claim 1 wherein the at least two bipolar transistors are NPN bipolar transistors.

3. The circuit of claim 1 further comprising a diode coupled between the protected node and a base of a top one of the at least two bipolar transistors.

4. The circuit of claim 3 wherein the at least two bipolar transistors are NPN bipolar transistors.

5. The circuit of claim 3 further comprising a capacitor coupled in parallel with the diode.

6. The circuit of claim 5 wherein the at least two bipolar transistors are NPN bipolar transistors.

7. The circuit of claim 1 further comprising at least two diodes coupled in series between the protected node and a base of a top one of the at least two bipolar transistors.

8. The circuit of claim 7 wherein the at least two bipolar transistors are NPN bipolar transistors.

9. An electrostatic discharge protection circuit comprising:a silicon controlled rectifier coupled to a protected node; at least one bipolar transistor coupled in series with the silicon controlled rectifier; a bottom one of the at least one bipolar transistor coupled to a common node; at least two resistors coupled in series; a top one of the at least two resistors coupled between the silicon controlled rectifier and a corresponding base of one of the at least one bipolar transistor; and a bottom one of the at least two resistors coupled between a base of the bottom one of the at least one bipolar transistor and the common node.

10. The circuit of claim 1 wherein the at least one bipolar transistor is an NPN bipolar transistor.

11. An electrostatic discharge protection circuit comprising:at least two MOS transistors coupled in series; a top one of the at least two MOS transistors coupled to a protected node; a bottom one of the at least two MOS transistors coupled to a common node; at least two resistors coupled in series; each of the at least two resistors is coupled to a corresponding back gate of one of the at least two MOS transistors; and a bottom one of the at least two resistors coupled between a back gate of the bottom one of the at least two MOS transistors and the common node.

12. The circuit of claim 11 wherein the at least two MOS transistors are NMOS transistors.

13. The circuit of claim 11 wherein a gate of each of the at least two MOS transistors is coupled to a corresponding source of each of the at least two MOS transistors.

14. The circuit of claim 11 wherein a gate of each of the at least two MOS transistors is coupled to the corresponding back gate of each of the at least two MOS transistors.

15. The circuit of claim 13 wherein the at least two MOS transistors are NMOS transistors.

16. The circuit of claim 11 further comprising a diode coupled between the protected node and a back gate of the top one of the at least two MOS transistors.

17. The circuit of claim 16 wherein the at least two MOS transistors are NMOS transistors.