The invention refers to a cell array having a plurality of cell elements integrated on a wafer in a bidimensional cell matrix, in particular a cell array integrated into a digital to analog converter (DAC).
A digital to analog converter (DAC) converts a digital input data word comprising several data bits and outputs an analog output which is proportional to the value of the input binary data word. The analog output signal is e.g. a current, a voltage, a charge or an analog signal or a frequency proportional to the value of the input data word.
An ideal digital to analog converter has an input-output characteristic which is a straight line through the origin as can be seen in FIG. 1. In the digital to analog converter (DAC) according to the state of the art, the actual input-output characteristic is a line which deviates from the ideal straight line, i.e. the input-output characteristic of the conventional digital to analog converter according to the state of the art is a non-linear input-output characteristic. The non-linearity of the input-output characteristic of the conventional digital to analog converter is due to offset and gain errors. Digital to analog converters are integrated circuits which are in most cases implemented as digital to analog converters having an array of cell elements which actually perform the conversion from the digital value to the analog signal. These cell array elements comprise a plurality of cell elements, such as current sources, capacitors, resistors, which are switched by means of switches controlled by the digital input data to be converted. A digital to analog converter (DAC) having a cell array consisting of current sources is designated as a current switch digital to analog converter a (DAC) comprising a cell array of resistor elements is referred to as a resistor string digital to analog converter, and a digital to analog converter (DAC) having a cell array consisting of capacitors and is referred to as a charge redistribution digital to analog converter.
Depending on the application of the digital to analog converter, the cell array is organized substantially in three different possible ways, i.e. as a binary-weighted array, as a thermometric array or as a mixed array.
In the binary-weighted cell array, the dimension of the cell elements goes as the power of two. In a thermometric cell array, all cell elements have the same dimension. In a mixed cell array, a part of the array is thermometer-coded, and the other part of the cell array is binary-coded.
In practical integrated circuits, a mismatch among the cell elements within the cell array of a digital to analog converter exists. The mismatch, i.e. the difference between the actual physical property of the cell element and the nominal property value of the cell element, can occur for several reasons.
The first cause for the mismatch is that the wafer manufacturing process is not completely homogeneous over the whole wafer surface. As a consequence of the inhomogeneous wafer manufacturing process nominal identical cell elements which are placed on the wafer at a certain distance from each other actually show a different physical behavior. The closer the cell elements are located to each other, the lower is the mismatch between both cell elements. For this reason, it is common practice to limit the extension of the wafer area on which the cell elements of the cell array are placed. This is usually accomplished by organizing the cell elements on the wafer in a bidimensional array structure. The non-homogenity of the manufacturing process on the surface of the wafer leads to the presence of a gradient in the physical behavior of the cell elements. This means that a given physical property of the cell elements deviates from its nominal value in a more or less linear fashion along a given direction on the wafer.
In
Another source of mismatch among cell elements leading to a distribution as shown in
The disadvantage of this conventional wiring pattern is that, in the presence of border proximity effects, the integral or accumulated non-linearity of the digital to analog converter is high. Because the cell array is scanned line-wise the cell elements with a higher mismatch, i.e. the cell elements in row 8, as show in
Accordingly, it is the object of the present invention to provide a cell array which has a reduced accumulated mismatch.
This object is achieved by a cell array having novel arrangements of connections and/or configurations.
One embodiment is a cell array having a plurality of cell elements integrated on a wafer in a bidimensional cell matrix, at least one integrated cell element exhibiting a mismatch between its actual physical property and a nominal property value. The mismatch of the at least one cell element is a function of the distance of the respective cell element to a center of the cell array having a bidimensional mismatch distribution. The plurality of cell elements arranged in rows and columns, and the cell elements are connected in series in a wiring pattern. For a plurality of rows of cell elements, each row of cell elements includes more than two series connections to cell elements of one or more other rows. For a plurality of columns of cell elements, each column of cell elements includes more than two series connections to cell elements of one or more other columns.
Accordingly, the above embodiment involves wiring patterns having features that reduce the accumulated mismatch.
In some embodiments, the cell matrix comprises a first number (N) of cell element rows and a second number (M) of cell element columns. Preferably, the first number (N) of cell element rows is equal to the second number (M) of cell element columns.
In some embodiments of the cell array according to the present invention, the cell array is surrounded by dummy cell elements. This provides the advantage that border effects affecting the peripheral cell elements of the cell array are suppressed.
In a preferred embodiment of the cell array according to the present invention, at least three successive elements are connected to elements displaced by one row and one column, thereby forming diagonal connections.
In further embodiments of the cell array according to the present invention, the cell elements are connected in a wiring pattern having a meandrous form.
In further embodiments of the cell array according to the present invention, the cell elements are connected in a wiring pattern having a helical form.
In further embodiments of the cell array according to the present invention, each cell element of the integrated cell array is bridgeable by a corresponding switch. In some embodiments of the cell array, the switches are provided within the integrated cell array. In other embodiments, the switches are provided outside the integrated cell array.
In certain embodiments, these elements may be capacitors, varactors, resistors, current sources, transistors, or diodes.
Another embodiment of the invention is a digital to analog converter having a cell array and a number of dummy cells. The cell array has a plurality of cell elements integrated on a wafer in a bidimensional cell matrix, at least one integrated cell element exhibiting a mismatch between its actual physical property and a nominal property value. The mismatch of the at least one cell element is a function of the distance of the respective cell element to a center of the cell array having a bidimensional mismatch distribution, the plurality of cell elements connected in series in a wiring pattern. The dummy cells extend around a perimeter of the cell array.
The dummy cells extending around the perimeter of the cell array help to reduce the accumulated mismatch of the cells in the array.
In the following, the preferred embodiments of a cell array according to the present invention are described in detail with reference to the enclosed figures.
a, 10b show further wiring patterns for wiring cell elements according to the present invention;
a, 11b show further wiring patterns for wiring cell elements in a cell array according to the present invention;
a, 12b show further wiring patterns for wiring cell elements in a cell array according to the present invention;
a, 13b show further wiring patterns for connecting cell elements within a cell array according to the present invention;
a, 14b show diagrams for illustrating the suppression effect by using dummy cells in a preferred embodiment of the cell array according to the present invention;
a, 15b show wiring patterns for connecting cell elements within a cell array according to the present invention;
a, 17b show resistor strings which are connected in series and shorted by switches according to an embodiment of the present invention;
a, 18b show an embodiment of a cell array employing the resistors as cell elements according to an embodiment of the present invention;
a, 19b show a cell array employing resistors as cell elements according to a further embodiment of the present invention;
a, 21b show a cell array according to the present invention wherein the number of columns deviates from the number of rows;
In the embodiment shown in
As can be seen from
In the embodiment shown in
If the first eight cell elements C18, C28, C38, . . . , C88 are connected according to the state of the art wiring pattern as shown in
In case that the eight cell elements are connected with the wiring patent according to the present invention as shown in
In this case, the DAC output is (1−96*ε/28)+(1+ε)+(1+2*ε)+(1+3*ε)+(1−96*ε/28)+(1+ε)+(1+2*ε)+(1−96*ε/28)
The integral non-linearity error amounts in this case to a mere −1.3*ε.
As can be seen from this example, the integral non-linearity of a cell matrix using a wiring pattern according to the present invention is drastically reduced in comparison to a conventional cell matrix having a conventional wiring pattern.
For the 6×6 cell element matrix, ten equations are provided for wiring the cell elements.
Computation of the left and right region:
Consequently, a wiring pattern as shown in
a shows a possible wiring patent according to the present invention, wherein the cell elements are connected in a meandrous form. The generated series connection of the cell elements has two terminals A1, A2.
In
a shows a further embodiment of a wiring pattern according to the present invention. In this embodiment, the cell elements are connected in series in a helical form wherein the cell element chain has two terminals A1, A2.
b shows a further embodiment of the wiring pattern according to the present invention wherein two helical chains are interlocked with each other. The first cell element chain comprises terminals A1, A2 and the second cell element chain comprises terminals B1, B2.
a shows a further wiring pattern according to the present invention with two interlocked cell element chains wherein the cell elements are connected to each other along diagonals having 45 degrees with respect to the rows and columns of the matrix. The structure has the advantage that each cell element of a chain has both cell elements of its own chain and cell elements of the other chain as neighboring cell elements. This provides in particular an advantage when two cell elements of the cell matrix are interacting.
b shows an alternative wiring structure with two interlocked cell element chains.
Each of the embodiments described above and shown in
a, 13b show a 12×12 cell array having a wiring structure according to the present invention to improve the integral non-linearity of a thermometer-coded digital to analog converter.
In a preferred embodiment as shown in
b shows the configuration of the cell array with the active cell elements surrounded by dummy cell elements.
a, 14b show diagrams for illustrating the suppression of border effects in a 6×6 cell element matrix. Inner cell elements are surrounded on all sides by further cell elements, as can be seen in
a shows a preferred embodiment of a cell array having a wiring pattern according to the present invention. The cell elements are connected in such a manner that all triangular configurations are bound together.
b shows a further embodiment with an improved interconnection of the triangular configuration wherein only two long-distance interconnections are provided. The first long-distance interconnection is between cell elements C0,6 and C0,11 and the second long-distance interconnection is between cell elements C5,11 and C11,10.
a shows a first resistor string within series-connected resistors R11-R18 which can be shorted by using bridging switches S11-S18. As can be seen in
a, 18b show an alternative embodiment wherein the switches S11-S18 are placed inside the resistor array according to the present invention.
a shows a different version of the embodiment shown in
b shows a more general configuration of the cell elements which are connected in parallel and controlled via a bus. The integral non-linearity is reduced by applying a wiring pattern according to the present invention. In preferred embodiments, the shown cell arrays are surrounded by dummy cell elements which are identical with the cell elements inside the active cell array.
In the example shown in
In the example shown in
b shows the topology of a preferred embodiment of the cell array according to the present invention wherein the resistors are connected in series and can be short-circuited by switches which are provided outside the cell array. The cell array comprises three terminals A1, A2, A3.
As can be seen from
a shows a part of a chain of cell elements which are bridgeable by means of switches.
b shows an embodiment of a cell array having a wiring pattern or wiring structure according to the present invention. The cell array comprises two terminals A1, A2 which are connected to each other by a chain of resistors which are connected in series according to a wiring pattern according to the present invention. In the given example, the cell array comprises 8×8 resistors so that the resistor chain comprises 64 resistors connected in series. To each resistor a corresponding switch is connected in parallel and can be controlled by an external digital signal. In the embodiment shown in
The inverting amplifying as shown in
Number | Name | Date | Kind |
---|---|---|---|
6204794 | Bult | Mar 2001 | B1 |
6452152 | Yang | Sep 2002 | B1 |