Many circuits include transistors. An example of a transistor is a field effect transistor (FET) such as an n-channel FET (NFET) or a p-channel FET (PFET). An NFET is turned ON by injecting current into the gate of the transistor to cause the voltage of the gate relative to the source to exceed the threshold voltage (Vt) of the transistor. In some applications, the source of the transistor is not connected to the ground of the circuit. For example, in the case of a high side FET coupled to a low side FET between a supply voltage and ground (a configuration that is typical of, for example, motor controllers, switching voltage regulators, etc.), the source of the high side FET is (or is connected to) the switch node for the circuit and is a voltage (relative to ground) that changes during each switching cycle.
In such applications, a controller drives (possibly, through a driver circuit) a digital signal (e.g., a voltage) to cause the high side FET to turn ON. The controller is coupled to circuit ground and its digital signal is a voltage with respect to circuit ground. To turn ON the high side FET, a gate driver coupled to the gate of the FET must produce a sufficient voltage on the gate of the high side FET with respect to the switch node voltage, which is a different voltage than circuit ground.
In some such applications, a signal isolator is included between the controller and the gate driver for the high side FET. The signal isolator is coupled to circuit ground and to the ground reference for the high side FET (e.g., the switch node). The signal isolator isolates the ground reference of the controller from the ground reference of the gate driver for the high side FET.
In one example, a transformer includes a substrate and a first metal layer having a first inductor having a first center tap. A second metal layer includes a second inductor having a second center tap, and the second metal layer includes a bond pad. A third metal layer includes a first conductor electrically connecting the bond pad to the first center tap, and the third metal layer includes a second conductor electrically connecting the bond pad and the first center tap. The third metal layer is situated between the substrate and the first metal layer, and the first metal layer is situated between the third metal layer and the second metal layer.
For a detailed description of various examples, reference will now be made to the accompanying drawings in which:
The same reference numbers or other reference designators are used in the drawings to designate the same or similar (either by function and/or structure) features.
A transformer can be figured to include a primary winding and a secondary winding such that the certain signals at the primary winding may be isolated from the secondary winding (and vice versa). Therefore, such transformers can provide the signal isolation described above, although other uses of the transformer described herein are possible as well. The example transformer described herein is a center-tapped transformer (each of the primary and secondary coils has a center tap) that is constructed in such a way to reduce the conversion of common mode voltage (e.g., a voltage whose value is relative to a common potential, such as ground) to a differential voltage (e.g., a voltage whose value is the difference between the voltages at two differential terminals). A common mode voltage may be, for example, a common mode noise that is present on the ground terminals of the transformer's coils. The described transformer also has a relatively high common mode rejection ratio (CMRR).
A bond pad is provided in the interior space defined by each concentric ring 221, 223. Bond pad 235 is provided in interior space 227 defined by concentric ring 221, and bond pad 238 is provided in interior space 237 defined by concentric ring 223. The interior space defined by each of the concentric rings may be filled with a suitable material such as dielectric material (e.g., silicon dioxide). Reference identifier PROJ1 identifies a projection of the interior space 227 along an axis normal to the plane of the concentric ring 221. Similarly, PROJ2 identifies a geometric projection of the interior space 237 along an axis normal to the plane of the concentric ring 223. A separate bond wire 112 is coupled to each of the bond pads 235 and 238 as well as the center tap CT1, as shown. Alternatively, a ball may be formed on each bond pad for wafer-scale packaging.
Starting at bond pad 235 within the concentric ring 221, the conductive lines of ring 221 wrap around the interior space 227 in a counterclockwise direction. The exterior connection point 215 of ring 221 couples to one end of the center tap CT1. The opposing end of the center tap CT1 is coupled to exterior connection point 216 of concentric ring 223. The conductive lines of concentric ring 223 wrap around the interior space 237 in a clockwise fashion and end at interior connection point 217 which is coupled to a bond pad 238. In this configuration, current that flows in one direction through concentric ring 221 flows in the opposite direction through concentric ring 223. For example, current that flows clockwise through concentric ring 221 flows counterclockwise through concentric ring 223, and current that flows counterclockwise through concentric ring 221 flows clockwise through concentric ring 223.
Inductor L2 similarly includes concentric rings 231 and 233 coupled to opposing ends of a center tap CT2. The metal layer in which inductor L2 is formed is between the substrate 210 and the metal layer in which inductor L1 is formed. An isulating layer (comprised of one or more layers of insulating material, such as silicon dioxide, silicon nitride, silicon oxynitride and/or a mixture thereof) is formed between L2 and L1 and between L2 and substrate 210. The concentric rings 231 and 233 of inductor L2 generally align vertically with the concentric rings 221 and 223 of inductor L1. The interior spaces of the concentric rings 231 and 233 also generally align with the interior spaces 227 and 237 of the concentric rings 221 and 223. The interior space projections PROJ1 and PROJ2 correspond to the projections of the interior spaces of the concentric rings for both inductors L1 and L2.
As shown in this example, inductors L1 and L2 are formed in a stacked arrangement. Bond pads 235 and 238 at opposing terminals of inductor L1, as well as center tap CT1, are readily exposed to receive bond wires 112. However, the corresponding connections to inductor L2 are in a metal layer between the metal layer in which inductor L1 is formed and the substrate 210 and thus may not be available for receiving bond wire connections. Instead, bond pads 241, 242, and 243 are provided to the side of the inductors L1 and L2. For example, if L2 is formed by the metal-2 layer and L1 is formed by the metal-3 layer, the metal-1 layer may be used to form the interconnections with L2 and bond pads 241, 242 and 243. Bond pads 241, 242, and 243 may be formed in the same metal layer as the layer that includes inductor L2 or they may be formed in the layer that includes inductor L1 (e.g., using vias/interconnections between the metal layer that L2 is formed and the metal layer that L1 is formed). Bond pads 241 and 243 are coupled to opposing terminals of inductor L2 by way of conductive lines 244 and 245, respectively. Bond pad 242 is coupled to the center tap CT2 of inductor L2 by way of two (or more) separate conductive lines 251 and 252. As explained below, the bifurcated connection between center tap CT2 and its bond pad 242 results in transformer 130 having a higher CMRR and lower common mode-to-differential voltage conversion, which results in the transformer having a higher degree of radiated noise immunity.
In one embodiment, the shape of the concentric rings is rectangular with curved corners, as shown. In this embodiment, each ring is defined by straight segments with approximately curved corners. In other embodiments, the rings may be circular, oval, or another suitable shape.
The projections PROJ1 and PROJ2 of the interiorspaces 227 and 237, respectively, described above are shown in
If, instead of a bifurcated conductive line connection between bond pad 252 and centertap CT2, a single conductive line 413 may be used to connect the bond pad to the centertap. The conductive line 413 would be outside the projections PROJ1 and PROJ2, and current injected into bond pad 242 would flow from the bond pad 242 in the direction of arrow 421 into the centertap CT2. From the centertap CT2, a portion of the current would flow clockwise in concentric ring 231, and another portion of the current would flow clockwise in concentric ring 233. Current on the righthand side of concentric ring 231 would flow in the direction of arrow 422, and current on the lefthand side of concentric ring 231 would flow in the direction of arrow 423. Current on the lefthand side of concentric ring 233 would flow in the direction of arrow 424, and current on the righthand side of concentric ring 233 would flow in the direction of arrow 425.
The righthand side of concentric ring 231 is closer to the single conductive line 413 than the lefthand side of concentric ring 231. The direction of current flow in condutive line 413 (arrow 421) is the same as the direction of current flow in the closer righthand side of concentric ring 231 (arrow 422). However, due to current flowing in the opposite direction in concentric ring 231, the direction of current flow in condutive line 413 (arrow 421) is opposite that of current flow in the closer lefthand side of concentric ring 233 (arrow 424). As a result of current flow 421 and 422 being in the same direction but current flow 421 and 424 being in opposing directions, the mutual inductance is larger as between conductive line 413 and the righthand side of concentric ring 231 than between conducitve line 413 and the lefthand side of concentric ring 233.
The embodiments described herein bifurcate the connection between bondpad 242 and centertap CT2 to include conductive lines 251 and 252. Because each conductive line 251 and 252 passes through the projection of the interior spaces defined by the inductor's concentric rings 231 and 233, the mutual inductance between each conductive line 251, 252 and the lefthand and righthand sides of its respective concentric ring generally cancels. Current that flows from bond pad 242 in the direction of arrow 431 through conductive line 251 is in the same direction as arrow 422 and in the opposite direction as arrow 423. Similarly, current that flows from bond pad 242 in the direction of arrow 432 through conductive line 252 is in the same direction as arrow 425 and in the opposite direction as arrow 424. This configuration of conductive lines 251 and 252 improves the symmetry of the transformer and has been shown by simulation-based analysis to reduce the conversion of common mode voltage to differential voltage conversion.
Inductors 631 and 632 comprise windings 631a and 632a, respectively, that are interleaved as identified in
Current injected into, for example, bond pad 601 enters terminal 661 and flows counterclockwise as indicated by arrows 671 (
The source of the LS transistor is coupled to circuit ground 711, which is the same ground reference used by the controller 702. The controller 702 produces output signals OUT1 and OUT2 to turn ON and OFF the corresponding HS and LS FETs. The voltage levels of OUT1 and OUT2 are referenced with respect to circuit ground 711. Isolator 704 has separate ground terminals connected to grounds 709 and 711 as shown. The isolator 704 includes the center-tapped transformer 130 described herein to provide isolation between grounds 709 and 711.
In this description, the term “couple” may cover connections, communications, or signal paths that enable a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform an action: (a) in a first example, device A is coupled to device B by direct connection; or (b) in a second example, device A is coupled to device B through intervening component C if intervening component C does not alter the functional relationship between device A and device B, such that device B is controlled by device A via the control signal generated by device A.
As used herein, the terms “terminal”, “node”, and “interconnection” are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to mean an interconnection between or a terminus of a device element, a circuit element, an integrated circuit, a device or other electronics or semiconductor component. Likewise, the terms “lead”, “pin” and “ball” are used interchangeably to mean an external interconnection of a semiconductor device.
A circuit or device that is described herein as including certain components may instead be adapted to be coupled to those components to form the described circuitry or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and/or inductors), and/or one or more sources (such as voltage and/or current sources) may instead include only the semiconductor elements within a single physical device (e.g., a semiconductor die and/or integrated circuit (IC) package) and may be adapted to be coupled to at least some of the passive elements and/or the sources to form the described structure either at a time of manufacture or after a time of manufacture, for example, by an end-user and/or a third-party.
While the use of particular transistors are described herein, other transistors (or equivalent devices) may be used instead with little or no change to the remaining circuitry. For example, a metal-oxide-silicon FET (“MOSFET”) (such as an n-channel MOSFET, nMOSFET, or a p-channel MOSFET, pMOSFET), a bipolar junction transistor (BJT—e.g. NPN or PNP), insulated gate bipolar transistors (IGBTs), and/or junction field effect transistor (JFET) may be used in place of or in conjunction with the devices disclosed herein. The transistors may be depletion mode devices, drain-extended devices, enhancement mode devices, natural transistors or other type of device structure transistors. Furthermore, the devices may be implemented in/over a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN) or a gallium arsenide substrate (GaAs).
While certain elements of the described examples are included in an integrated circuit and other elements are external to the integrated circuit, in other example embodiments, additional or fewer features may be incorporated into the integrated circuit. In addition, some or all of the features illustrated as being external to the integrated circuit may be included in the integrated circuit and/or some features illustrated as being internal to the integrated circuit may be incorporated outside of the integrated. As used herein, the term “integrated circuit” means one or more circuits that are: (i) incorporated in/over a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated into the same module; and/or (iv) incorporated in/on the same printed circuit board.
Uses of the phrase “ground” in the foregoing description include a chassis ground, an Earth ground, a floating ground, a virtual ground, a digital ground, a common ground, and/or any other form of ground connection applicable to, or suitable for, the teachings of this description. In this description, unless otherwise stated, “about,” “approximately” or “substantially” preceding a parameter means being within +1-10 percent of that parameter, or, if the parameter is zero, a reasonable range of values around zero.
Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.