This disclosure relates generally to the field of circuit protection devices and more particularly to ceramic chip fuses.
Fuses, which are commonly used as circuit protection devices, provide electrical connections between sources of electrical power and circuit components that are to be protected. Chip fuses, also known as thin-film fuses, surface-mount fuses, or SMD fuses, are one type of fuse that includes a fusible element disposed between non-conductive layers of material. Conductive terminals are connected to each end of the fusible element to provide a means of connecting the fuse within a circuit. Upon the occurrence of a specified fault condition in a circuit, such as an overcurrent condition, the fusible element can melt, or otherwise separate, to interrupt current flow in the circuit path. Protected portions of the circuit are thereby electrically isolated and damage to such portions may be prevented or at least mitigated.
Chip fuses are often used to provide protection to components on a printed circuit board. As will be appreciated, real estate on printed circuit boards is very limited. Furthermore, chip fuses are often used in high voltage, high current, and/or high temperature environments necessitating the need for stability and performance reliability.
Some chip fuses are mounted on and/or enclosed in a rigid substrate (e.g., FR4, or the like) to provide support to the fuse and ensure that when the fuse link interrupts in response to a fault condition, the fuse body is not ruptured. Rupturing of the fuse body can cause damage to the components to be protected as well as adjacent components on the printed circuit board. The rigid substrate also adds additional size as well as cost to the chip fuse.
Thus, there is a need for a chip fuse that provides high voltage and current interruption capabilities and is reliable for use in high temperature environments, but which is small enough to satisfy design constraints for printed circuit board use.
In accordance with the present disclosure, a fuse is disclosed. The fuse may include a plurality of non-conductive layers, a fuse element disposed between ones of the plurality of ceramic layers such that more ceramic layers are above the fuse element than below the fuse element in a first direction, and first and second conductive terminals electrically connected to the fuse element to connect the fuse to a circuit to be protected and a source of power.
In some examples, a ceramic chip fuse comprised of multiple ceramic layers in which a fuse element is placed off-center in the vertical axis is provided. In some examples, the fuse element is positioned below the centerline of the fuse with respect to the vertical axis such that that the thickness of ceramic above the fuse element is greater than the thickness of ceramic below the element. The additional ceramic thickness above the element provides that the fuse may reliably interrupt high voltages. Particularly, the additional ceramic thickness above the element provides that the fuse may reliably interrupt high voltages without rupturing.
By way of example, specific embodiments of the disclosed device will now be described, with reference to the accompanying drawings, in which:
In general, the present disclosure provides a ceramic chip fuse comprised of multiple ceramic layers in which a fuse element is placed off-center on the vertical axis. Said differently, the present disclosure provides layers of non-conductive material (e.g., ceramic) stacked with a fuse element disposed off-center in the vertical direction of the stack. In some examples, the fuse element is positioned below the centerline of the fuse with respect to the vertical axis such that that the thickness of ceramic above the fuse element is greater than the thickness of ceramic below the element. The additional ceramic thickness above the element provides that the fuse may reliably interrupt high voltages.
The chip fuse 300 is depicted including layers 320-1 to 320-8, which the fuse element 310 disposed between (e.g., “sandwiched” between) layers 320-6 and 320-7. Said differently, the fuse element 310 is disposed between the non-conductive layers 320 such that more non-conductive layers 320 are above the fuse element 310 than below. That is, the fuse element 310 is disposed below the centerline of the vertical axis 342 of the chip fuse 300.
In general, the fuse element 310 may be any material having desirable electrically conductive properties. In some examples, the fuse element 310 may be nickel, copper, silver, gold, tin, or an alloy or mixture comprising, nickel, copper, silver, gold, or tin. With some examples, the fuse element 310 may have a thickness between 0.02 and 5 mils. Additionally, with some examples, the non-conductive layers 320 may be ceramic, such as, for example, alumina. With some examples, the non-conductive layers 320 may have a thickness between 0.5 and 20 mils and the terminals may be formed from any conductive materials, such as, for example, silver, copper, tin, nickel, or any combination of such materials.
It is to be appreciated, that the number of layers depicted in
Continuing to block 620, a number of other layers may be stacked onto the first layer. For example, the layers 320-1 to 320-6 are stacked on top of the layer 320-7 in
Continuing to block 630, the layers and the fuse element are fired to form a fuse body. For example, the non-conductive layers 320 and the fuse element 310 may be fired to form the fuse body 360 shown in
Continuing to block 640, first and second fuse terminals may be formed on the fuse body. For example, the first and second conductive terminals 332 and 334 may be formed on the fuse body 360. In some examples, the materials (e.g., the materials being the first and second fuse terminals formed by dipping and/or plating) may be formed by dipping and/or plating the ends of the fuse body.
Continuing to block 720, a number of additional layers (which form a second layer) may be stacked onto the fuse element and the first layer such that second layer non-conductive material is greater in thickness/width than the first portion of non-conductive material. The additional secondary layers (second layer) and the first layer surround and protect the fuse element. For example, the layers 320-1 to 320-6 are stacked on top of the layer 320-7 in
Continuing to block 730, the layers and the fuse element are co-fired using one of a variety of firing processes at a temperature between 500 and 1000 degrees Celsius for between 10 minutes and 90 minutes to form a fuse body. For example, the non-conductive layers 320 and the fuse element 310 may be co-fired to form the fuse body 360 shown in
Continuing to block 740, first and second fuse terminals may be formed on the fuse body. For example, the first and second conductive terminals 332 and 334 may be formed on the fuse body 360. In some examples, the materials may be formed by dipping and/or plating the ends of the fuse body.
In view of the forgoing, it is evident that providing a ceramic chip fuse comprised of multiple ceramic layers in which a fuse element is placed off-center on the vertical axis provides that the fuse may reliably interrupt high voltages. Said differently, by providing layers of non-conductive material (e.g., ceramic) stacked with a fuse element disposed off-center in the vertical direction of the stack, such as disposing the fuse element below the centerline of the fuse with respect to the vertical axis such that that the thickness of ceramic above the fuse element is greater than the thickness of ceramic below the element, allows the fuse to ensure that when the fuse link interrupts in response to a fault condition, the fuse body is not ruptured. Moreover, the ceramic chip fuse, as described herein, prevents the fuse body from being ruptured without adding additional size as well as cost to the chip fuse. Hence the ceramic chip fuse provides high voltage and current interruption capabilities and is reliable for use in high temperature environments, but which is small enough to satisfy design constraints for printed circuit board use.
The present disclosure is not to be limited in scope by the specific embodiments described herein. Indeed, other various embodiments of and modifications to the present disclosure, in addition to those described herein, will be apparent to those of ordinary skill in the art from the foregoing description and accompanying drawings. Thus, such other embodiments and modifications are in the tended to fall within the scope of the present disclosure. Furthermore, although the present disclosure has been described herein in the context of a particular implementation in a particular environment for a particular purpose, those of ordinary skill in the art will recognize that its usefulness is not limited thereto and that the present disclosure may be beneficially implemented in any number of environments for any number of purposes. Thus, the claims set forth below should be construed in view of the full breadth and spirit of the present disclosure as described herein.
This application claims the benefit of U.S. Provisional Patent Application Ser. No. 61/925,862, filed Jan. 10, 2014, the entirety of which application is incorporated by reference herein.
Number | Date | Country | |
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61925862 | Jan 2014 | US |