Chained Hybrid IOMMU

Abstract

In one embodiment, an input/output (I/O) node comprises an I/O memory management unit (IOMMU) configured to translate memory requests. The I/O node is configured to couple to an interconnect and to operate as a tunnel on the interconnect, and wherein the IOMMU is configured translate memory requests passing through the tunnel in the upstream direction. In another embodiment, a system comprises another I/O node configured to bridge another interconnect to the interconnect, wherein the I/O node is the tunnel for the other I/O node.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The following detailed description makes reference to the accompanying drawings, which are now briefly described.

FIG. 1 is a block diagram of a high level view of one embodiment of a computer system.

FIG. 2 is a block diagram of one embodiment of a HyperTransport™ chain of devices.

FIG. 3 a flowchart illustrating operation of one embodiment of an IOMMU shown in FIG. 2.

FIG. 4 is a block diagram of an example of using IOMMUs in some downstream nodes and not in other nodes.

FIG. 5 is a block diagram of one embodiment of a device table entry for a device table shown in FIG. 2.

Claims

1. An input/output (I/O) node comprising: an I/O memory management unit (IOMMU) configured to translate memory requests; andthe I/O node is configured to couple to an interconnect and to operate as a tunnel on the interconnect, and wherein the IOMMU is configured to translate memory requests passing through the tunnel in the upstream direction on the interconnect.

2. The I/O node as recited in claim 1 wherein the I/O node is configured to transmit translated memory requests on the interconnect from one more I/O devices coupled to the I/O node, and wherein the translated memory request from the one or more I/O devices comprises a device identifier assigned to the I/O node on the interconnect.

3. The I/O node as recited in claim 1 wherein the IOMMU comprises a control register programmable with an enable indication indicating whether or not translation of the memory requests passing through the tunnel is enabled, wherein the IOMMU is configured to translate the memory requests passing through the tunnel if the enable indication indicates enabled, and wherein the IOMMU is configured to pass the memory requests unmodified if the enabled indication indicates disabled.

4. The I/O node as recited in claim 1 wherein the IOMMU is configured to access a device table comprising a plurality of device table entries, wherein the IOMMU is configured to select a device table entry responsive to a device identifier (ID) from a given memory request passing through the tunnel.

5. The I/O node as recited in claim 4 wherein the IOMMU is configured to pass the given memory request unmodified if the device table entry corresponding to the given memory request indicates that translation is disabled.

6. The I/O node as recited in claim 5 wherein the device table entry with translation disabled is useable for a downstream node on the interconnect that includes an IOMMU.

7. The I/O node as recited in claim 4 wherein the IOMMU is configured to select another device table entry responsive to a device identifier corresponding to one of one or more I/O devices bridged by the I/O node to translate a memory request sourced by the I/O device.

8. A system comprising: a first input/output (I/O) node configured to bridge a first interconnect to a second interconnect; anda second I/O node configured to bridge a third interconnect to the second interconnect, wherein the first I/O node is coupled to the second I/O node via the second interconnect, and wherein the second I/O node is configured to operate as a tunnel for memory requests from the first I/O node travelling upstream, and wherein the second I/O node comprises an I/O memory management unit (IOMMU) configured to translate memory requests from the third interconnect and to translate memory requests from the first I/O node.

9. The system as recited in claim 8 wherein the translated memory request from the third interconnect comprises a device identifier assigned to the I/O node on the second interconnect.

10. The system as recited in claim 8 wherein the IOMMU comprises a control register programmable with an enable indication indicating whether or not translation of the memory requests from the first I/O node is enabled, wherein the IOMMU is configured to translate the memory requests from the first I/O node if the enable indication indicates enabled, and wherein the IOMMU is configured to pass the memory requests from the first I/O node unmodified if the enabled indication indicates disabled.

11. The system as recited in claim 8 wherein the IOMMU is configured to access a device table comprising a plurality of device table entries, wherein the IOMMU is configured to select a device table entry responsive to a device identifier (ID) from a given memory request from the first I/O node

12. The system as recited in claim 11 wherein the IOMMU is configured to pass the given memory request unmodified if the device table entry corresponding to the given memory request indicates that translation is disabled.

13. The system as recited in claim 11 wherein the IOMMU is configured to select another device table entry responsive to a device identifier corresponding to an I/O device on the third interconnect, to translate a memory request sourced by the I/O device.

14. A method comprising: receiving a memory request travelling upstream on a first interconnect in an input/output (I/O) node that operates as a tunnel on the first interconnect;translating the memory request using an I/O memory management unit in the I/O node; andforwarding the translated memory request further upstream.

15. The method as recited in claim 14 further comprising the translating is further responsive to an enable indication that controls whether or not translation of memory requests travelling in the tunnel is enabled.

16. The method as recited in claim 14 wherein the translating comprises accessing a device table entry by the IOMMU.

17. The method as recited in claim 16 further comprising: accessing the device table entry for a second memory request travelling upstream, wherein the device table indicates that translation is disabled for the second memory request; andforwarding the second memory request further upstream unmodified.

18. The method as recited in claim 17 further comprising translating the second memory request prior to the I/O node receiving the second memory request.