The present invention relates to data processing and more particularly to data processing in a communication device.
Virtually all systems perform communications, either internally and/or externally between different systems. Wireless devices or mobile stations such as cellular handsets and other wireless systems transmit and receive radio frequency (RF) information including representations of speech waveforms. A physical layer of a cellular handset typically includes circuitry for performing two major functions, namely encoding and decoding. This circuitry includes a channel codec for performing channel encoding and decoding functions and a vocoder for performing voice encoding and decoding functions. The vocoder performs source encoding and decoding on speech waveforms. Source coding removes redundancy from the waveform and reduces the bandwidth (or equivalently the bit-rate) in order to transmit the waveform in real-time. The channel codec increases redundancy in the transmitted signal to enhance the robustness of the transmitted signal.
A number of different wireless protocols exist. One common protocol is referred to as global system for mobile communications (GSM). Typical GSM and other communications systems that employ error correction coding such as forward error correction (FEC) generally use a two-stage receiver architecture having an equalizer and a decoder. The function of the equalizer is to compensate for adverse channel effects, while the function of the decoder is to recover original data bits from the encoded sequence. It is also common practice to employ an interleaving scheme to avoid large gaps in the received data if the channel conditions degrade temporarily. After deinterleaving, degraded data symbols are spread amongst a large number of reliable symbols, allowing the decoder a chance to correctly decode the degraded symbols. In many applications, data are transmitted and received in finite-length packets or bursts. Interleaving in such systems is done over multiple bursts, and hence decoding occurs after a certain number of bursts have been received. For example, in a GSM system data are interleaved over a range of 2 to 22 bursts depending on the logical channel in use. The equalizer, on the other hand, generally works on each burst separately.
Because FEC adds redundancy to payload data, in some communication systems such coding is only applied to the most important data (e.g., bits). For optimal performance, an equalizer provides a decoder with “soft decisions” rather “hard decisions” or bits. A soft decision carries information about what the received bit is and a reliability number for the bit. The soft decisions from each burst are stored in a buffer until enough data are available for the decoder to operate. One design parameter in a system that employs FEC is the precision (e.g., number of bits) to be used for storing the soft information. This parameter is a tradeoff between performance increases with an increasing number of bits and increased cost of storing larger numbers of bits per soft metric.
Another design parameter is the format of the soft metrics. Two common formats used to represent soft metrics are 1's and 2's complement numbers. Because most programmable processors use 2's complement arithmetic, if the soft metrics are in 1's complement representation, additional pre-processing to convert numbers to 2's complement is done before performing arithmetic operations. This conversion process may be repeated several times for each soft metric, which increases complexity. If instead 2's complement representation is used, which has only one representation for zero, a bias may occur when slicing (i.e, processing) low precision 2's complement soft metrics to obtain uncoded bits. In other words, 2's complement representation loses the distinction between 0− and 0+ that is maintained by a 1's complement representation. This loss in resolution is equivalent to an offset bias (referred to as a bias problem or a bias effect) in the soft metrics for uncoded bits, which will cause degradation in bit error rate (BER) performance on the uncoded bits. These two design parameters (i.e., precision and format of soft decisions) thus lead to tradeoffs that are not ideal for any system.
In one embodiment, the present invention includes a method for receiving channel data via a transmission channel, generating a hard decision and a soft decision for each bit of the channel data in an equalizer, and storing the hard decisions in a first buffer and storing the soft decisions in a second buffer. Each of the soft decisions may be quantized before their storage, while the hard decisions may be generated based on a corresponding unquantized soft decision. Using these hard and soft decisions, the channel data may be decoded in one of a number of different manners, depending on a type of data received.
Other embodiments may be implemented in an apparatus, such as an integrated circuit (IC). The IC may include an equalizer to generate hard decisions and soft decisions for incoming data, a first buffer to store the hard decisions, and a second buffer to store the soft decisions. The equalizer may generate the hard decisions from corresponding unquantized soft decisions, where the soft decisions are in a 2's complement representation. The IC may further include a decoder coupled to the equalizer to decode the incoming data based on the hard decisions and the soft decisions. As an example, the IC may take the form of a digital signal processor (DSP), and the buffers may be implemented in a storage of the DSP.
Embodiments of the present invention may be implemented in appropriate hardware, firmware, and software. To that end, a method may be implemented in hardware, software and/or firmware to handle decoding of data, e.g., of a wireless device via hard and soft decisions. The method may perform various functions including determining a soft decision for each incoming baseband data and determining a corresponding hard decision from the soft decision, and decoding at least one of the hard decision and the soft decision for each of the baseband data to generate a symbol corresponding to the baseband data. In some implementations, only a single one of the hard decision and the soft decision may be decoded, while in other implementations both decisions may be decoded, at least for certain types of data.
In one embodiment, a system in accordance with an embodiment of the present invention may be a wireless device such as a cellular telephone handset, personal digital assistant (PDA) or other mobile device. Such a system may include a transceiver, as well as digital circuitry. The digital circuitry may include circuitry such as an IC that includes at least some of the above-described hardware, as well as control logic to implement the above-described methods.
In various embodiments, an equalizer may generate both hard decisions and soft decisions for all received data. Further, the soft decisions may be stored in a 2's complement format, thus avoiding conversion before every arithmetic operation. The hard decisions may be generated before the corresponding soft decisions are quantized for storage, avoiding the bias problem. In other words, the equalizer may obtain hard decisions by slicing high precision (e.g., 16 bit) 2's complement soft metrics. An equalizer in accordance with one embodiment may be used in various communication systems including wireless devices, wired devices, and even within a single data processing system such as between discrete components of a computer system, among many other systems.
Referring to
While shown as including a number of particular components in the embodiment of
DSP 10 may be adapted to perform various signal processing functions on audio data. While discussed in the context of audio processing, other data may also be processed by the embodiment of
The audio samples may be collected and stored in the buffer until a complete data frame is stored. While the size of such a data frame may vary, in embodiments used in a time division multiple access (TDMA) system, a data frame (also referred to as a “speech frame”) may correspond to 20 ms of real-time speech (e.g., corresponding to 160 speech samples). In various embodiments, the input buffer may hold 20 ms or more of speech data from ADC 18. As will be described further below, an output buffer (not shown in
The buffered data samples may be provided to an audio processor 30a for further processing, such as equalization, volume control, fading, echo suppression, echo cancellation, noise suppression, automatic gain control (AGC); and the like. From front-end processor 30a, data are provided to a vocoder 35 for encoding and compression. As shown in
In the downlink direction, incoming RF signals may be received by antenna 70 and provided to RF circuitry 60 for conversion to baseband signals. The transmission chain then occurs in reverse such that the modulated baseband signals are coupled through components of the downlink direction. As shown in
When sufficient data is stored in DI buffers 48b, e.g., corresponding to a number of data bursts, the data may be provided to channel decoder 45b of codec 40. Channel decoder 45b may deinterleave the data from buffers 48b and perform decoding, for example, FEC decoding. The channel coded data is then provided to a speech decoder 42b of vocoder 35, and then in turn to an audio processor 30b, and DAC 22 (via a buffer, in some embodiments) to obtain analog audio data that is coupled to, for example, a speaker 8 of the handset.
For purposes of further illustration, the discussion is with respect to a representative GSM/general packet radio service (GPRS)/EDGE/TDMA system (generally a “GSM system”). However, other protocols may implement the methods and apparatus disclosed herein, particularly where data received by a system or a component of such a system is coded, for example, FEC-coded.
A GSM system makes use of a TDMA technique, in which each frequency channel is further subdivided into eight different time slots numbered from 0 to 7. Each of the eight time slots may be assigned to an individual user in GSM system, while multiple slots can be assigned to one user in a GPRS/EDGE system. A set of eight time slots is referred to herein as a TDMA frame, and may be a length of 4.615 ms. A 26-multiframe is used as a traffic channel frame structure for the representative system. The total length of a 26-frame structure is 26*4.615 ms=120 msec. In a GSM system, a speech frame is 20 msec while a radio block is 4 TDMA frames, which is 4*4.615=18.46 msec. Thus every three radio blocks the TDMA frame or radio block boundary and the speech frame boundaries are aligned.
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Shown in Table 1 below are different representations of four-bit reliability metrics.
As shown in Table 1, each of a 1's complement, 2's complement and decimal representation of reliability factors, i.e., soft metrics are shown. Further as shown in Table 1, the reliability metrics are shown in a descending reliability order for the negative range (i.e., a value of −8 has the greatest reliability, while a value of −0 has the lowest reliability), while the positive range is shown is an ascending reliability (i.e., +7 has the highest reliability value, while +0 has the least reliability). Due to the inherent nature of 1's complement and 2's complement representations, certain reliability values are not available. Specifically, as shown in Table 1, a soft metric of −8 does not have 1's complement representation. Furthermore, a 2's complement representation has no value for a −0 metric reliability measure. Although a 2's complement representation does not have an analog for a negative zero value, a hard decision corresponding to this level may be accurate, as it is generated prior to the quantization value in Table 1. Thus bias errors are
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However, other implementations are possible, and in many implementations the size of the soft decision buffer(s) may be substantially larger than the hard decision buffer(s). In the described implementations, the soft buffer may be at least two times greater than the hard decision buffer and more particularly at least four times and even up to sixteen times greater. Furthermore, while described as separate buffers, in some embodiments a single memory may include all of the buffers. For example, with reference back to
Although two separate buffers are used for hard and soft decisions, in various implementations memory usage may actually decrease. That is, hard decisions use only 1 bit per symbol and thus may be packed 16 to a word. This minimal memory consumption may be used instead of increased precision of soft metrics, which would consume significantly greater memory.
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For example, when the decoder decodes multiple bursts of data, e.g., corresponding to a radio block, the decoder may determine a specific logical channel being used. In other words, the decoder may determine the type of coding, if any, applied to the received data. In some implementations, so-called stealing flags may be decoded to determine a given logical channel. For example, in a GPRS mode, the decoder can determine what logical channel is to be decoded before any deinterleaving is done. Therefore, depending on the logical channel, the decoder may perform only one deinterleave operation from either the soft buffer (e.g., for CS1/2/3 which use FEC) or from the hard buffer (e.g., for CS-4 which is uncoded). Thus, based on a determination of the given logical channel, one or both buffers may be deinterleaved, as will be discussed further below.
In other implementations, e.g., in a GSM system, speech channels may have certain burst portions encoded, while other burst portions are uncoded. For example, in one GSM implementation, full-rate speech may be transmitted in blocks of 260 bits, in which the first 182 bits are considered class one bits and are encoded, while the final 78 bits are class two bits and are not encoded. In such implementations, the soft decision buffer may first be deinterleaved and decoded, and then a portion of the hard buffer corresponding to the uncoded bits may be deinterleaved, thus overwriting the soft decisions for the uncoded bits. Still further, additional data transmitted with voice information, e.g., control information may also be encoded.
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If instead at diamond 165 it is determined that all of the data is not encoded, this implicitly means that instead all data is uncoded, as is the case for CS-4 logical channel data. Accordingly, control passes from diamond 165 to block 175. There, only the hard buffer may be deinterleaved (block 175). Then the deinterleaved symbols may be provided to the speech decoder (block 178).
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Thus although in some implementations both the hard and soft decisions are deinterleaved in the decoder, computational complexity may be minimized. In different implementations, deinterleaving may take various forms, depending on the type of data to be decoded. As an example, all data in both hard and soft buffers may be deinterleaved. However, to reduce computation, not all bits are deinterleaved twice. Instead, only the uncoded bits may be deinterleaved from both the hard and soft buffers, with the deinterleaved decision from the soft buffer being overwritten by the hard decision.
The methods described herein may be implemented in software, firmware, and/or hardware. A software implementation may include an article in the form of a machine-readable storage medium onto which there are stored instructions and data that form a software program to perform such methods. As an example, a DSP may include instructions or may be programmed with instructions stored in a storage medium to perform equalization and decoding in accordance with an embodiment of the present invention.
Referring now to
Incoming RF signals are provided to a transceiver 310 which may be a single chip transceiver including both RF components and baseband components. Transceiver 310 may be formed using a complementary metal-oxide-semiconductor (CMOS) process, in some embodiments. As shown in
In some embodiments, transceiver 310 may correspond to ASIC 15 of
After processing signals received from RF transceiver 312, baseband processor 314 may provide such signals to various locations within system 300 including, for example, an application processor 320 and a memory 330. Application processor 320 may be a microprocessor, such as a central processing unit (CPU) to control operation of system 300 and further handle processing of application programs, such as personal information management (PIM) programs, email programs, downloaded games, and the like. Memory 330 may include different memory components, such as a flash memory and a read only memory (ROM), although the scope of the present invention is not so limited. Additionally, a display 340 is shown coupled to application processor 320 to provide display of information associated with telephone calls and application programs, for example. Furthermore, a keypad 350 may be present in system 300 to receive user input.
Thus, in various embodiments an equalizer may generate both hard decisions and 2's complement soft decisions for all data bits, and a corresponding decoder deinterleaves data from either the soft buffer, hard buffer, or from both depending on the specific channel data. For a given performance level, embodiments may reduce computational complexity and memory usage for systems where the minimum precision of soft metrics is dictated by the bias term. Accordingly, embodiments of the present invention are computationally more efficient, as arithmetic operations may be performed without format conversion. Still further, reduced memory usage may be afforded, as the separate buffers allow reduced precision in storage of the soft metrics.
While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.