Patent Application
20240264965
Aspects of the present disclosure relate generally to computer information systems, and more particularly, to communications systems for coupling components of computer information systems. Some features may enable and provide improved bus or interconnect capabilities for reducing power consumption.
Computer information systems may include many components including expansion circuit boards (such as mother and daughter cards), integrated circuit (IC) devices, and/or System-on-Chip (SoC) devices. The components may include processing circuits, user interface components, storage components, and/or other peripheral components. Communication between components may be implemented using a bus. The bus may be operated in compliance with standards-defined specifications and protocols. One example of such a specification-defined interface to a bus is the Peripheral Component Interconnect Express (PCIe) interface. PCIe provides a shared parallel bus architecture that supports interconnection of two devices using links that include one or more serial, full-duplex lanes.
The value and use of information by individuals continues to increase, as do computational requirements. Computational processes performed by computer information systems rely on busses to transmit interface components, so that each component may perform an assigned task. The tasks may include processing, compiling, storing, and/or communicating information for business, personal, or other purposes thereby allowing users to take advantage of the value of the information. Technology and information handling needs and requirements vary between different users and different applications and different computer information systems, such that there may be differences in how the information is handled, processed, stored, or communicated. The variations in information handling allow for computer information systems to be general or configured for a specific user or specific use, such as financial transaction processing, airline reservations, enterprise data storage, or global communications. The buses that interconnect components of computer information systems components are generally capable of supporting the use of the information to increase the value of the information but also provide specialized features to support certain operations or increase performance when performing certain tasks or kinds of information.
The following summarizes some aspects of the present disclosure to provide a basic understanding of the discussed technology. This summary is not an extensive overview of all contemplated features of the disclosure and is intended neither to identify key or critical elements of all aspects of the disclosure nor to delineate the scope of any or all aspects of the disclosure. Its sole purpose is to present some concepts of one or more aspects of the disclosure in summary form as a prelude to the more detailed description that is presented later.
Certain aspects of this disclosure relate to systems, apparatus, methods and techniques that provide dynamic bandwidth control by adjusting a directionality of wires within a lane for a PCIe bus interface or other bus interface in a computer information system, such as a mobile communication device. In some aspects, the direction of transmission over wires of a bus between a first component (e.g., a PCIe endpoint or PCIe root complex) and another component (e.g., a PCIe root complex or PCIe endpoint) may be negotiated to allow asymmetric connections.
Asymmetric connections involve an unequal number of wires for transmission and reception in the bus, such that the data rate achievable for one direction of transmission may be increased by reducing the data rate achievable for the other direction of transmission. The asymmetric configuration for lanes of the bus may be configured based on a configuration of a component communicating on the bus. For example, certain components may have workloads that have asymmetric data transfers, such as a graphics processing unit (GPU) that may input larger amounts of data (e.g., textures, geometric representations of scenes) but output smaller amounts of data (e.g., a rendered frame). The asymmetric configuration for lanes of the bus may be also or additionally be configured based on a workload of a component coupled to the bus. For example, a component with a large file to store in a storage device may have a large workload for transmission over the bus in one transfer direction during which only small acknowledgements are received from the storage device in the other transfer direction.
In some aspects, the bus interface may be implemented in battery-operated devices, including certain mobile communication devices. Mobile devices may be designed to meet increasingly tighter power consumption budgets in order to increase operating time while operating from a battery or other limited power supply. Aspects of this disclosure may be used in mobile communication devices to improve power efficiency or reduce power consumption when transmitting information between components coupled to a bus. As applications generate continuously-increasing demand for improved communication capabilities including higher data rates, lower data transmission latencies and improved battery conservation, there exists an ongoing need for improved power management that may be addressed by certain aspects of this disclosure.
The systems, apparatus, methods and techniques described herein may be incorporated into logic circuitry as a bus interface and built in an integrated circuit (IC) on a semiconductor die. The IC may be integrated into other components, such as a central processing unit (CPU) (including an applications processor), a graphics processing unit (GPU), a controller for a storage device (e.g., a universal flash storage (UFS) device or a multimedia memory card (MMC) device), a communications processor (e.g., a wireless modem for 3G, 4G LTE, 5G NR, Wi-Fi, Bluetooth, or a wireline transceiver for Ethernet).
The methods and techniques may also or alternatively be incorporated into instructions for storage as firmware or software in a computer readable medium, such as random access memory (RAM) or read-only memory (ROM). The instructions may be executed by the logic circuitry to cause a component executing the instructions to communicate over a bus through the bus interface.
An apparatus in accordance with at least one embodiment includes a bus interface configured to support communications between a first component coupled to a bus and a second component coupled to the bus. The bus interface may include logic configured to perform operations for formatting data and generating signals for transmission on the bus to convey the data along with control information and perform operations for processing signals received from the bus and extracting information from the signals. The bus interface may also include logic configured to perform operations to facilitate connections from the first component to the second component over the bus, such as by performing link training, link negotiation, link monitoring, and/or link adaptation.
In one aspect of the disclosure, a method for communicating on a bus through a bus interface includes transmitting a link configuration change request to a component through a bus to reconfigure the link from a first link configuration to a second link configuration, the second link configuration indicating at least one lane configuration indicating a bidirectional lane, a unidirectional transmit lane, or a unidirectional receive lane; and communicating over the bus based on the link configuration change.
In another aspect of the disclosure, a method for communicating on a bus through a bus interface includes receiving a link configuration change request from a component through a bus to reconfigure the link from a first link configuration to a second link configuration, the second link configuration indicating at least one lane configuration indicating a bidirectional lane, a unidirectional transmit lane, or a unidirectional receive lane; and communicating over the bus based on the link configuration change request.
In an additional aspect of the disclosure, an apparatus includes at least one processor and a memory coupled to the at least one processor. The at least one processor is configured to perform one or more operations of the methods, operations, and/or techniques described herein. The processor may be logic circuitry in a host component. The host component may be a component of a computer information system, such as an applications processor, a graphics processing unit (GPU), a controller of a storage device, a communications processor (e.g., a modem for 3G, 4G LTE, 5G NR, Wi-Fi, Bluetooth, or a wireline transceiver for Ethernet). The host component communicates over a bus in accordance with the method of communicating on a bus.
In an additional aspect of the disclosure, an apparatus includes means for performing one or more operations of the methods, operations, and/or techniques described herein. For example, an apparatus, such as a host component, may include a bus interface for communicating on the bus, in which the bus interface includes means for transmitting a link configuration change request to the component through the bus to reconfigure the link from a first link configuration to a second link configuration, the second link configuration indicating at least one lane configuration indicating a bidirectional lane, a unidirectional transmit lane, or a unidirectional receive lane, means for receiving a link configuration change request from the component through the bus to reconfigure the link from a first link configuration to a second link configuration, the second link configuration indicating at least one lane configuration indicating a bidirectional lane, a unidirectional transmit lane, or a unidirectional receive lane, and/or means for communicating over the bus based on the link configuration change request.
Other aspects, features, and implementations will become apparent to those of ordinary skill in the art, upon reviewing the following description of specific, exemplary aspects in conjunction with the accompanying figures. While features may be discussed relative to certain aspects and figures below, various aspects may include one or more of the advantageous features discussed herein. In other words, while one or more aspects may be discussed as having certain advantageous features, one or more of such features may also be used in accordance with the various aspects. In similar fashion, while exemplary aspects may be discussed below as device, system, or method aspects, the exemplary aspects may be implemented in various devices, systems, and methods.
The method may be embedded in a computer-readable medium as computer program code comprising instructions that cause a bus interface to perform the steps of the method. In some embodiments, the bus interface may be integrated with a processor that is part of a mobile device including a first network adaptor coupled to the processor through the bus interface with the first network adaptor configured to transmit data (e.g., images or videos in a previously-recorded file or as streaming data) over a first network connection of a plurality of network connections. The processor may be coupled to the first network adaptor and a memory for storing data through a common bus interface or multiple bus interfaces to support the processing and communications operations performed by the processor. The network adaptor may support communication over a wireless communications network such as a 5G NR communication network. The processor may cause the transmission of data by retrieving the data stored in memory over a bus interface, package the data for transmission on a selected network, and transmit the packaged data through the bus interface to the first network adaptor for transmission on the wireless communication network.
The foregoing has outlined, rather broadly, the features and technical advantages of examples according to the disclosure in order that the detailed description that follows may be better understood. Additional features and advantages will be described hereinafter. The conception and specific examples disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present disclosure. Such equivalent constructions do not depart from the scope of the appended claims. Characteristics of the concepts disclosed herein, both their organization and method of operation, together with associated advantages will be better understood from the following description when considered in connection with the accompanying figures. Each of the figures is provided for the purposes of illustration and description, and not as a definition of the limits of the claims.
While aspects and implementations are described in this application by illustration to some examples, those skilled in the art will understand that additional implementations and use cases may come about in many different arrangements and scenarios. Innovations described herein may be implemented across many differing platform types, devices, systems, shapes, sizes, and packaging arrangements. For example, aspects and/or uses may come about via integrated chip implementations and other non-module-component based devices (e.g., end-user devices, vehicles, communication devices, computing devices, industrial equipment, retail/purchasing devices, medical devices, artificial intelligence (AI)-enabled devices, etc.).
While some examples may or may not be specifically directed to use cases or applications, a wide assortment of applicability of described innovations may occur. Implementations may range in spectrum from chip-level or modular components to non-modular, non-chip-level implementations and further to aggregate, distributed, or original equipment manufacturer (OEM) devices or systems incorporating one or more aspects of the described innovations.
In some configurations, devices incorporating described aspects and features may also include additional components and features for implementation and practice of claimed and described aspects. For example, transmission and reception of wireless signals may includes a number of components for analog and digital purposes (e.g., hardware components including antenna, radio frequency (RF)-chains, power amplifiers, modulators, buffer, processor(s), interleaver, adders/summers, etc.). Innovations described herein may be practiced in a wide variety of devices, chip-level components, systems, distributed arrangements, end-user devices, etc. of varying sizes, shapes, and constitution.
A further understanding of the nature and advantages of the present disclosure may be realized by reference to the following drawings. In the appended figures, similar components or features may have the same reference label. Further, various components of the same type may be distinguished by following the reference label by a dash and a second label that distinguishes among the similar components. If just the first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label irrespective of the second reference label.
Like reference numbers and designations in the various drawings indicate like elements.
The detailed description set forth below, in connection with the appended drawings, is intended as a description of various configurations and is not intended to limit the scope of the disclosure. Rather, the detailed description includes specific details for the purpose of providing a thorough understanding of the inventive subject matter. It will be apparent to those skilled in the art that these specific details are not required in every case and that, in some instances, well-known structures and components are shown in block diagram form for clarity of presentation.
The present disclosure provides systems, apparatus, methods, and computer-readable media that support data processing, including techniques for identifying data rate consumption of components coupled to a bus and determining a redistribution of the transmission and reception line pairs inside a link to accommodate different data rate requirements for transmission and reception.
Particular implementations of the subject matter described in this disclosure may be implemented to realize one or more of the following potential advantages or benefits. In some aspects, the present disclosure provides reduced power consumption by allowing the link configuration to accommodate a higher data in one direction. The higher data rate may decrease the amount of time used on the bus to complete an input/output (I/O) operation. A faster operation (completing in a shorter period of time) allows the link to return to a low power state quicker than conventionally possible with a fixed symmetric configuration of the link.
According to certain aspects, a bus interface, such as a PCIe bus interface, may be used to interconnect electronic devices that are subcomponents of an apparatus such as a cellular phone, a smart phone, a session initiation protocol (SIP) phone, a laptop, a notebook, a netbook, a smartbook, a personal digital assistant (PDA), a satellite radio, a global positioning system (GPS) device, a smart home device, intelligent lighting, a multimedia device, a video device, a digital audio player (e.g., MP3 player), a camera, a game console, an entertainment device, a vehicle component, a wearable computing device (e.g., a smart watch, a health or fitness tracker, eyewear, etc.), an appliance, a sensor, a security device, a vending machine, a smart meter, or any other similar functioning device.
The apparatus 120 includes an application-specific integrated circuit (ASIC) 122 that has one or more application processors 132 (e.g., a heterogenous mix of processors of different configurations, such as performance cores and efficiency cores), one or more modems 130 (e.g., baseband modems), and/or other logic circuits or functions. The apparatus 120 may be controlled by a basic input/output system (BIOS), firmware, and/or an operating system and may provide an application programming interface (API) layer that enables the one or more processors 132 to execute software modules residing in the memory device 134. The software modules may include instructions and data stored in a processor readable storage such as the memory device 134.
The ASIC 122 may access an internal memory, the memory device 134 (external to the ASIC 122), and/or storage devices included in peripheral devices 136 or storage devices outside the apparatus 120. Memory may include read-only memory (ROM) or random-access memory (RAM), electrically erasable programmable ROM (EEPROM), flash cards, or any memory device that can be used in processing systems and computing platforms. The ASIC 122 may include, or have access to, a local database or other parameter storage that maintains operational parameters and other information used to configure and operate the ASIC 122 and/or the apparatus 120. The local database may be implemented using registers, a database module, flash memory, magnetic media, EEPROM, optical media, tape, soft or hard disk, or the like. The apparatus 120 may also be operably coupled to external devices such as the antennas 142, a display, user interface 124 (e.g., a button, an integrated or external keypad, and/or a touch screen).
The apparatus 120 may communicate through a bus interface circuit 128, which may include a combination of fabrics, circuits, counters, timers, control logic and/or other configurable circuits or modules. In one example, the bus interface circuit 128 may be configured to operate in accordance with PCIe specifications and protocols. The apparatus 120 may include or control a power management function that configures and manages the bus interface 128, the user interface 124, the RF front-end circuit 126, and the operation of one or more application processors 132 resident in the ASIC 122. In certain modes of operation, the bus interface circuit 128 may be configured to transition between power states based on activity of the bus interface 128.
The bus interface 128 operates using one or more links. In an embodiment of apparatus 120 implementing a PCIe bus, the bus interface 128 may operate using high-speed serial links. The PCIe bus interface 128 may be characterized as having a point-to-point topology, with separate dual simplex point-to-point serial connections (e.g., link 140) connecting each device to a host, or root complex. The link 140 may have scalable link widths (e.g., ×1, ×2, ×4, ×8, ×16) and may have scalable link speeds (e.g., 2.5, 5.0, 8.0, 16.0 GT/s). The link 140 may be operated according to a packet-based transaction protocol and implement, optionally, data integrity and error handling, credit-based flow control, interrupt handling, and/or advanced power management. One or more transaction types may be supported by the link 140 including a memory read or memory write (used to transfer data to or from a memory-mapped location), a I/O read or I/O write (used to transfer data to or from an I/O location, such as a legacy endpoint), a configuration read or configuration write (used to discover device capabilities, features, and/or check a status of a component), or messaging (used to signal events or provide general purpose information).
The root complex 204 may control communication between the processor 202 the memory subsystem 208 and/or other PCIe endpoint devices 210, 212A, 212B, . . . , 212N. An endpoint device 210, 212A, 212B, . . . , 212N may be a device other than the root complex 204 that is capable of requesting or initiating a PCIe transaction or responding to (e.g., completing) a PCIe transaction. The root complex 204 may store a master copy of a Type 1 Configuration Table that defines a host memory space that is accessible from each endpoint device. Each PCIe endpoint may store a master copy of the endpoint's own memory space map in the host system memory as a Type 0 Configuration Table. Each device's configuration table allows the host to access the local memory of a PCIe device. The configuration tables may be setup by a host operating system that controls the root complex 204 by a process known as enumeration, which acts to build a device memory map for the system by querying each bridge and endpoint 210, 212A-N coupled to the bus network.
Information to be communicated using the PCIe interface 200 is encapsulated in packets in accordance with PCIe bus protocols. Devices coupled to a PCIe bus may communicate over links 222 using one or more PCIe lanes contained within the link. The number of lanes within each link 222 may be referred to as the width of the link. A PCIe lane may be defined as a point-to-point communication channel between two PCIe ports. A PCIe lane may provide full-duplex communication and may include two differentially encoded pairs of signaling wires or signal traces, with one pair of wires being used for transmitting data and the other pair of wires being used for receiving data. Packets may carry information in eight-bit bytes. In a multi-lane PCIe link, packet data may be striped across multiple lanes. The number of lanes in the multi-lane link may be negotiated during device initialization.
Each of the links 222 in the bus of
Example lane configurations for the links 222 are shown in
A link configuration 322 for the link 320 may specify a direction for each of the lanes of the link 320. Example direction indicators may include a bidirectional lane (bD), a unidirectional transmit lane (uTx), or a unidirectional receive (uRx) lane. In some embodiments, the lane may include more than two pairs of wires and there may be more than 3 lane configurations for each lane.
A link may include more than two lanes, although only two lanes are shown in
A method of reconfiguring a link to support different bandwidths for transmit and receive is shown in
One example algorithm is to monitor a fill level of a buffer for the link, in which a bandwidth change criteria is satisfied when the fill level exceeds a threshold level or exceeds a threshold level for a predetermined amount of time. Another example algorithm is to receive hints from a higher level, such as through an application programming interface (API), indicating a change in an upcoming change in bandwidth demands. A further example algorithm is to monitor an average transmission rate and if the transmission rate meets a threshold level for a predetermined period of time then bandwidth change criteria are satisfied.
At block 404, the method 400 includes a first, transmitting device coupled to the bus transmitting a link configuration change request to a second, receiving device through the bus to reconfigure the link from a first link configuration to a second link configuration. The configuration change request may be based on certain criteria being satisfied in block 402. In some embodiments, multiple criteria may be specified for the determination of block 402 and each criteria may also specify a resulting link configuration to apply at block 404. The determination of bandwidth change criteria may include monitoring the utilization of bandwidth for transmit and/or receive during operation of the link at the first link configuration. For example, the bandwidth may be monitored to determine that the transmit lanes are more than a threshold level (e.g., 80%) utilized.
The link configuration change request of block 404 may indicate a new configuration for the lanes in the link. The link configuration change request may include a link configuration value that indicates a second link configuration for the bus to reconfigure to from its current, first link configuration. The link configuration value may indicate a lane configuration specifying, for each lane, a bidirectional lane, a unidirectional transmit lane, or a unidirectional receive lane. In some embodiments, the link configuration value may be a single value that corresponds to a predetermined lane configuration. For example, a value of 1 may correspond to link configuration 322 shown in
A handshake process at block 405 may follow the initiation of a configuration change of block 404. One example handshake process may include link recovery and configuration operations on the bus. When the handshake process completes successfully, the method 400 may continue to block 406.
At block 406, the method 400 includes a first device communicating over the bus based on the link configuration change. If the second link configuration increases a number of wires available for transmission then the communication at block 406 may increase a data rate of transmission. If the second link configuration increases a number of wires available for receiving then the communication at block 406 may increase a data rate of receiving. After a transaction is completed at the link configuration, the link may be switched to a low-power state to reduce power consumption.
An example reconfiguration operation for a link is shown in
The first device 410 may be a requestor device and may transmit a lane weight redistribution request 420 to the second device 412, which may be a completer device. The second device 412 may acknowledge 422 the lane weight redistribution request 420, after which the link between the first device 410 and the second device 412 enters into a recovery/configuration path 424. The lanes may be reconfigured between the three types of bidirectional, unidirectional transmit, and unidirectional receive, according to weights in a configuration state of the link.
One example reconfiguration may be performed in a link configuration state controlled by a Link Training and Status State Machine (LTSSM) for a PCIe bus interface to bring up an appropriate number of lanes according to the link configuration of block 404. The LTSSM may define several top-level states including Detect, Polling, Configuration, Recovery, L0, L0s, L1, L2, Hot Reset, Loopback and Disable. These top-level states may be grouped into five categories: Link Training states, Re-Training (Recovery) state, Software driven Power Management states, Active-State Power Management states, and Other states. The flow of the LTSSM follows the Link Training states when exiting from a Reset (e.g., from Detect to Polling to Configuration to L0). In the L0 state, normal packet transmission/reception may proceed. The Recovery State may be used for a variety of reasons, such as changing back from a low-power Link state, such as L1, or changing the link Bandwidth.
During this recovery state the directions of lanes may be reconfigured 428 and, optionally, the training performed for the lanes. In some embodiments, the lane weights are communicated as part of the redistribution request 420 and used to update a configuration register 426 within the bus interface at each of the first device 410 and the second device 412. In some embodiments, the lane weights are communicated in a message subsequent to the redistribution request 420 and used to update a configuration register within the bus interface.
In some embodiments, a register in the bus interface includes a reserved 8-bit configuration register to configure the weights (e.g., C0, C1, and C2 corresponding to bD, uTx, and uRx, respectively) for the link. There are 2n-1 possible configurations, thus with nmax=32, (2n-1)max=63, which can be represented through 6 bits. An example configuration register for the weights may be defined according to the following table:
Also, in this configuration state, the link repeats as much of the training process as needed to configure and returns to the L0 state. Power management software may also place a device into a low-power device state forcing the link into a lower Power Management Link state (e.g., L1 or L2). If there are no packets to send for a predetermined time, period power management software may be allowed to transition the link into low power ASPM states (e.g., L0 or ASPM L1). In addition, software may direct a link to enter another special state (e.g., Disabled, Loopback, Hot Reset)
After the link is reconfigured 428, communications may continue on the reconfigured lanes 430. The reconfiguration may allow, for example, a large read operation to a storage device to reconfigure additional lanes or substantially all (e.g., all except one reserved for bidirectional) lanes for unidirectional receive to increase the data rate and thus reduce the transfer time.
In some embodiments, the link reconfiguration may include changing a data rate or other signaling aspect of one or more lanes. For example, a PCIe link may be reconfigured between different generations of signaling to achieve higher or lower data rates. For example, a link may be reconfigured between Gen1 (2.5 GT/s), Gen 2 (5 GT/s), Gen3 (8 GT/s), and Gen4 (16 GT/s). In some embodiments, individual lanes may be reconfigured to a different generation or control other signaling characteristics of the link.
An example reconfiguration of a PCIe link with four lanes between two endpoints operating at Gen1 (which supports 250 MB/s per wire pair) is shown in the table below:
Conventionally, a PCIe link only supports case 4 in which all lanes are bidirectional, resulting in a symmetric link configuration. According to aspects of this disclosure, different numbers of lanes may be allocated for different directions of transfer, which provides flexibility in the bus configuration to support a variety of different devices that may be present in an electronic device, such as a mobile communication device that performs many different functions. As described in the example above, reconfiguring the bus for data transfer to a storage device may be useful when a large data file is queued for reading or writing to the storage device to decrease the amount of time the link is out of low-power state to perform the transfer. As another example, a network interface, such as a wireless modem, may have changing bandwidth requirements, such as when a large file is transmitted to a cloud server (which involves a large transmit operation from memory to the modem) or when a video is downloaded from the Internet (which involves a large receive operation from the modem to the storage device).
A similar operation may be performed by the second device, or receiving device, coupled to the first device through the bus.
At block 504, the second, receiving device, communicates over the bus based on the link configuration change.
Operations of methods 400 or 500 may be performed by a user equipment (UE), a base station (BS), other communications device, or other computer information system, such as any of the devices described with reference to
Wireless network 600 illustrated in
A base station may provide communication coverage for a macro cell or a small cell, such as a pico cell or a femto cell, or other types of cell. A macro cell generally covers a relatively large geographic area (e.g., several kilometers in radius) and may allow unrestricted access by UEs with service subscriptions with the network provider. A small cell, such as a pico cell, would generally cover a relatively smaller geographic area and may allow unrestricted access by UEs with service subscriptions with the network provider. A small cell, such as a femto cell, would also generally cover a relatively small geographic area (e.g., a home) and, in addition to unrestricted access, may also provide restricted access by UEs having an association with the femto cell (e.g., UEs in a closed subscriber group (CSG), UEs for users in the home, and the like). A base station for a macro cell may be referred to as a macro base station. A base station for a small cell may be referred to as a small cell base station, a pico base station, a femto base station or a home base station. In the example shown in
Wireless network 600 may support synchronous or asynchronous operation. For synchronous operation, the base stations may have similar frame timing, and transmissions from different base stations may be approximately aligned in time. For asynchronous operation, the base stations may have different frame timing, and transmissions from different base stations may not be aligned in time. In some scenarios, networks may be enabled or configured to handle dynamic switching between synchronous or asynchronous operations.
UEs 615 are dispersed throughout the wireless network 600, and each UE may be stationary or mobile. It should be appreciated that, although a mobile apparatus is commonly referred to as a UE in standards and specifications promulgated by the 3GPP, such apparatus may additionally or otherwise be referred to by those skilled in the art as a mobile station (MS), a subscriber station, a mobile unit, a subscriber unit, a wireless unit, a remote unit, a mobile device, a wireless device, a wireless communications device, a remote device, a mobile subscriber station, an access terminal (AT), a mobile terminal, a wireless terminal, a remote terminal, a handset, a terminal, a user agent, a mobile client, a client, a gaming device, an augmented reality device, vehicular component, vehicular device, or vehicular module, or some other suitable terminology. Within the present document, a “mobile” apparatus or UE need not necessarily have a capability to move, and may be stationary. Some non-limiting examples of a mobile apparatus, such as may include implementations of one or more of UEs 615, include a mobile, a cellular (cell) phone, a smart phone, a session initiation protocol (SIP) phone, a wireless local loop (WLL) station, a laptop, a personal computer (PC), a notebook, a netbook, a smart book, a tablet, and a personal digital assistant (PDA). A mobile apparatus may additionally be an IoT or “Internet of everything” (IoE) device such as an automotive or other transportation vehicle, a satellite radio, a global positioning system (GPS) device, a global navigation satellite system (GNSS) device, a logistics controller, a smart energy or security device, a solar panel or solar array, municipal lighting, water, or other infrastructure; industrial automation and enterprise devices; consumer and wearable devices, such as eyewear, a wearable camera, a smart watch, a health or fitness tracker, a mammal implantable device, gesture tracking device, medical device, a digital audio player (e.g., MP3 player), a camera, a game console, etc.; and digital home or smart home devices such as a home audio, video, and multimedia device, an appliance, a sensor, a vending machine, intelligent lighting, a home security system, a smart meter, etc. In one aspect, a UE may be a device that includes a Universal Integrated Circuit Card (UICC). In another aspect, a UE may be a device that does not include a UICC. In some aspects, UEs that do not include UICCs may also be referred to as IoE devices. UEs 615a-615d of the implementation illustrated in FIG. A are examples of mobile smart phone-type devices accessing wireless network 600. A UE may also be a machine specifically configured for connected communication, including machine type communication (MTC), enhanced MTC (eMTC), narrowband IoT (NB-IoT) and the like. UEs 615e-615k illustrated in
A mobile apparatus, such as UEs 615, may be able to communicate with any type of the base stations, whether macro base stations, pico base stations, femto base stations, relays, and the like. In FIG. A, a communication link (represented as a lightning bolt) indicates wireless transmissions between a UE and a serving base station, which is a base station designated to serve the UE on the downlink or uplink, or desired transmission between base stations, and backhaul transmissions between base stations. UEs may operate as base stations or other network nodes in some scenarios. Backhaul communication between base stations of wireless network 600 may occur using wired or wireless communication links.
In operation at wireless network 600, base stations 605a-605c serve UEs 615a and 615b using 3D beamforming and coordinated spatial techniques, such as coordinated multipoint (CoMP) or multi-connectivity. Macro base station 605d performs backhaul communications with base stations 605a-605c, as well as small cell, base station 605f. Macro base station 605d also transmits multicast services which are subscribed to and received by UEs 615c and 615d. Such multicast services may include mobile television or stream video, or may include other services for providing community information, such as weather emergencies or alerts, such as Amber alerts or gray alerts.
Wireless network 600 of implementations supports mission critical communications with ultra-reliable and redundant links for mission critical devices, such UE 615e, which is a flying device. Redundant communication links with UE 615e include from macro base stations 605d and 605e, as well as small cell base station 605f. Other machine type devices, such as UE 615f (thermometer), UE 615g (smart meter), and UE 615h (wearable device) may communicate through wireless network 600 either directly with base stations, such as small cell base station 605f, and macro base station 605e, or in multi-hop configurations by communicating with another user device which relays its information to the network, such as UE 615f communicating temperature measurement information to the smart meter, UE 615g, which is then reported to the network through small cell base station 605f. Wireless network 600 may also provide additional network efficiency through dynamic, low-latency TDD communications or low-latency FDD communications, such as in a vehicle-to-vehicle (V2V) mesh network between UEs 615i-615k communicating with macro base station 605e.
In various implementations, the techniques and apparatus may be used for wireless communication networks such as code division multiple access (CDMA) networks, time division multiple access (TDMA) networks, frequency division multiple access (FDMA) networks, orthogonal FDMA (OFDMA) networks, single-carrier FDMA (SC-FDMA) networks, LTE networks, GSM networks, 5th Generation (5G) or new radio (NR) networks (sometimes referred to as “5G NR” networks, systems, or devices), as well as other communications networks. As described herein, the terms “networks” and “systems” may be used interchangeably. A CDMA network, for example, may implement a radio technology such as universal terrestrial radio access (UTRA), cdma2000, and the like. UTRA includes wideband-CDMA (W-CDMA) and low chip rate (LCR). CDMA2000 covers IS-2000, IS-95, and IS-856 standards. A TDMA network may, for example implement a radio technology such as Global System for Mobile Communication (GSM). The 3rd Generation Partnership Project (3GPP) defines standards for the GSM EDGE (enhanced data rates for GSM evolution) radio access network (RAN), also denoted as GERAN. An OFDMA network may implement a radio technology such as evolved UTRA (E-UTRA), Institute of Electrical and Electronics Engineers (IEEE) 802.11, IEEE 802.16, IEEE 802.20, flash-OFDM and the like. UTRA, E-UTRA, and GSM are part of universal mobile telecommunication system (UMTS). In particular, long-term evolution (LTE) is a release of UMTS that uses E-UTRA. The various different network types may use different radio access technologies (RATs) and RANs.
While aspects and implementations are described in this application by illustration to some examples, those skilled in the art will understand that additional implementations and use cases may come about in many different arrangements and scenarios. Innovations described herein may be implemented across many differing platform types, devices, systems, shapes, sizes, packaging arrangements. For example, implementations or uses may come about via integrated chip implementations or other non-module-component based devices (e.g., end-user devices, vehicles, communication devices, computing devices, industrial equipment, retail devices or purchasing devices, medical devices, AI-enabled devices, etc.). While some examples may or may not be specifically directed to use cases or applications, a wide assortment of applicability of described innovations may occur. Implementations may range from chip-level or modular components to non-modular, non-chip-level implementations and further to aggregated, distributed, or original equipment manufacturer (OEM) devices or systems incorporating one or more described aspects. In some practical settings, devices incorporating described aspects and features may also necessarily include additional components and features for implementation and practice of claimed and described aspects. It is intended that innovations described herein may be practiced in a wide variety of implementations, including both large devices or small devices, chip-level components, multi-component systems (e.g., radio frequency (RF)-chain, communication interface, processor), distributed arrangements, end-user devices, etc. of varying sizes, shapes, and constitution.
In one or more aspects, techniques for supporting data transfer through a bus, may include additional aspects, such as any single aspect or any combination of aspects described below or in connection with one or more other processes or devices described elsewhere herein. In various aspects listed below, an electronic device, such as a UE or BS, may be an apparatus that includes a bus configured to couple components of the electronic device, in which a bus interface is provided to facilitate communications on the bus by the components.
In a first aspect, the bus interface may be configured to perform operations including transmitting a link configuration change request to a component through a bus to reconfigure the link from a first link configuration to a second link configuration, the second link configuration indicating at least one lane configuration indicating a bidirectional lane, a unidirectional transmit lane, or a unidirectional receive lane; and communicating over the bus based on the link configuration change.
In a second aspect, in combination with the first aspect, the second link configuration indicates a plurality of lane configurations, each of the plurality of lane configurations corresponding to a lane of the link.
In a third aspect, in combination with one or more of the first aspect or the second aspect, at least one lane configuration of the first link configuration is bidirectional and at least one lane configuration of the second link configuration is bidirectional.
In a fourth aspect, in combination with one or more of the first aspect through the third aspect, the link configuration change request includes a first value indicating a first number of lanes of the link configured as a bidirectional lane, a second value indicating a second number of lanes of the link configured as a unidirectional transmit lane, and a third value indicating a third number of lanes of the link configured as a unidirectional receive lane.
In a fifth aspect, in combination with one or more of the first aspect through the fourth aspect, the method may further include determining a characteristic for a workload of the component, wherein the characteristic indicates at least one of a transmit data rate and a receive data rate on the bus, wherein the link configuration change request is based on the characteristic for the workload.
In a sixth aspect, in combination with one or more of the first aspect through the fifth aspect, transmitting the link configuration change request comprises transmitting a lane weight redistribution request to the component, receiving an acknowledge of the lane weight redistribution request from the component, and reconfiguring the link with a new lane weight distribution according to the second link configuration, wherein the communicating over the bus based on the link configuration change is after the reconfiguring the link.
In a seventh aspect, in combination with one or more of the first aspect through the sixth aspect, the second link configuration indicates a data rate for each lane of the at least one lane configuration.
In an eighth aspect, in combination with one or more of the first aspect through the seventh aspect, storing a value corresponding to a link configuration for the link in a register.
In a ninth aspect, in combination with one or more of the first aspect through the eighth aspect, the transmitting is performed by a bus interface comprising a peripheral component interconnect express (PCIe) interface.
In a tenth aspect, in combination with one or more of the first aspect through the ninth aspect, the component comprises a PCIe endpoint or a PCIe root complex.
In an eleventh aspect, in combination with one or more of the first aspect through the tenth aspect, a method includes receiving a link configuration change request from a component through a bus to reconfigure the link from a first link configuration to a second link configuration, the second link configuration indicating at least one lane configuration indicating a bidirectional lane, a unidirectional transmit lane, or a unidirectional receive lane; and communicating over the bus based on the link configuration change request.
In a twelfth aspect, in combination with one or more of the first aspect through the eleventh aspect, the second link configuration indicates a plurality of lane configurations, each of the plurality of lane configurations corresponding to a lane of the link.
In a thirteenth aspect, in combination with one or more of the first aspect through the twelfth aspect, at least one lane configuration of the first link configuration is bidirectional and at least one lane configuration of the second link configuration is bidirectional.
In a fourteenth aspect, in combination with one or more of the first aspect through the thirteenth aspect, the link configuration change request includes a first value indicating a first number of lanes of the link configured as a bidirectional lane, a second value indicating a second number of lanes of the link configured as a unidirectional transmit lane, and a third value indicating a third number of lanes of the link configured as a unidirectional receive lane.
In a fifteenth aspect, in combination with one or more of the first aspect through the fourteenth aspect, the receiving is performed by a bus interface comprising a register configured to store a value corresponding to a link configuration for the link, the bus interface comprises a peripheral component interconnect express (PCIe) interface, and the component comprises a PCIe endpoint or a PCIe root complex.
In the description of embodiments herein, numerous specific details are set forth, such as examples of specific components, circuits, and processes to provide a thorough understanding of the present disclosure. The term “coupled” as used herein means connected directly to or connected through one or more intervening components or circuits. Also, in the following description and for purposes of explanation, specific nomenclature is set forth to provide a thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that these specific details may not be required to practice the teachings disclosed herein. In other instances, well known circuits and devices are shown in block diagram form to avoid obscuring teachings of the present disclosure.
Some portions of the detailed descriptions which follow are presented in terms of procedures, logic blocks, processing, and other symbolic representations of operations on data bits within a computer memory. In the present disclosure, a procedure, logic block, process, or the like, is conceived to be a self-consistent sequence of steps or instructions leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Usually, although not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated in a computer system.
In the figures, a single block may be described as performing a function or functions. The function or functions performed by that block may be performed in a single component or across multiple components, and/or may be performed using hardware, software, or a combination of hardware and software. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps are described below generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure. Also, the example devices may include components other than those shown, including well-known components such as a processor, memory, and the like.
Unless specifically stated otherwise as apparent from the following discussions, it is appreciated that throughout the present application, discussions utilizing the terms such as “accessing,” “receiving,” “sending,” “using,” “selecting,” “determining,” “normalizing,” “multiplying,” “averaging,” “monitoring,” “comparing,” “applying,” “updating,” “measuring,” “deriving,” “settling,” “generating,” or the like, refer to the actions and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's registers, memories, or other such information storage, transmission, or display devices.
The terms “device” and “apparatus” are not limited to one or a specific number of physical objects (such as one smartphone, one camera controller, one processing system, and so on). As used herein, a device may be any electronic device with one or more parts that may implement at least some portions of the disclosure. While the description and examples herein use the term “device” to describe various aspects of the disclosure, the term “device” is not limited to a specific configuration, type, or number of objects. As used herein, an apparatus may include a device or a portion of the device for performing the described operations.
Certain components in a device or apparatus described as “means for accessing,” “means for receiving,” “means for sending,” “means for using,” “means for selecting,” “means for determining,” “means for normalizing,” “means for multiplying,” or other similarly-named terms referring to one or more operations on data, such as image data, may refer to processing circuitry (e.g., application specific integrated circuits (ASICs), digital signal processors (DSP), graphics processing unit (GPU), central processing unit (CPU)) configured to perform the recited function through hardware, software, or a combination of hardware configured by software.
Those of skill in the art would understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.
Components, the functional blocks, and the modules described herein with respect to
Those of skill in the art that one or more blocks (or operations) described with reference to
Those of skill in the art would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure. Skilled artisans will also readily recognize that the order or combination of components, methods, or interactions that are described herein are merely examples and that the components, methods, or interactions of the various aspects of the present disclosure may be combined or performed in ways other than those illustrated and described herein.
The various illustrative logics, logical blocks, modules, circuits and algorithm processes described in connection with the implementations disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. The interchangeability of hardware and software has been described generally, in terms of functionality, and illustrated in the various illustrative components, blocks, modules, circuits, and processes described above. Whether such functionality is implemented in hardware or software depends upon the particular application and design constraints imposed on the overall system.
The hardware and data processing apparatus used to implement the various illustrative logics, logical blocks, modules and circuits described in connection with the aspects disclosed herein may be implemented or performed with a general purpose single- or multi-chip processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, or any conventional processor, controller, microcontroller, or state machine. In some implementations, a processor may be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. In some implementations, particular processes and methods may be performed by circuitry that is specific to a given function.
In one or more aspects, the functions described may be implemented in hardware, digital electronic circuitry, computer software, firmware, including the structures disclosed in this specification and their structural equivalents thereof, or in any combination thereof. Implementations of the subject matter described in this specification also may be implemented as one or more computer programs, which is one or more modules of computer program instructions, encoded on a computer storage media for execution by, or to control the operation of, data processing apparatus.
If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. The processes of a method or algorithm disclosed herein may be implemented in a processor-executable software module which may reside on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that may be enabled to transfer a computer program from one place to another. A storage media may be any available media that may be accessed by a computer. By way of example, and not limitation, such computer-readable media may include random-access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that may be used to store desired program code in the form of instructions or data structures and that may be accessed by a computer. Also, any connection may be properly termed a computer-readable medium. Disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media. Additionally, the operations of a method or algorithm may reside as one or any combination or set of codes and instructions on a machine readable medium and computer-readable medium, which may be incorporated into a computer program product.
Various modifications to the implementations described in this disclosure may be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to some other implementations without departing from the spirit or scope of this disclosure. Thus, the claims are not intended to be limited to the implementations shown herein but are to be accorded the widest scope consistent with this disclosure, the principles and the novel features disclosed herein.
Additionally, a person having ordinary skill in the art will readily appreciate, opposing terms such as “upper” and “lower,” or “front” and back,” or “top” and “bottom,” or “forward” and “backward” are sometimes used for ease of describing the figures, and indicate relative positions corresponding to the orientation of the figure on a properly oriented page, and may not reflect the proper orientation of any device as implemented.
As used herein, the term “coupled to” in the various tenses of the verb “couple” may mean that element A is directly connected to element B or that other elements may be connected between elements A and B (i.e., that element A is indirectly connected with element B), to operate certain intended functions. In the case of electrical components, the term “coupled to” may also be used herein to mean that a wire, trace, or other electrically conductive material is used to electrically connect elements A and B (and any components electrically connected therebetween). In some examples, the term “coupled to” mean a transfer of electrical energy between elements A and B, to operate certain intended functions.
In some examples, the term “electrically connected” mean having an electric current or configurable to having an electric current flowing between the elements A and B. For example, the elements A and B may be connected via resistors, transistors, or an inductor, in addition to a wire, trace, or other electrically conductive material and components. Furthermore, for radio frequency functions, the elements A and B may be “electrically connected” via a capacitor.
The terms “first,” “second,” “third,” etc. are employed for ease of reference and may not carry substantive meanings. Likewise, names for components/modules may be adopted for ease of reference and might not limit the components/modules. \
Certain features that are described in this specification in the context of separate implementations also may be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation also may be implemented in multiple implementations separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination may in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.
Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown, or in sequential order, or that all illustrated operations be performed to achieve desirable results. Further, the drawings may schematically depict one or more example processes in the form of a flow diagram. However, other operations that are not depicted may be incorporated in the example processes that are schematically illustrated. For example, one or more additional operations may be performed before, after, simultaneously, or between any of the illustrated operations. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system components in the implementations described above should not be understood as requiring such separation in all implementations, and it should be understood that the described program components and systems may generally be integrated together in a single software product or packaged into multiple software products. Additionally, some other implementations are within the scope of the following claims. In some cases, the actions recited in the claims may be performed in a different order and still achieve desirable results.
As used herein, including in the claims, the term “or,” when used in a list of two or more items, means that any one of the listed items may be employed by itself, or any combination of two or more of the listed items may be employed. For example, if a composition is described as containing components A, B, or C, the composition may contain A alone; B alone; C alone; A and B in combination; A and C in combination; B and C in combination; or A, B, and C in combination. Also, as used herein, including in the claims, “or” as used in a list of items prefaced by “at least one of” indicates a disjunctive list such that, for example, a list of “at least one of A, B, or C” means A or B or C or AB or AC or BC or ABC (that is A and B and C) or any of these in any combination thereof.
The term “substantially” is defined as largely, but not necessarily wholly, what is specified (and includes what is specified; for example, substantially 90 degrees includes 90 degrees and substantially parallel includes parallel), as understood by a person of ordinary skill in the art. In any disclosed implementations, the term “substantially” may be substituted with “within [a percentage] of” what is specified, where the percentage includes 0.1, 1, 5, or 10 percent.
The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
