1. Field of the Invention
The invention relates to data receivers such as those for 1000BASE-T (“Gigabit”) communication.
2. Prior Art Discussion
Such communication involves compensation for various sources of error. For example, the response of the cable introduces time dispersion, resulting in intersymbol interference (ISI).
The primary existing approaches to equalizing the 1000BASE-T channel are as follows.
The main problems with analog equalizers are:
The FIR digital equalizer has difficulty handling the cable's low frequency effects. These effects tend to last for a long time and are difficult to cancel by a filter with finite impulse response of reasonable length. The number of coefficients of the equalizer would have to significantly grow if these effects were to be cancelled with an FIR filter.
It is proposed in Samulei et al (IEEE Journal on selected Areas in Communications, volume 9, no. 6 August 1991 pages 839-847) and the document referenced therein Chen, W. Y. (Proc. 1990 IEEE Int. Symp. Circ. Syst, May 1990 pages 1947-1950), to use an infinite impulse response (IIR) filter in conjunction with an FIR filter to reduce the complexity of the FIR filter. The IIR filter is adapted to the cable characteristics using an LMS-type algorithm. This approach appears to require considerable area and power in ASIC implementations.
Also, it is more difficult to meet the performance requirements at longer cable lengths, however the system bit error rate (BER) needs to be met at all cable lengths.
The invention is thus directed towards providing for improved compensation to address these problems.
According to the invention there is provided an equalization system for a data receiver, the system comprising a digital equalizer, characterized in that,
In one embodiment the sets of taps are in an infinite impulse response (IIR) structure.
In one embodiment a set of taps is optimal for shorter cable lengths.
In another embodiment the system further comprises an analog filter and said set of taps comprises means for cancelling adaptation of the analog filter.
In a further embodiment a set of taps is optimal for longer cable lengths and comprises means for matching lower frequencies.
In one embodiment the system further comprises a feed forward equalizer between the analog filter and the digital filter.
In one embodiment the decision device comprises means for selecting a set of taps by comparing performance of the system with each of the sets of taps individually selected.
In a further embodiment the decision device comprises means for selecting a set of taps at every start-up.
In one embodiment the decision device comprises a measurement circuit for measuring the power of the noise output associated with a set of taps.
In one embodiment the measurement circuit comprises a squarer and an accumulator.
The invention will be more clearly understood from the following description of some embodiments thereof, given by way of example only with reference to the accompanying drawings in which:
Referring to
In more detail, the analog filter 2 is not adaptive. It has a fixed mode, suitable for much of the adaptation required for the longest permissible cable length. However, it is ineffective for short lengths. The FFE 3 is conventional.
The digital filter 4 has two sets of taps in a simple IIR structure. One set is optimal for shorter cable lengths as it cancels the adaptation of the analog filter and also caters for noise arising from SRL and additive noise. The second set is optimal for long cable lengths, and so it assists operation of the analog filter 2. An aspect of the second set of taps is that it matches lower frequencies, something not done effectively by the analog filter 1 or the FFE 3.
The decision block 5 selects the set of taps appropriate for any particular channel. It does this by, at start-up, comparing the performance of the system with the filter 4 in both settings and selecting the set giving the best signal to noise ratio. A slicer and measurement circuitry within the block 5 perform the measurements and comparisons.
The measurement circuitry comprises a squarer and an accumulator for subtracting the symbols from the combined incoming symbols and noise.
In a first setting of the digital filter 4 the block 5 uses the digital filter output and its own internal squarer and accumulator to measure the power of the noise at the digital filter output. After an appropriate time this power is stored and this measurement is repeated for the other set of taps. The set of taps providing the lower noise value is selected.
Referring to
The invention is not limited to the embodiments described but may be varied in construction and detail.
This is a complete application claiming benefit of provisional 60/309,165 filed Aug. 2, 2001.
Number | Name | Date | Kind |
---|---|---|---|
5388063 | Takatori et al. | Feb 1995 | A |
5481564 | Kakuishi et al. | Jan 1996 | A |
5561687 | Turner | Oct 1996 | A |
5617450 | Kakuishi et al. | Apr 1997 | A |
5818378 | Cheng et al. | Oct 1998 | A |
6438164 | Tan et al. | Aug 2002 | B2 |
6501329 | Petrofsky et al. | Dec 2002 | B1 |
6980592 | Rambaud et al. | Dec 2005 | B1 |
Number | Date | Country |
---|---|---|
0428129 | May 1991 | EP |
0467412 | Jan 1992 | EP |
1107527 | Jun 2001 | EP |
Number | Date | Country | |
---|---|---|---|
20030026333 A1 | Feb 2003 | US |
Number | Date | Country | |
---|---|---|---|
60309165 | Aug 2001 | US |