Claims
- 1. A charge compensation control circuit, comprising:a charge compensation circuit operative to supply an amount of charge to a supply voltage based on a charge compensation value; and a test charge compensation circuit operably coupled to the charge compensation circuit, wherein the test charge compensation circuit is operative to determine the charge compensation value by modeling charge consumption characteristics of a circuit using the supply voltage; wherein the test charge compensation circuit is configured to iterate through a plurality of intermediate charge compensation values before selecting the charge compensation value provided to the charge compensation circuit.
- 2. The charge compensation control circuit of claim 1 further comprising a plurality of charge compensation circuits, each charge compensation circuit operative to supply a respective amount of charge to a respective supply voltage based on the charge compensation value.
- 3. A method for controlling a charge compensation circuit, comprising:determining a charge compensation value using a charge compensation bit generator that includes a test charge compensation circuit, wherein the test charge compensation circuit models behavior of the charge compensation circuit; and providing the charge compensation value to the charge compensation circuit such that an amount of charge sourced by the charge compensation circuit is controlled; wherein the test charge compensation circuit is configured to iterate through a plurality of intermediate charge compensation values before selecting the charge compensation value provided to the charge compensation circuit.
- 4. The charge compensation control circuit of claim 1, wherein the charge compensation circuit is configured to maintain the supply voltage at a substantially level voltage between a power supply level and a ground level while current is drawn from the supply voltage by the circuit using the supply voltage as a voltage source.
- 5. The method of claim 3, including sourcing said amount of charge to a voltage node so as to maintain the voltage node at a substantially level voltage between a power supply level and a ground lever while current is drawn from the voltage node by a driver circuit.
- 6. The method of claim 3, including sourcing said amount of charge from the charge compensation circuit to a supply voltage node used by a circuit as a voltage source, so as to maintain the supply voltage node at a substantially level voltage between a power supply level and a ground level;wherein the step of determining a charge compensation value includes modeling charge consumption characteristics of the circuit using the supply voltage node.
CROSS REFERENCE TO RELATED APPLICATIONS
This application is a continuation of prior U.S. patent application Ser. No. 09/698,997, filed Oct. 26, 2000, which is a continuation of prior U.S. patent application Ser. No. 09/222,590, filed Dec. 28, 1998, now U.S. Pat. No. 6,163,178, issued Dec. 19, 2000, both of which are incorporated herein in their entirety.
US Referenced Citations (12)
Foreign Referenced Citations (3)
Number |
Date |
Country |
0 463 316 |
Jan 1992 |
EP |
0 482 392 |
Apr 1992 |
EP |
58-54412 |
Mar 1983 |
JP |
Non-Patent Literature Citations (7)
Entry |
Allen, Arnold O.; “Probability, Statistics, and Queueing Theory with Computer Science Applications”; 2nd Edition, CH 7; pp. 450, 458-459. |
Chappell, Terry I. et al.; “A 2ns Cycle, 4ns Access 512 kb CMOS ECL SRAM”; IEEE International Solid State Circuits Conference 1991; pp. 50-51. |
Donnelly, Kevin S et al.; “A 660 MB§ Interface Megacell Circuit in 0.3 μm-0.7 μm CMOS ASIC”; IEEE Journal of Solid State Circuits; vol. 31, No. 12; Dec. 1996, pp. 1995-2003. |
Pilo, Harold et al.; “A 300 MHz 3.3V 1 Mb SRAM Fabricated in a 0.5 μm CMOS Process”; IEEE International Solid State Circuits Conference 1996; pp. 148-149. |
Schumacher, Hans-Jürgen et al.; “CMOS Subnanosecond True-ECL Output Buffer”; IEEE Journal of Solid-State Circuits; vol. 25, No. 1; Feb. 1990 pp. 150-154. |
Sidiropoulos, Stefanos et al.; “A 700-Mb/s/pin CMOS Signaling Interface Using Current Integrating Receivers”; IEEE Journal of Solid-State Circuits; vol. 32, No. 5, May 1997; pp. 681-690. |
Yang, Tsen-Shau et al.; “A 4-ns 4Kx1-bit Two-Port BiCMOS SRAM”; IEEE Journal of D-State Circuits; vol. 23, No. 5; Oct. 1988; pp. 1030-1040. |
Continuations (2)
|
Number |
Date |
Country |
Parent |
09/698997 |
Oct 2000 |
US |
Child |
10/014650 |
|
US |
Parent |
09/222590 |
Dec 1998 |
US |
Child |
09/698997 |
|
US |