CHARGE PUMP APPARATUS

Abstract

The invention provides a charge pump apparatus including a clock signal generator, a clock freezing circuit, a charge pump circuit, and a feedback circuit. The clock signal generator generates a clock signal. The clock freezing circuit directly receives the clock signal and an enable signal. The clock freezing circuit decides whether to pass or latch a voltage level of the clock signal according to the enable signal to generate a controlled clock signal. The charge pump circuit directly receives the controlled clock signal and operates a charge pump operation on an input voltage to generate a pumping voltage.

Description

BACKGROUND

1. Field of the Invention

The invention relates to a charge pump apparatus. Particularly, the invention relates to a charge pump apparatus capable of reducing voltage ripple on the pumping voltage generated by the charge pump apparatus.

2. Description of Related Art

A charge pump circuit is used to provide a pumping voltage with higher voltage level based on a reference voltage. The voltage level of the pumping voltage may be several times of a voltage level of the reference voltage. The charge pump circuit may be applied in a plurality of electronic apparatus, such as non-volatility memory, display driver and so on.

In conventional art, if the clock signal is not stopped when the voltage level of the pumping voltage reaches a target value, a ripple voltage may be carried on the pumping voltage. For reducing the harmful effect of the ripple voltage, a decoupling capacitor with larger size is needed. That is, chip size of the charge pump circuit is increased.

In some conventional art, when the voltage level of the pumping voltage reaches the target value, the clock signal can be stopped through a clock source for generating the clock signal. However, there is a time delay between a timing point of the pumping voltage reaching the target value and a timing of the clock signal being stopped. That is, some un-necessary pulses on the clock signal may be fed to the charge pump circuit, and the ripple voltages are generated accordingly.

SUMMARY OF THE INVENTION

The invention is directed to a charge pump apparatus, which can effectively reduce a ripple voltage on the pumping voltage generated by the charge pump apparatus.

The invention provides a charge pump apparatus including a clock signal generator, a clock freezing circuit, a charge pump circuit, and a feedback circuit. The clock signal generator generates a clock signal. The clock freezing circuit is coupled to the clock signal generator, and directly receives the clock signal and an enable signal. The clock freezing circuit decides whether to hold a voltage level of the clock signal on a constant level or not according to the enable signal for generating a controlled clock signal. The charge pump circuit is coupled to the clock freezing circuit. The charge pump circuit directly receives the controlled clock signal and operates a charge pump operation on an input voltage to generate a pumping voltage.

According to an embodiment of present application, wherein the feedback circuit generates the enable signal with a first logic level when the pumping voltage is lower than the preset target voltage, and the feedback circuit generates the enable signal with a second logic level when the pumping voltage is higher than the preset target voltage. Wherein, the first logic level and the second logic level are complementary.

According to an embodiment of present application, wherein the clock freezing circuit passes the voltage level of the clock signal to generate the controlled clock signal when the enable signal is at the first logic level.

According to an embodiment of present application, wherein the clock freezing circuit generates the controlled clock signal by latching the clock signal at a time point for the enable signal transited from the first logic level to the second logic level.

According to an embodiment of present application, wherein the charge pump circuit includes at least one capacitor, and the controlled clock signal is directly connected to the at least one capacitor.

According to the above descriptions, the present application provides a clock freezing circuit for stopping a logic level transition of the clock signal. That is, there is no extra pulses on the clock signal be transported to the charge pump circuit when the pumping voltage equal to a target. Accordingly, the voltage ripple on the pumping voltage from the charge pump apparatus can be reduced, and the stress issue of the charge pump apparatus can be improved.

In order to make the aforementioned and other features and advantages of the invention comprehensible, several exemplary embodiments accompanied with figures are described in detail below.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

FIG. 1 illustrates a charge pump apparatus according to an embodiment of present application.

FIG. 2 illustrates a block diagram of the clock freezing circuit according to the embodiment of present application.

FIG. 3A illustrates a circuit diagram of the latch circuit according the embodiment of present application.

FIG. 3B illustrates a circuit diagram of the tri-state inverter TINV in FIG. 3A.

FIG. 4 illustrates a block diagram of the feedback circuit according to the embodiment of present application.

FIG. 5 illustrates a block diagram of the charge pump circuit according to the embodiment of present application.

FIG. 6 illustrates a block diagram of the clock generator according to the embodiment of present application.

DETAILED DESCRIPTION OF DISCLOSED EMBODIMENTS

Referring to FIG. 1, FIG. 1 illustrates a charge pump apparatus according to an embodiment of present application. The charge pump apparatus 100 includes a clock signal generator 110, a clock freezing circuit 120, a charge pump circuit 130, and a feedback circuit 140. The clock signal generator 110 is used to generate a clock signal CLK, and the clock signal CLK is provided to the clock freezing circuit 120. The clock freezing circuit 120 receives the clock signal CLK and an enable signal EN, and the clock freezing circuit 120 may decide whether to freeze the clock signal CLK to generate a controlled clock signal CCLK or not according to the enable signal.

The enable signal EN is generated by the feedback circuit 140. The feedback circuit 140 is coupled between the charge pump circuit 130, the clock freezing circuit 120, and the clock signal generator 110. The feedback circuit 140 compares a regulated pumping voltage VOUT which is generated by the charge pump circuit 130 with a preset target voltage to generate the enable signal EN. Wherein, the pumping voltage VOUT is generated by the charge pump circuit 130 through a charge pump operation based on the controlled clock signal CCLK. That is, when a voltage level of the pumping voltage VOUT is lower than the preset target voltage, the feedback circuit 140 may generate the enable signal EN with a first logic level (such as logic level “1”). On the contrary, when the voltage level of the pumping voltage VOUT is not lower than the preset target voltage, the feedback circuit 140 may generate the enable signal EN with a second logic level (such as logic level “0”). The first and second logic levels are complementary. It can be easily seen, when the logic level of the enable signal EN is the second logic level, the charge pump operation of the charge pump circuit 130 has been competed and no more pulses on the controlled clock signal CCLK is needed.

When the clock freezing circuit 120 receives the enable signal EN with the second logic level, the clock freezing circuit 120 may freeze the clock signal CLK by holding a voltage level of the clock signal CLK on a constant level, and generates the controlled clock signal CCLK. In detail, the clock freezing circuit 120 may immediately hold the voltage level of the clock signal CLK on a constant level when the logic level of the enable signal EN transited from the first logic level to the second logic level. That is, when at a timing point T1 which the logic level of the enable signal EN transited from the first logic level to the second logic level, the clock freezing circuit 120 sets the voltage level of the clock signal CLK held on the voltage level at the timing point T1 to generate the controlled clock signal CCLK. Accordingly, no more pulses on the controlled clock signal CCLK transported to the charge pump circuit 130 when the pumping voltage VOUT is higher than the preset target voltage.

On the other hand, clock freezing circuit 120 may hold the voltage level of the clock signal CLK by latching the clock signal CLK according to the enable signal EN.

It should be noted here, when the logic level of the enable signal EN is at the first logic level, the clock freezing circuit 120 may pass the clock signal CLK to be the controlled clock signal CCLK, and the charge pump circuit 130 may operate the charge pump operation based on the clock signal CLK normally.

Besides, the controlled clock signal CCLK is directly connected to the charge pump circuit 130. When the enable signal EN transited to the second logic level, the controlled clock signal CCLK may be held on a constant voltage level immediately, and no more extra pulses transported to the charge pump circuit 130.

Referring to FIG. 2, FIG. 2 illustrates a block diagram of the clock freezing circuit according to the embodiment of present application. The clock freezing circuit 120 includes a latch circuit 121. An input end of the latch circuit 121 receives the clock signal CLK, and an output end the latch circuit 121 outputs the controlled clock signal CCLK. Moreover, the latch circuit 121 decides whether to hold the voltage level of the clock signal CLK or not to generate the controlled clock signal CCLK according to the enable signal EN.

In some embodiment, the clock signal CLK may include a plurality of sub-clock signals, such as a first, second, third, and fourth sub-clock signals, and the phases of the first, second, third, and fourth sub-clock signals are different. Correspondingly, the latch circuit 121 may includes four sub-latches respect to the first, second, third, and fourth sub-clock signals for latching the four clock signal to generate four sub-controlled clock signal, respectively.

Referring to FIG. 3A, FIG. 3A illustrates a circuit diagram of the latch circuit according the embodiment of present application. The latch circuit 310 includes inverters INV1 and INV2, switch SW1, and tri-state inverter TINV. The inverter INV1 receives the clock signal CLK and generates an inverted clock signal. The switch SW1 receives the inverted clock signal, and decides whether to transport the inverted clock signal to the inverter INV2 or not according to the enable signal. In FIG. 3A, the switch SW1 is a transmission gate TG1. The transmission gate TG1 is controlled by the enable signal EN and an inverted enable signal ENB, and when the enable signal EN is at logic level 1, the transmission gate TG1 is turned on for transporting the inverted clock signal to the inverter INV2. On the contrary, when the enable signal EN is at logic level 0, the transmission gate TG1 is cut off, and the inverted clock signal is not transported to the inverter INV2.

An input end of the inverter INV2 is coupled to an output end of the tri-state inverter TINV, and an output end of the inverter INV2 is coupled to an input end of the tri-state inverter TINV. Further, the tri-state inverter TINV is controlled by the enable signal EN. When the switch SW1 is turned off at timing point T1 by the enable signal EN, the tri-state inverter TINV is enabled, and the inverter INV2 and the tri-state inverter form a latch loop for latching the voltage level at the timing point T1 of the clock signal CLK to be the controlled clock signal CCLK. On the contrary, when the switch SW1 is turned on by the enable signal EN, the tri-state inverter TINV is disabled, and the clock signal CLK passes through the inverters INV1 and INV2 to be the controlled clock signal CCLK.

Here, the latch circuit can be formed by other logic gates (such as NOR gates or NAND gates). The latch circuit in FIG. 3A is only an example, and not use to limit the scope of present application.

Please refer to FIG. 3B, FIG. 3B illustrates a circuit diagram of the tri-state inverter TINV in FIG. 3A. The tri-state inverter TINV includes transistors M1-M4. The transitory M1 and M2 are P-type transistors, and the transistors M1-M2 are coupled in series between a voltage source VDD2 and an output end OUT of the tri-state inverter TINV. The transistors M3 and M4 are N-type transistors, and the transistors M3-M4 are coupled in series between the output end OUT and a reference ground GND. A gate end of the transistor M1 receives the enable signal EN, a gate of the transistor M4 receives the inverted enable signal ENB, and gates of the transistors M2-M3 are coupled to an input end IN of the tri-state inverter TINV. When the transistors M1 and M4 are turned off according to the enable signal EN and the inverted enable signal ENB respectively, the output end OUT of the tri-state inverter TINV is in high impedance. On the contrary, when the transistors M1 and M4 are turned on according to the enable signal EN and the inverted enable signal ENB respectively, the logic levels of the output end OUT and the input end IN are complementary.

Referring to FIG. 4, FIG. 4 illustrates a block diagram of the feedback circuit according to the embodiment of present application. The feedback circuit 140 includes a voltage regulator 441 and a comparator 442. The voltage regulator 441 receives the pumping voltage VOUT, and generates a compared voltage COMPV by regulating the pumping voltage VOUT. The comparator 442 receives the compared voltage COMPV and the preset target voltage VREF, and generates the enable signal EN by comparing the compared voltage COMPV and the preset target voltage VREF.

Referring to FIG. 5, FIG. 5 illustrates a block diagram of the charge pump circuit according to the embodiment of present application. The charge pump circuit 130 includes a switching circuit 131 and at least one capacitor C1-CM. The charge pump circuit 130 may receive a voltage source VDD2 and the controlled clock signals CCLK1-CCLKM provided to one or more of the capacitors C1-CM in a specified sequence by the switching circuit 131 to generate a higher pumping voltage VOUT. The voltage source VDD2 may be the operation voltage of the switching circuit 131. It should be noted here, the controlled clock signals CCLK1-CCLKM are provided to the charge pump circuit 130 for the charge pump operation, and the controlled clock signals CCLK1-CCLKM are respectively directly provided to the capacitors C1-CM. That is, when voltage levels of the controlled clock signals CCLK1-CCLKM are held on constant voltage levels, the charge pump operation can be stopped as soon as possible.

Referring to FIG. 6, FIG. 6 illustrates a block diagram of the clock generator according to the embodiment of present application. The clock generator 110 is a ring oscillator, and includes a plurality of inverters IV1-IVN and a nand gate NAND1. A first input end of the nand gate NAND1 receives an enable signal EN. The inverters IV1-IVN are coupled in series between a second input end and an output end of the nand gate NAND1, and the output end of the serial inverters IV1-IVN outputs the clock signal CLK. A frequency of the clock signal CLK may be controlled by a number of the inverters IV1-IVN and gate delays of each of the inverters IV1-IVN and the nand gate NAND1. Of course, the ring oscillator in FIG. 6 is only an example, and any other clock generator know by persons skilled in the art can be applied in the present application.

The enable signal EN can be used to enable or disable the clock generator 110. In this embodiment, when the enable signal EN is logic high, the clock generator 110 can be enabled, and the clock signal CLK can be generated. On the contrary, when the enable signal EN is logic low, the clock generator 110 can be disabled, and a transition of the clock signal CLK is stopped.

In summary, the present application provides a clock freezing circuit to hold the voltage level of the clock signal when the pumping voltage reaches the target value. That is, no more extra pulses be transported to the charge pump circuit, and the ripple voltage on the pumping voltage can be reduced. The stress issue and the area penalty of the charge pump apparatus can be improved.

It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.

Claims

1. A charge pump apparatus, comprising: a clock signal generator, generating a clock signal;a clock freezing circuit, coupled to the clock signal generator, directly receiving the clock signal and an enable signal, and deciding whether to pass a voltage level of the clock signal or not according to the enable signal for generating a controlled clock signal;a charge pump circuit, coupled to the clock freezing circuit, directly receiving the controlled clock signal and operating a charge pump operation on an input voltage to generate a pumping voltage; anda feedback circuit, coupled to the charge pump circuit and the clock freezing circuit, wherein the feedback circuit compares the pumping voltage and a preset target voltage to generate the enable signal.

2. The charge pump apparatus as claimed in claim 1, wherein the feedback circuit generates the enable signal with a first logic level when the pumping voltage is lower than the preset target voltage, and the feedback circuit generates the enable signal with a second logic level when the pumping voltage is higher than the preset target voltage, wherein the first logic level and the second logic level are complementary.

3. The charge pump apparatus as claimed in claim 2, wherein the clock freezing circuit passes the voltage level of the clock signal to generate the controlled clock signal when the enable signal is at the first logic level.

4. The charge pump apparatus as claimed in claim 3, wherein the clock freezing circuit generates the controlled clock signal by latching the clock signal at a time point for the enable signal transited from the first logic level to the second logic level.

5. The charge pump apparatus as claimed in claim 4, wherein the clock freezing circuit comprises: a latch circuit, receives the clock signal and the enable signal, and decide whether to latch the clock signal or not to generated the controlled clock signal according to the enable signal.

6. The charge pump apparatus as claimed in claim 5, wherein the latch circuit comprises: a first inverter, receives the clock signal and generates an inverted clock signal;a switch, has a first end for receiving the inverted clock signal, and controlled by the enable signal to be turned on or turned off;a second inverter, has a input end coupled to a second end of the switch, and an output end of the second inverter generates the controlled clock signal; anda tri-state inverter, has an input end, an output end and a control end, wherein the output end of the tri-state inverter is coupled to the second end of the switch, the input end of the tri-state inverter is coupled to the output end of the second inverter, and the control end of the tri-state inverter receives the enable signal.

7. The charge pump apparatus as claimed in claim 5, wherein the switch is a transmission gate, and a first end of the transmission gate receives the inverted clock signal, a second end of the transmission gate is coupled to the input end of the second inverter, and a first and second control ends of the transmission gate respectively receive the enable signal and a inverted enable signal.

8. The charge pump apparatus as claimed in claim 1, wherein the feedback circuit comprises: a voltage regulator, receives the pumping voltage and generated a compared voltage according to the pumping voltage; anda comparator, coupled to the voltage regulator and the clock freezing circuit, and the comparator compares the compared voltage and the preset target voltage to generate the enable signal.

9. The charge pump apparatus as claimed in claim 1, wherein the clock signal generator further receives the enable signal, and the clock signal generator decides whether to generate the clock signal or not according to the enable signal.

10. The charge pump apparatus as claimed in claim 1, wherein the charge pump circuit comprises at least one capacitor, and the controlled clock signal is directly connected to the at least one capacitor.

11. The charge pump apparatus as claimed in claim 1, wherein the clock signal comprises a first, second, third and fourth sub-clock signals, and the phases of the first, second, third and fourth sub-clock signals are different.

12. The charge pump apparatus as claimed in claim 1, wherein the clock signal generator is a ring oscillator.