Charge pump circuit

Abstract

Charge pump circuit. A charge pump circuit is provided for use in a phase-lock loop circuit. The charge pump circuit comprises a charge pump core circuit that outputs a control voltage. The charge pump circuit also comprises a replica circuit that is coupled to the charge pump core circuit, wherein the replica circuit receives the control voltage and produces one or more bias signals that are coupled to the charge pump core circuit to minimize the difference between charge up and charge down currents generated by the charge pump core circuit.

Description

FIELD OF THE INVENTION

The present invention relates generally to phase-locked loop systems, and more particularly, to phase-locked loop systems that utilize charge pump circuits.

BACKGROUND OF THE INVENTION

Phase-locked loops (PLL) find widespread use in frequency synthesizers, clock recovery circuits, phase modulators, and frequency demodulators. Generally, a PLL consists of a voltage-controlled oscillator (VCO), counter, phase/frequency detector (P/FD), charge pump (CP), and RC integration filter.

The phase-locked loop relies on feedback to drive the frequency difference and phase offset between a reference signal and the output of the counter towards zero. Its operation depends on the circuits that comprise the system; and as such, variations in circuit parameters alter the response of the system, lower the stability of the feedback loop, and introduce distortion. The charge pump and integration filter are circuits that are especially sensitive.

It is therefore desirable to improve the performance of the charge pump so that the PLL can better adapt to parameter changes.

SUMMARY OF THE INVENTION

In one or more embodiments, a PLL system is provided that includes an improved charge pump (CP) circuit that operates linearly and compensates for parameter variations. The improved CP circuit produces fast and symmetric current pulses with reduced ringing and overshoot.

In one embodiment, a charge pump circuit is provided that comprises a replica circuit that provides a current difference between charge (UP) and discharge (DN) currents, and a buffer coupled to the replica circuit to buffer a received control voltage.

In one embodiment, a charge pump circuit is provided for use in a phase-lock loop circuit. The charge pump circuit comprises a charge pump core circuit that outputs a control voltage. The charge pump circuit also comprises a replica circuit that is coupled to the charge pump core circuit, wherein the replica circuit receives the control voltage and produces one or more bias signals that are coupled to the charge pump core circuit to minimize the difference between charge up and charge down currents generated by the charge pump core circuit.

In one embodiment, a method is provided for operating a charge pump circuit in a phase-lock loop circuit. The method comprises generating an output control voltage at a charge pump core circuit, generating one or more bias signals based on the control voltage, and adjusting the operation of the core circuit based on the one or more bias signals so as to minimize a difference between charge up and charge down currents.

In one embodiment, a charge pump circuit is provided for use in a phase-lock loop circuit. The charge pump circuit comprises a charge pump core circuit means for outputting a control voltage. The charge pump circuit also comprises a replica circuit means for receiving the control voltage and producing one or more bias signals that are coupled to the charge pump core circuit means to minimize the difference between charge up and charge down currents generated by the charge pump core circuit means.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing aspects and the attendant advantages of the embodiments described herein will become more readily apparent by reference to the following detailed description when taken in conjunction with the accompanying drawings wherein:

FIG. 1 shows one embodiment of a PLL;

FIG. 2 shows a mathematical model of the PLL of FIG. 1;

FIG. 3 shows a circuit diagram that illustrates the operation of a phase/frequency detector and a CP circuit included in the PLL of FIG. 1;

FIG. 4 shows a timing diagram that illustrates the signal timing of the circuits of FIG. 3;

FIG. 5 shows one embodiment of a CP core circuit;

FIG. 6 shows a signal diagram that illustrates ringing and overshoot in the current pulses connected to an integration filter of the CP of FIG. 5;

FIG. 7 shows one embodiment of a CP core circuit where differential pair switches replace single switch transistors used in the CP core circuit of FIG. 5;

FIG. 8 shows one embodiment of the CP core circuit where a diode-connected transistor is added to the CP core circuit of FIG. 7;

FIG. 9 shows a detail diagram of one embodiment of a CP circuit that operates to minimize the difference in the charge (I_UP) and discharge (I_DN) currents;

FIG. 10 shows a detailed view of one embodiment of a buffer circuit that operates to minimize the difference in the charge (I_UP) and discharge (I_DN) currents in a CP circuit;

FIG. 11 shows a detailed view of error amplifier circuits for use in a CP circuit;

FIG. 12 shows a detailed diagram of one embodiment of a replica circuit for use inaCP;

FIG. 13 shows one embodiment of a switch driver for use in a CP circuit.

FIG. 14 shows another embodiment of a switch driver where a switch amplifier is realized as a bipolar differential pair; and

FIG. 15 shows one embodiment of a servo circuit for use with a CP circuit.

DETAILED DESCRIPTION

In one or more embodiments, a PLL system is provided that includes an improved charge pump (CP) circuit that operates linearly and compensates for parameter variations.

FIG. 1 shows one embodiment of a PLL that comprises a charge pump (CP), RC integration filter, voltage-controlled oscillator (VCO), N-counter, and a phase/frequency detector (P/FD). The PLL relies on feedback to drive the frequency difference and phase offset between a reference (Ref) signal and the output of the N-counter towards zero. The operation of the PLL may also depend on the circuits that comprise the system; and as such, variations in circuit parameters alter the response of the system, lower the stability of the feedback loop, and introduce distortion. The CP and RC integration filter are circuits that may be especially sensitive.

FIG. 2 shows a mathematical model of the PLL of FIG. 1. The VCO produces an output signal (V_out) at a frequency set by control voltage (v_ctrl) that is expressed as;V_out(t)=A_c cos (ω_freet+K_VCO∫v_ctrl(t)dt)where ω_free is the free-running frequency of the oscillator and K_vco is its gain function. The gain function K_vco describes the relationship between the excess phase of the carrier Φ_out(s) and the control voltage v_ctrl, i.e.

$\frac{{\Phi }_{\mathrm{out}}\left(s\right)}{v_{\mathrm{ctrl}}\left(s\right)}=\frac{K_{\mathrm{vco}}}{s}$ The Div-by-N counter simply divides the output phase Φ_out(s) by N. When the PLL is locked, the phase/frequency detector and CP combination generate an output signal (i_CP(t)) that is proportional to the phase difference (error Δθ) between the two periodic signals input to the phase detector. The CP output signal can be expressed as;

$i_{\mathrm{CP}}\left(s\right)=K_{\mathrm{PD}}\frac{\mathrm{\Delta \theta }\left(s\right)}{2\pi }$ A simple RC integration filter, consisting of resistor R and capacitor C, transforms the CP output signal to the control voltage V_ctrl, which can be expressed as;

$v_{\mathrm{ctrl}}\left(s\right)=i_{\mathrm{out}}\left(s\right)\left(R+\frac{1}{\mathrm{sC}}\right)$ Combining the above transfer functions yields the composite transfer function;

$T\left(s\right)=\frac{K_{\mathrm{PD}}{K}_{\mathrm{VCO}}\left(\mathrm{Rs}+\frac{1}{C}\right)}{s^2+K_{\mathrm{PD}}{K}_{\mathrm{VCO}}\frac{1}{N}\left(\mathrm{Rs}+\frac{1}{C}\right)}$ where a zero (at 1/RC) has been added to the second order system to stabilize it.

The phase/frequency detector and CP define the parameter K_PD. These circuits compare the output of the feedback N-counter to the reference signal Φ_in and generate the output signal I_cp(t) representing their phase difference.

FIG. 3 shows a circuit diagram that illustrates the operation of the phase/frequency detector and CP circuits included in the PLL of FIG. 1. FIG. 4 shows a timing diagram that illustrates the signal timing of the circuits of FIG. 3.

Referring again to FIG. 3, the phase/frequency detector (P/FD) tracks the N-counter's output signal (expressed as DIV) and the reference signal (expressed as REF), thereby triggering flip-flops (FF1 and FF2) on the active falling edges of these signals. An AND gate 302 resets the flip-flops, forcing both UP and DN pulses low, shortly after the triggering of the second flip-flop (FF2) occurs. As such, the UP and DN pulses overlap slightly and stop at the same time, as illustrated in FIG. 4.

The P/FD drives the CP, which comprises a pair of switches S₁ and S₂ that connect current sources I_UP and I_DN to the integration filter (R₁, C₁). An UP pulse closes switch S₁ and directs charge to the integration filter, raising the control voltage v_ctrl. Similarly, a DN pulse closes switch S₂ and removes charge from the integration filter, lowering the control voltage v_ctrl. The control voltage v_ctrl, in turn, sets the frequency of the voltage-controlled oscillator (VCO in FIG. 2).

Ideally, the CP circuit is both symmetrical and insensitive to the level of the control voltage v_ctrl. The net charge (ΔQ) transferred or removed from the integration filter is proportional to the time difference (Δt) between the active edges of the N-counter's output signal (DIV) and the reference signal (REF), and can be expressed as;ΔQ=K_PDIΔtwhere K_PD is the associated scaling factor and I is the current level—either I_UP or I_DN. It may also be important that these currents be equal and therefore cancel during the overlap of the UP and DN pulses, otherwise, an error occurs.

In one embodiment, the current sources I_UP and I_DN and the switches S₁ and S₂ are implemented using CMOS transistors. In one embodiment, the current source transistors operate in the saturation region with V_DS≧V_GS−V_T. In this region, the applied gate-source voltage V_GS sets the drain current I_D as expressed by;

$I_D=\frac{\mu C_{\mathrm{OX}}}{2}\frac{W}{L}{\left(V_{\mathrm{GS}}-V_T\right)}^2\left[1+\lambda \left(V_{\mathrm{DS}}-V_{\mathrm{GS}}-V_T\right)\right]$ where the μ is the carrier mobility, C_OX is the oxide capacitance, W and L are the device dimensions, V_T is the threshold voltage, and λ is the channel-length modulation coefficient. The voltage difference V_GS-V_T is oftentimes noted as the overdrive or effective voltage V_eff. In other applications, V_DS<V_GS−V_T and the transistor operates in the linear region with I_D given by;

$I_D=\mu C_{\mathrm{OX}}\frac{W}{L}\left[\left(V_{\mathrm{GS}}-V_T\right)V_{\mathrm{DS}}-\frac{V_{\mathrm{DS}}^2}{2}\right]\mathrm{for}{V}_{\mathrm{DS}}<V_{\mathrm{GS}}-V_T$ Therefore, to operate the transistor in saturation mode, the minimum drain-source V_DS(sat) is approximated by;

$V_{\mathrm{DS}\left(\mathrm{sat}\right)}\approx \sqrt{\frac{I_D}{\kappa }}$ where κ is the intrinsic gain of the device

$\frac{\mu C_{\mathrm{OX}}}{2}\frac{W}{L}$ and λ is assumed to be small.

Phase-locked loops may target a specific frequency or range of frequencies. The feedback system adapts to different device parameters and circuit responses through changes in the control voltage v_ctrl. Supporting a wide control voltage range provides for lower VCO sensitivity (K_VCO) and improved noise immunity. Unfortunately, this may also mean dramatic changes in the operating bias for the transistors in the CP circuit. As a result, the symmetry, matching, and overall performance of the CP circuit may suffer.

FIG. 5 shows one embodiment of a CP core circuit. Transistors P₃, N₃ act as switches and connect current-source transistors P₁, N₁ to the integration filter. These switches also set the drain-source voltage V_DS applied to the current sources. To transfer an accurate charge to the integration filter (R₁, C₁) and to operate devices P₁, P₃ in the saturation mode, the following two conditions should be met;V_UP+<V₊−+V_DS(sat)P1−V_GSPP2 V_ctrl<V₊−V_DS(sat)P1−V_DS(sat)P2 Increasing voltage V_UP+, collapses the drain-source voltage available to the current-source transistor P₁ and thereby prevents any charge transfer.

Similarly, to remove an accurate charge from the integration filter and to operate devices N₁, N₃ in the saturation mode, the following two conditions should be met;V_DN+>V_GSP2+V_DS(sat)N1 V_ctrl>V_DS(sat)N2+V_DS(sat)N1 Lowering voltage V_DN+ prevents any charge transfer. This means that the drain-source voltage applied to current-source transistors P₁ and N₁ actually switches, charging and discharging any associated device capacitances.

FIG. 6 shows a signal diagram that illustrates how the charging and discharging action, described with reference to the CP core circuit of FIG. 5, may create ringing and overshoot in the current pulses connected to the integration filter. This adversely affects the switching times of the CP circuit, altering the net charge transferred and degrading the performance of the phase-locked loop.

FIG. 7 shows one embodiment of a CP core circuit 700 where differential pair switches replace the single switch transistors that were used in the CP core circuit 500. Transistors P₂ and P₃ form one of the differential pair switches and operate to steer current I_UP either to the integration filter or directly to ground. The following voltage difference (ΔV_UP) is required to ensure complete switching, with all the current I_UP flowing through one of the devices—either transistor P₂ or P₃—so that;

$\Delta V_{\mathrm{UP}}>\sqrt{\frac{2I}{\kappa }}$ Ideally, the differential pair switch maintains a fixed voltage at the drain of transistor P₁. In practice, this voltage may change due to voltage and impedance differences seen at the drain of transistors P₂ and P₃.

FIG. 8 shows one embodiment of a CP core circuit 800. The CP core circuit 800 comprises the CP core circuit 700 where a diode-connected transistor N₄ is added to raise the voltage and impedance seen by the drain of transistor P₂. As a result, the two transistors (P₂ and P₃) closely match, thereby reducing the voltage changes at the drain of transistor P₁, which improves the performance of the CP core circuit 800. Diode-connected transistor P₄ serves a similar purpose.

The current source transistors P₁, N₁ generally have long-channel geometries and high effective gate-source bias voltages (V_eff) to reduce channel-length modulation effects, minimize parasitic capacitance, and improve matching. The effective voltage also corresponds to the minimum drain-source voltage for operation in saturation mode V_DS(sat) since;

$V_{\mathrm{DS}\left(\mathrm{sat}\right)}\approx \sqrt{\frac{I_D}{\kappa }}$ and as a result;V_DS(Sat)N1≦V_ctrl≦V₊−V_DS(sat)P1 The effective voltage is typically several hundred millivolts.

An ideal charge pump circuit generates matching charge (I_UP) and discharge (I_DN) currents so that these currents cancel each other when the UP and DN pulses overlap. In practice, this is challenging because the current sources are implemented using complimentary devices—PMOS and NMOS transistors—and therefore may be dependent upon different parameters.

FIG. 9 shows a detail diagram of one embodiment of a CP circuit that operates to minimize the difference in the charge (I_UP) and discharge (I_DN) currents. The CP circuit comprises the CP core circuit 800 and a replica circuit that duplicates the core circuit 800. The replica circuit shares the same bias conditions including the output voltage (v_ctrl), which is forced through a buffer amplifier (BUFFER) and connects to the replica circuit through resistor R₂. The forcing action may require the buffer amplifier to supply an output current Δi, indicating that I_UP is different from I_DN. For example, if Δi is positive (current flows towards the replica circuit), then I_DN is greater than I_UP. Similarly, if Δi is negative (current flows towards buffer amplifier), then I_UP is greater than I_DN. The difference current Δi may be due to device mismatches or the level of the control voltage, V_ctrl.

Any output current Δi is sensed by resistor R2 and amplified by error amplifiers G_M1 and G_M2. In one embodiment, the amplifiers G_M1 and G_M2 are transconductance amplifiers that convert an input differential voltage to an output current. The output currents from error amplifiers G_M1 and G_M2 adjust bias currents IB2 and IB4, which are mirrored to the replica circuit and the CP core current sources (transistors P₁ and N₁). The two error amplifiers (G_M1 and G_M2) are part of feedback loops that reduce the current Δi, and thus the difference in the replica circuit's as well as the charge pump's currents (I_UP and I_DN).

FIG. 10 shows a detailed view of one embodiment of a buffer circuit that operates to minimize the difference in the charge (I_UP) and discharge (I_DN) currents in a CP circuit. The buffer circuit uses a buffer amplifier 1002 and resistor R₂ to force a replica circuit (constructed using transistors that match P₅, P₆ and N₅, N₆) to the same control voltage v_ctrl that is input to the charge pump circuit at node 1004. In this way, the buffer circuit supplies or sinks the necessary current Δi to establish the control voltage v_ctrl at the replica circuit, where;Δi=I_N6−I_P6≈I_DN−I_UP and develops a proportional voltage across resistor R₂ equal to ΔiR₂.

FIG. 11 shows a detailed view of error amplifier circuits (G_M1, G_M2) for use in a CP circuit. In one case, with regards to the circuit G_M1, the voltage developed across resistor R₂ is zero, and as such, bias current I_B1 splits equally between transistors N₈ and N₉, with I_N8=I_N9, (I_N8 and I_N9 are the currents through transistors N₈ and N₉, respectively. Since transistors P₈ and P₉ mirror current I_N8, current I_P9 essentially equals current I_N9 and the difference current ΔI_UP approaches zero. When the operational amplifier 1102 supplies current to the replica circuit, it indicates that I_UP is less than I_DN. The voltage developed across resistor R₂ drives transistor N₉ to pull more current than transistor N₈. The difference current ΔI_UP is then pulled through transistor P₇, with;I_P7=I_B2+ΔI_UP≈I_UP where current source I_B1 (and thus ΔI_UP) depends on the output of the operational amplifier 1102. That is to say that the current I_B1 exists only when the voltage v_ctrl rises significantly above its lower limit, V_DS(sat)N1. As a result, the difference current ΔI_UP is generally positive.

With regards to G_M2, transistors P₁₀, P₁₁, N₇, and N₁₀, N₁₁, along with current sources I_B3 and I_B4 form a network similar to the one described above that adjusts current-source transistors N₁ and N₆. When the operational amplifier 1102 sinks current from the replica circuit, it indicates that I_UP is larger than I_DN. This creates a voltage across resistor R₂ that steers more current through transistor P₁₁ than transistor P₁₀. As a result, a difference current ΔI_DN is directed towards transistor N₇, making;I_N7=I_B4+ΔI_DN≈I_DN where the bias current I_B3 (and thus ΔI_DN) depends on the output of the operational amplifier 1102. Although it operates similarly to bias current I_B1, in this case, current I_B3 exists only when the voltage v_ctrl falls significantly below its upper limit, V₊−V_DS(sat)P1. This generally makes ΔI_DN positive.

FIG. 12 shows a detailed diagram of one embodiment of a replica circuit for use in a CP. The replica circuit sets the bias voltages V_B1 and V_B2 to properly bias current sources P₆ and N₆ in the replica circuit. Transistor P₁₂ duplicates transistor P₅ along with transistor P₃ (see FIG. 11) of the CP circuit. Transistor P₁₂ is connected as a diode to force its drain voltage to equal its gate voltage (and thus V_DS to equal V_GS). With transistor P₁₃ biased at V_DS(sat), the gate voltage of transistor P₁₂ corresponds to the maximum value allowed for V_B1;V_B1=V₊−V_DS(sat)P13−V_GSP12 where mirror circuitry N₇ and N₁₂ establishes the proper current in transistors P₁₂ and P₁₃. Similarly, transistor P₁₄ establishes the proper current density needed to set the gate-source voltage of transistor N₁₃ and the drain-source voltage of transistor N₁₄ with;V_B2=V_GSN13+V_DS(sat)N14 where the voltage V_B2 serves as a reference to a feedback network shown in FIG. 12.

FIG. 13 shows a detailed embodiment of a driver switch for use with a CP circuit. The output levels associated with the driver switch are set by current sources I_N16 and I_N18 and resistors R₃, R₄, and R₅ such that;V_DN+=V₊−(I_N16+I_N18)R₅ and V_DN−=V₊−(I_N16+I_N18)R₅+I_N18R₅ where R₃=R₄ and

$I_{\mathrm{N18}}{R}_4\approx \Delta V_{\mathrm{UP}}>\sqrt{\frac{2I}{\kappa }}$ which assures full switching of the differential pair N₂, N₃. In addition, the voltage V_DN+ actually sets the drain voltage of the current source transistor N₁ withV_DS(sat)N1=V_DN+−V_GSN13 Note that V_DS(sat) changes with both the drain current and the effective voltage V_eff of the device. A similar switch driver can be used to control transistors P₂ and P₃.

FIG. 14 shows another embodiment of a switch driver where a switch amplifier is realized as a bipolar differential pair (Q1, Q2).

FIG. 15 shows one embodiment of a servo loop circuit for use with a CP circuit. The required drain voltage for transistor N₁ is set by the replica circuit and servo loop circuit. For example, the replica circuit shown in FIG. 15 may be the same replica circuit shown in FIG. 12. The replica circuit establishes a copy of the charging current I_UP and develops a voltage V_B2 equal to;V_B2=V_GSN13+V_DS(sat)N14 which corresponds to the voltage needed for V_DN+ to properly bias transistor N₁. This assumes matching between transistors N₂, N₃ and N₁₃ (to duplicate V_GS(on)) and transistors N₃ and N₁₄ (to duplicate V_DS(sat)). In turn, the servo loop circuit forces the maximum output level from the switch driver (equivalent to V_DN+) to be equal to V_B2, assuming transistors N₁₅ and N₁₆, N₁₇ and N₁₈, resistors R₃ and R₇, plus resistors R₅ and R₆ are matched. As a result,(I_N15+I_N17)R₆+I_N17R₇=(I_N16+I_N18)R₅+I_N18R₄ which establishes the proper output levels from the driver switch.

The above circuit descriptions remain valid even when the currents in the replica and mirror structures are lowered as long as the current density in these structures is uniform. This minimizes the overall current consumption of the CP.

These innovative circuits generate the proper switch levels, minimize the difference between the charge and discharge currents of the CP circuit, and remove many of the design restrictions associated with current source transistors. The result is a circuit with improved performance, stable K_PD, and extended control voltage range. The described circuits also allow the CP circuit to operate at lower supply voltages.

In one or more embodiments, an improved charge pump circuit is provided. Accordingly, while one or more embodiments of the charge pump circuit have been illustrated and described herein, it will be appreciated that various changes can be made to the embodiments without departing from their spirit or essential characteristics. Therefore, the disclosures and descriptions herein are intended to be illustrative, but not limiting, of the scope of the invention, which is set forth in the following claims.

Claims

1. A charge pump circuit for use in a phase-lock loop circuit, the charge pump comprising: a charge pump core circuit that outputs a control voltage, said charge pump core circuit including first switching elements;a replica circuit that is coupled to the charge pump core circuit, wherein the replica circuit receives the control voltage and produces one or more bias signals that are coupled to the charge pump core circuit to minimize the difference between charge up and charge down currents generated by the charge pump core circuit and wherein said replica circuit includes second switching elements configured such that said first switching elements and said second switching elements operate with substantially identical switching characteristics.

2. The charge pump circuit of claim 1, further comprising a buffer circuit that is coupled to receive the control voltage and output the control voltage to the replica circuit.

3. The charge pump circuit of claim 2, further comprising one or more error amplifiers that are coupled to the replica circuit and the buffer circuit, the one or more error amplifiers operate to output the one or more bias signals.

4. The charge pump circuit of claim 1, further comprising: a servo circuit coupled to the replica circuit to receive at least one bias signal; anda driver circuit coupled between the servo circuit and the charge pump core circuit.

5. A method for operating a charge pump circuit in a phase-lock loop circuit, the method comprising: generating an output control voltage at a charge pump core circuit;generating one or more bias signals based on the control voltage, wherein said generating the one or more bias signals includes receiving the control voltage at a buffer circuit operative to output a version of the control voltage and using the version of the control voltage to create, at a replica circuit, the one or more bias signals; andadjusting the operation of the core circuit based on the one or more bias signals so as to minimize a difference between charge up and charge down currents.

6. The method of claim 5, further comprising: generating a current difference based on the version of the control voltage; andgenerating the one or more bias signals based on the current difference.

7. A charge pump circuit for use in a phase-lock loop circuit, the charge pump circuit comprising; a charge pump core circuit means for outputting a control voltage, said charge pump core circuit means including first switching elements; anda replica circuit means for receiving the control voltage and producing one or more bias signals that are coupled to the charge pump core circuit means to minimize the difference between charge up and charge down currents generated by the charge pump core circuit means, said replica circuit means including second switching elements wherein substantially identical switching characteristics characterize operation of said first switching elements and said second switching elements.

8. The charge pump circuit of claim 7, further comprising a buffer circuit means for receiving the control voltage and outputting a version of the control voltage to the replica circuit means.

9. The charge pump circuit of claim 8, further comprising one or more error amplifiers means for receiving the version of the control voltage and outputting the one or more bias signals.

10. The charge pump circuit of claim 7, further comprising: a servo circuit means for receiving the at least one bias signal; anda driver circuit means coupled to the servo circuit means.

11. The charge pump circuit of claim 3 wherein said error amplifiers comprise transconductance amplifiers.

12. The charge pump circuit of claim 9 wherein said error amplifier means comprise transconductance amplifier means.

13. The charge pump circuit of claim 4 wherein said servo circuit is disposed to set the voltage of a driver used to switch a charge pump current.

14. The charge pump circuit of claim 10 wherein said servo circuit means is disposed to set the voltage of a driver means used to switch a charge pump current.

15. A charge pump circuit comprising; a charge pump core circuit outputting a control voltage wherein said charge pump core circuit includes a switching circuit;a buffer circuit coupled to said charge pump core circuit disposed to buffer said control voltage;replica circuit matching said charge pump core circuit for receiving the buffered control voltage and producing one or more bias signals; anda transconductance amplifier for generating a signal to minimize the difference between charge up and charge down currents generated by the charge pump core circuit.

16. The charge pump circuit of claim 15 further comprising a switch driver disposed to control a current switch.

17. The charge pump circuit of claim 16 wherein said switch driver comprises a field effect transistor.

18. The charge pump circuit of claim 16 wherein said switch driver comprises a bipolar junction transistor.