Charge-pump closely coupled to switching converter

Abstract

A circuit, (30, 54) comprising a plurality of switches (S1, S2, S3, S4 and S5) coupled together in a charge pump arrangement (56). A first switch (S1) is driven by a first driver (X1), and a second switch (S2) is driven by a second driver (X2). The first and second switches (S1 and S2) are connected to the input voltage terminal (Vin). The charge pump arrangement (32, 56) is adapted to provide a bootstrap voltage (Vboot) and a drive voltage (Vdrv) for a switch mode power supply. At least the first driver (X1) is powered by a voltage higher than the input voltage (Vin). The higher voltage maybe obtained from a voltage (V3) at a node between an additional switch (S6) and an additional capacitor (C3). Alternatively, the higher voltage may be obtained from the boot voltage (Vboot). Powering the driver (X1) with the higher voltage allows the lateral semiconductor area of the charge pump circuit (32, 56) to be reduced, by using NMOS FETs for at least one switch. The invention is particularly useful for applications such as DSPs and mixed signal or analog circuits.

Description

TECHNICAL FIELD OF THE INVENTION

This invention relates generally to integrated circuits, and more specifically to a charge pump circuit for a switching converter.

BACKGROUND OF THE INVENTION

As logic integrated circuits (ICs) have migrated to lower working voltages in the search for lower power consumption and higher operating frequencies, and as overall system sizes have continued to decrease, IC power supply designs with smaller size and higher efficiency are in demand. Switch mode power supplies, or DC to DC converters, as they are sometimes called, are frequently used in IC circuits such as digital signal processors (DSPs) and mixed signal analog circuits, etc., to efficiently convert an input supply voltage to voltage levels appropriate for internal circuitry as well as external circuitry that the IC is coupled to. For instance, a 2.8 volt supply voltage provided to a BiCMOS IC may need to be increased internally to 5.0 volts to operate internal CMOS circuitry. As appliances and circuit designs continue to decrease in size, the need for smaller and more efficient IC switch mode power converters increases.

SUMMARY OF THE INVENTION

The present invention achieves technical advantages as a charge pump adapted for use in a circuit, the charge pump having switches driven by a voltage higher than an input voltage to the circuit, resulting in the ability to use smaller NMOS FETs as switches, saving semiconductor real estate.

In one embodiment, a circuit is adapted to receive an input voltage, including a means of producing a second voltage higher than the input voltage, the means being integral to the circuit. The circuit includes a plurality of switches coupled together in a charge pump arrangement, including a first switch, where at least the first switch is driven by the second voltage. The first switch may be driven by a first driver, and another of the switches may be a second switch driven by a second driver. The charge pump arrangement may be adapted to provide a bootstrap voltage at a bootstrap voltage terminal and a drive voltage for a switch mode power supply. The higher voltage may be obtained from a voltage at a node between an additional switch and an additional capacitor, or alternatively, the higher voltage may be obtained from the bootstrap voltage.

In another embodiment, a switch mode power converter powered by a charge pump circuit includes a first, second, third, fourth and fifth switch coupled together in a charge pump circuit. The first switch is connected to an input voltage terminal and is driven by a first driver. The second switch is connected to an input voltage terminal and is driven by a second driver. The charge pump arrangement provides a bootstrap voltage at a boot voltage terminal for a third driver and a drive voltage at a drive voltage terminal to a fourth driver. A first capacitor is coupled between the drive voltage terminal and a ground terminal. The first transistor is driven by the first driver and is coupled to the input voltage terminal and a phase node. The second capacitor is connected at one end to the bootstrap voltage terminal and at the other end to the phase node. A second transistor is coupled to the output of the second driver, the phase node and the ground terminal. At least the first driver is powered by a voltage higher than the input voltage at the input voltage terminal. The higher voltage may be obtained from a voltage at a node between an additional switch and an additional capacitor, or alternatively, the higher voltage may be obtained from the bootstrap voltage.

Also disclosed is a method of reducing the lateral semiconductor area of a charge pump circuit. The method includes the step of providing a plurality of switches coupled together in a charge pump arrangement, where the charge pump arrangement is adapted to provide a bootstrap voltage at a boot voltage terminal for a switch mode power supply. The plurality of switches includes at least a first switch and a second switch coupled to an input voltage terminal. The first and second switches are driven by a first driver and a second driver, respectively. The method includes the step of powering at least first driver with a voltage higher than input voltage. The higher voltage may be obtained from a voltage at a node between an additional switch and an additional capacitor, or alternatively, the higher voltage may be obtained from the bootstrap voltage.

Advantages of the present invention include at least one driver of a switch in the charge pump circuit being powered by a voltage higher than the input voltage of the circuit, which allows NMOS FETs to be used for the majority of the switches in the charge pump circuit, resulting in semiconductor real estate savings of one-half to on-third. Another advantage of the present invention is that noise generated by the charge pump is inherently synchronous to the main switching converter, which reduces the likelihood that charge pump noise will interfere with the main converter. A further advantage of the present invention is that the main load of the charge pump is the gate charge required for the main switching converter power FETs, synchronizing the charge pump to the main converter, making the charge pump output approximately track the demand. Also, the second embodiment of the present invention requires no additional components to achieve a bootstrap voltage higher than the input voltage powering the driver of the first switch.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings, which form an integral part of the specification and are to be read in conjunction therewith:

FIG. 1 is a block diagram of a switch mode converter powered from a charge pump;

FIG. 2 illustrates a block diagram of a schematic of a first embodiment of the present invention with additional switch S 6 and capacitor C 3 creating a voltage V 3 that is used to power drivers X 1 and X 2 ;

FIG. 3 is a timing diagram for the circuit shown in FIG. 2 ;

FIG. 4 is a more detailed view of portions of the circuit shown in FIG. 2 , with switch S 6 implemented as a diode;

FIG. 5 illustrates a second embodiment of the present invention with drivers X 1 and X 2 being powered by the bootstrap voltage V boot ; and

FIG. 6 is a timing diagram for the circuit shown in FIG. 5 .

Like numerals and symbols are employed in different figures to designate similar components in various views unless otherwise indicated.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

A problem with prior art switching converters with charge pumps is that the charge pump circuitry requires low resistance FETs in order to obtain a high efficiency. Some of the low resistance FETs must be PMOS, which require a large amount of area of silicon material, for example between 75,000 to 100,000 square microns. A charge pump circuit is needed in art having a high efficiency yet can utilize smaller FETs such as NMOS FETs which require one-half to two-thirds the area that PMOS FETs require, saving semiconductor real estate.

FIG. 1 illustrates a block diagram of a switch mode converter 10 powered from a charge pump 12 , of related case filed herewith, entitled “Circuit and Method of Restoring a Boot Capacitor of a Switch Mode Power Converter” by Grant. The charge pump 12 initially runs from an internal oscillator (not shown), until the capacitors C 1 and C 2 are fully charged. Once both capacitors C 1 and C 2 are charged, the main switch mode converter is started. The switch mode converter alternately turns transistors MN 1 and MN 2 on, causing the phase node 20 to swing between 0 V and V in . The transistors MN 1 and MN 2 are often field effect transistors (FETs). The phase node 20 is tied to one end of capacitor C 2 . The other end of capacitor C 2 provides the power supply for the driver 14 for transistor MN 1 . When transistor MN 1 begins to turn on, the phase node 20 rises, increasing the drive voltage for transistor MN 1 . The charge required to turn on transistor MN 1 is supplied from capacitor C 2 . When the transistor MN 1 turns off and transistor MN 1 turns on, the phase node 20 is brought down to 0V and capacitor C 2 is recharged by switch S 5 .

The charge pump 12 may include a first driver X 1 and a second driver X 2 that are used to drive switches S 1 and S 2 , respectively. The drivers X 1 and X 2 are powered by input voltage Vin. The charge pump 12 is used to increase the supply voltage to a switching converter to allow the converter to drive external transistors, which may be inexpensive FETs with a high voltage threshold V t . To achieve a charge pump 12 with a high efficiency, low resistance PMOS FETs are typically used in the art for the switches S 1 , S 2 , S 4 , and S 5 of the charge pump 12 , which may require up to approximately twice the amount of semiconductor real estate that NMOS FETs require. Switch S 3 is typically an NMOS FET.

FIG. 2 illustrates a block diagram of a first embodiment of the present invention, a circuit 30 including a charge pump 32 driving SMPS drivers 14 and 16 . The charge pump comprises a first driver X 1 and a second driver X 2 , the drivers obtaining a clock signal by timing generator 34 . Switches S 1 and S 2 are driven by the first driver X 1 and second driver X 2 , respectively. A switch S 3 is coupled to capacitor C 0 and a ground terminal 22 . Switch S 4 is coupled to C 0 and S 1 , as well as switch S 5 . The signal from switch S 5 is the voltage V boot which is used to power driver 14 . The signal V drv at switch S 4 is used to power driver 16 . Signal V drv is connected to capacitor C 1 , which capacitor C 1 is connected to ground terminal 22 . Drivers 14 and 16 are controlled by SMPS control 18 . Driver 14 is controllably coupled to transistor MN 1 , and driver 16 is controllably coupled to transistor MN 2 . A capacitor C 2 is connected to the source of transistor MN 1 at one end and to the node containing signal V boot at the other end. The node at the source of transistor MN 1 defines a phase node 20 at which the signal V phase is located. The drain of transistor MN 2 is coupled to the phase node 20 , and the source of transistor MN 2 is connected to ground terminal 22 . An inductor L 1 is connected at one end to the phase node 20 and at the other end to an output terminal V out . A load capacitor C L and a load R load comprising a processor, DSP, or logic IC, for example, are coupled across V out and the ground terminal 22 . The circuit 30 provides an output voltage V out when an input voltage V in is applied to the circuit.

In the preferred embodiment of the circuit 30 shown in FIG. 2 , an additional switch S 6 is connected at one end to the bootstrap capacitor C 2 and also to an additional capacitor C 3 which is connected to the ground terminal 22 at the other end. The voltage at a node V 3 between capacitors C 3 and switch S 6 is used to power the drivers X 1 and X 2 of the charge pump 32 . When the end of capacitor C 2 connected to V boot is high, some of the charge from node V boot is transferred through switch S 6 to capacitor C 3 . The voltage at node V 3 is approximately equal to (V in plus V drv ) and is used to power drivers X 1 and X 2 for switches S 1 and S 2 , in the charge pump 32 . Because V 3 is V drv higher than V in , switches S 1 and S 2 are preferably NMOS devices, rather than being PMOS as in the prior art. This is advantageous because NMOS devices require the lowest amount of lateral semiconductor area for their required Rds on . Using an NMOS FET may require 50,000 square microns versus the 75,000 to 100,000 square microns required by a PMOS FET. This results in a semiconductor real estate savings of 25,000 to 50,000 square microns, for each PMOS FET replaced by an NMOS FET. Switch S 3 is preferably NMOS and may be driven directly from V drv . Depending on the minimum level of V in , it may also be possible to make S 4 an NMOS FET driven off V 3 because the gate drive of S 4 will be V in above V drv . However, if V in is too low to allow sufficient gate drive for switch S 4 , a PMOS FET maybe used. Preferably, switches S 1 , S 2 , S 3 and S 4 are NMOS FETs to save the most amount of semiconductor real estate, although any one or several of them may also be PMOS, as the circuit design requires. Switch S 5 is preferably a PMOS device.

Preferably in order to reduce diode losses internal to FETs, switches S 1 , S 2 , S 3 , S 4 , S 5 , and S 6 are MOS transistors. The sequencing of the MOS FETs is very closely tied to the switching of the main converter. At initial power up, the main converter is not running, and the charge pump 32 pumps V drv and V boot up to their target voltages. The phase node 20 is initially at 0 V. The target voltage of bootstrap voltage V boot is approximately equal to V drv . Also at initial power up, the charge pump 32 does not have V 3 available yet, so the charge pump 32 runs at reduced efficiency. However, the main load on the charge pump 32 , the main load being the main converter comprising SMPS drivers 14 and 16 , is not running, so full efficiency is not yet required. An auxiliary clock is preferably an external oscillator and is represented by the timing generator 34 generates the timing for the charge pump 32 . Once voltages V drv and V boot are precharged sufficiently to start the main converter, the control of the timing of the charge pump 32 is handed over to the main converter and the main converter is then allowed to start. Once the main converter starts, the phase node 20 begins switching, so voltage V boot now switches between V drv and (V drv +V in ), and V 3 equals approximately (V drv +V in ). The charge pump 32 is able to run off a higher supply in accordance with the present invention, achieving full efficiency operation.

FIG. 3 shows a timing diagram for the circuit 30 of FIG. 2 once the system has been running for some time, with the x-axis representing time. At time “a,” switch S 6 is open and V phase (signal 42 ) at the phase node 20 rises from 0 V to V in . V boot (signal 44 ) is pushed up via the capacitor C 2 from approximately V drv to (V drv +V in ). At time “b” switch S 6 closes (signal 46 ), allowing capacitor C 3 to charge from V boot , shown at V 3 (signal 47 ). At time “c”, the charge pump 32 reaches the point in its sequence when switch S 1 needs to be closed (signal 48 ). Because V boot is at approximately (V drv +V in ), V boot can be used to drive an NMOS FET rather than a PMOS FET of the prior art to perform the switching function for switch S 1 . In the first embodiment where S 6 and capacitor C 3 are present, the voltage V 3 on capacitor C 3 is used to power the drivers X 1 and/or X 2 that drive the gates of switches S 1 and S 2 , respectively, which switches are preferably NMOS FETs.

At time “d”, switch S 1 is opened (signal 48 ) before V boot falls again to V drv . At time “e”, switch S 6 is opened (signal 46 ) before V boot falls to V drv . At time “f”, V phase and V boot fall (signals 42 and 44 , respectively). In the preferred embodiment, capacitor C 3 and switch S 6 are present so the voltage on V 3 (at signal 47 ) is held roughly equal to the peak voltage on V boot (signal 44 ), or (V drv +V in ). At time “g” switch S 2 is closed (signal 50 ) and according to the preferred embodiment the voltage on V 3 (signal 47 ) is used to drive an NMOS FET for switch S 2 . Voltage V 3 (signal 47 ) fluctuates from approximately (V drv +V in −200 mV) to (V drv +V in ). At time “h”, S 2 is closed again (signal 50 ) and the cycle is ready to restart.

FIG. 4 illustrates in more detail portions of the circuit 30 shown in FIG. 2 . The gates of switches S 1 and S 2 , which preferably comprise NMOS FETs, are driven by drivers X 1 and X 2 respectively. Switch S 3 also preferably comprises an NMOS FET. A Schottky diode implemented for switch S 6 , although a PMOS FET may also be used for switch S 6 , as shown in FIG. 2 . Capacitor C 3 is preferably a capacitor of approximately 0.1 μF for example.

FIG. 5 shows a second embodiment of the present invention where driver X 1 is powered from V boot rather than V in . This is advantageous because one less pin is required on the device, compared with the first embodiment, and an external capacitor C 3 is not required as in the first embodiment. However, switch S 2 does not derive benefit from an increased gate drive and is powered by Vin as in the prior art. In this configuration, S 2 cannot be powered by V boot , because V boot is not in the high state when switch S 2 is required to be on. An additional advantage of the second embodiment is that an additional switch S 6 is not required, as in the first embodiment. However, the second embodiment is the less preferred implementation of the present invention because V 3 does not exist and switch S 2 must be implemented as a less efficient and real estate consuming PMOS FET device.

FIG. 6 shows a corresponding timing diagram 60 for the second embodiment. The timing of the second embodiment is similar to that of the first embodiment, without S 6 and V 3 shown. At time “a,” V phase (signal 42 ) at the phase node 20 rises from 0V to V in . V boot (signal 44 ) is pushed up via the capacitor C 2 from approximately V drv to (V drv +V in ). At time “c”, the charge pump 32 reaches the point in its sequence when switch S 1 needs to be closed (signal 48 ). Because V boot is at approximately (V drv +V in ), V boot can be used to drive an NMOS FET rather than a PMOS FET of the prior art to perform the switching function for switch S 1 . The voltage V boot on bootstrap capacitor C 2 is used to power the driver X 1 that drives the gate of switch S 1 , which switch is preferably an NMOS FET. At time “d”, switch S 1 is opened (signal 48 ) before V boot falls again to V drv . At time “f”, V pase and V boot fall (signals 42 and 44 , respectively). At time “g” switch S 2 is closed (signal 50 ). At time “h” S 2 is closed again (signal 50 ) and the cycle is ready to restart.

One advantage of the present invention is that at least one driver of a switch in the charge pump circuit is powered by a voltage higher than the input voltage of the circuit. This allows NMOS FETs to be used for the majority of switches S 1 , S 2 , S 3 , S 4 and S 5 in the charge pump circuit. Because NMOS FETs require less semiconductor area than the PMOS FETS used for switches in the prior art, the present invention saves semiconductor real estate.

Another advantage of the present invention is that noise generated by the charge pump is inherently synchronous to the main switching converter, which reduces the likelihood that charge pump noise will interfere with the main converter. This is particularly advantageous if the main converter is running fixed frequency to reduce interference, as it is often the case in sampled data system in communication systems, where the charge pump noise lies in the same frequency bands as the main converter noise.

Another advantage of the present invention is that the main load of the charge pump is the gate charge required for the main switching converter power FETs, which synchronizes the charge pump to the main converter, making the charge pump output approximately track the demand.

An advantage of the second embodiment of the present invention is that no additional components are required to achieve a voltage, Vboot, higher than voltage V in powering the driver X 1 of the first switch S 1 . This allows the use of a semiconductor real estate saving PMOS FET for switch S 1 .

While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. For example, preferably four of the five switches within the charge pump are implemented as NMOS FET devices in the present invention. However, fewer than four switches may be implemented as NMOS devices, as is advantageous in each particular application. The charge pump circuit of the present invention may be utilized with a power converter in a wide variety of applications, such as digital signal processors, microprocessors, telecommunications applications, mobile devices and systems, laptops and personal computers, mixed signal and analog devices, and any lower power electrical application, in general.

Claims

1. A switch mode power converter powered by a charge pump circuit, comprising:a first, second, third, fourth and fifth switch coupled together in a charge pump circuit, said first switch connected to the input voltage terminal and driven by a first driver, said second switch connected to the input voltage terminal and driven by a second driver, said charge pump arrangement providing a bootstrap voltage at a bootstrap voltage terminal; a first capacitor coupled between said drive voltage terminal and a ground terminal; a first transistor driven by said first driver and coupled to said input voltage terminal and a phase node; a second capacitor connected at one end to said bootstrap voltage terminal and at the other end to said phase node; and a second transistor coupled to the output of the second driver, said phase node and said ground terminal, wherein at least the first driver is powered by a voltage higher than the input voltage at said input voltage terminal.

2. The converter of claim 1 further comprising said second driver being powered by a voltage higher than the input voltage at said input voltage terminal.

3. The converter of claim 1 further comprising:a sixth switch coupled to said bootstrap voltage terminal; and a third capacitor having a first end connected to said ground terminal and a second end coupled to said sixth switch, the voltage at the second end of said third capacitor powering at least said first driver driving said first switch of said charge pump arrangement.

4. The converter of claim 2, further comprising said voltage at the second end of said third capacitor powering said second driver driving said second switch.

5. The converter of claim 1 wherein said first driver driving said first switch is powered by said bootstrap voltage.

6. The converter of claim 1 wherein said converter comprises a semiconductor material and wherein at least said first and second switches of said charge pump arrangement comprise NMOS FETs, reducing the lateral physical area of said semiconductor material of said charge pump arrangement.

7. The converter of claim 1 wherein the voltage at the second end of said third capacitor is 2.5 volts or greater.

8. The converter of claim 1 wherein said charge pump arrangement comprises:a third switch coupled to said second switch and said ground terminal; a fourth switch coupled to said first switch and to said drive voltage terminal; and a fifth switch coupled to said first switch and said bootstrap voltage terminal.

9. A method of operating a switch mode power converter powered by a charge Dump circuit, comprising the steps of:providing a plurality of switches coupled together in a charge pump arrangement and operating from an input voltage, said plurality of switches including at least a first switch and a second switch, said first and second switches being driven by a first driver and second driver, respectively; generating a second voltage internal to said circuit, said second voltage being greater than said input voltage; and powering at least said first driver with said second voltage.

10. The method of claim 9 further comprising the step of:powering said second driver with said second voltage.

11. The method of claim 9 further comprising the step of:providing a third switch having a first and second end; providing a capacitor at said second end of said third switch; and selectively switching said third switch to generate said second voltage at said first end of said third switch.

12. The method of claim 9 wherein at least said first switch is an NMOS FET.

13. The method of claim 9 further comprising the step of:coupling said second voltage of said circuit to a switch mode power converter.