1. Field
The disclosure relates to charge pumps, and in particular, to techniques for reducing surge current drawn from a charge pump voltage supply during charge pump operation.
2. Background
Charge pumps are commonly utilized in electronic circuitry to step a given voltage supply level up or down, and/or to invert the supply to an inverse voltage level to power a loading circuit. A charge pump may find application in, e.g., a class G amplifier architecture, wherein the voltage supply level provided to an amplifier may be varied depending on the level of the input signal to be amplified. In such applications, a charge pump may be used to provide the variable voltage supply levels to a power amplifier, e.g., in response to an indication of the input signal level as determined by a charge pump controller. The charge pump controller may, e.g., control a gain mode of the charge pump, and/or a charge pump switching frequency.
During charge pump operation, a plurality of switches may be alternately configured to charge one or more capacitors using the voltage supply, and then to couple the one or more capacitors to the load. In certain situations, e.g., when a gain mode of the charge pump is switched, a large voltage differential may be placed across one or more of such switches. Such large voltage differentials may cause an unacceptably large surge current to be drawn from the voltage supply.
It would be desirable to provide techniques for reducing the maximum level of surge current drawn by a charge pump, while maintaining efficient overall charge pump operation.
Various aspects of the disclosure are described more fully hereinafter with reference to the accompanying drawings. This disclosure may, however, be embodied in many different forms and should not be construed as limited to any specific structure or function presented throughout this disclosure. Rather, these aspects are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Based on the teachings herein one skilled in the art should appreciate that the scope of the disclosure is intended to cover any aspect of the disclosure disclosed herein, whether implemented independently of or combined with any other aspect of the disclosure. For example, an apparatus may be implemented or a method may be practiced using any number of the aspects set forth herein. In addition, the scope of the disclosure is intended to cover such an apparatus or method which is practiced using other structure, functionality, or structure and functionality in addition to or other than the various aspects of the disclosure set forth herein. It should be understood that any aspect of the disclosure disclosed herein may be embodied by one or more elements of a claim.
The detailed description set forth below in connection with the appended drawings is intended as a description of exemplary aspects of the invention and is not intended to represent the only exemplary aspects in which the invention can be practiced. The term “exemplary” used throughout this description means “serving as an example, instance, or illustration,” and should not necessarily be construed as preferred or advantageous over other exemplary aspects. The detailed description includes specific details for the purpose of providing a thorough understanding of the exemplary aspects of the invention. It will be apparent to those skilled in the art that the exemplary aspects of the invention may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the novelty of the exemplary aspects presented herein.
In
As shown in
In
It will be appreciated from the aforementioned configuration of switches that the total voltage across Cfly will approach Vdd/2 in steady state (subject to loading), as Phases I and II effectively divide the supply voltage Vdd in half between Vpos and GND during Phases I and II. During Phase III, Cfly is inverted, and Vneg approaches −Vdd/2.
During Phase II, terminals C1p and C1n are coupled to GND and Vneg nodes, respectively. In this phase, C1n is coupled to the negative output voltage node Vneg via switch S5, thereby causing the voltage Vneg to approach −Vdd, and charging one of the terminals of capacitor Cneg 162 (not shown in
One of ordinary skill in the art will appreciate that in alternative exemplary embodiments, the sequence of the phases need not be as shown in
As earlier described with reference to
In an aspect of the present disclosure, techniques are provided to reduce surge current drawn by the charge pump from the voltage supply VDD when switching a gain mode of the charge pump. As earlier described with reference to
Plot 5b) shows the current I_Vdd drawn from the voltage supply Vdd over the time period corresponding to plot 5a). As seen from plot 5b), at t0, I_Vdd surges to a maximum value 10 at time t0, in response to the voltage difference across S1 being approximately Vdd/2, as earlier described herein. After t0, I_Vdd decreases over time as the node Vpos is gradually charged. It will be seen that the current of 10 momentarily exceeds the maximum power supply current limit Imax immediately following t0.
To reduce the surge current, it will be appreciated that the on-resistance R_S1 may be increased. However, increasing R_S1 would undesirably increase the time required to charge Vpos, increase the equivalent resistance on Vpos, and also increase the amount of voltage ripple present on Vpos.
In an exemplary embodiment, R_S1 may be dynamically decreased over time during Gain=1, Phase I, to advantageously reduce surge current resulting from gain switching, while simultaneously preserving low on-resistance during steady state operation.
It will be appreciated that the profile shown for the decrease in R_S1 over time is given for illustrative purposes only, and is not meant to limit the scope of the present disclosure to any particular profile shown. In an exemplary embodiment, R_S1 may be decreased in discrete steps, e.g., by successively closing switches coupled in parallel, as further described hereinbelow. In alternative exemplary embodiments, other techniques for decreasing resistance over time may be applied, e.g., continuously decreasing the channel resistance of an MOS transistor by increasing a gate control voltage, etc. Note R_S1 may be decreased linearly over time, or according to any other functional relationship. Such alternative exemplary embodiments are contemplated to be within the scope of the present disclosure.
In
In a further exemplary embodiment, the techniques described for decreasing the on-resistance of switch S1 may be similarly applied to the bypass switch S7, earlier described herein with reference to
While exemplary embodiments have been described herein for changing the on-resistance of switches S1 and S7, it will be appreciated that the on-resistance of any of the switches S1-S7 may be varied according to the principles of the present disclosure. Such alternative exemplary embodiments are contemplated to be within the scope of the present disclosure.
In
At block 1120, the on-resistance of at least one of the plurality of switches is varied over time.
In
The charge pump controller 110 accepts the digital input signal Vin 100a, and generates a charge pump gain control signal cp_gain 110a and a charge pump frequency control signal cp_fclk 110b. The signals 110a, 110b are provided to the charge pump 120 to control the charge pump gain setting and the charge pump switching frequency, respectively. The charge pump 120 includes a switch control module 123 which may control the operation of switches and sub-switches within the charge pump, as well as vary the on-resistance of any of the switches within the charge pump, e.g., as described with reference to
In an exemplary embodiment, per class G amplifier operation, the charge pump controller 110 adjusts the signal 110a to, e.g., increase the voltage Vpos 120a (and decrease the voltage Vneg 120b) when the magnitude of the signal Vin 100a is higher, and correspondingly decrease the voltage Vpos 120a (and decrease the voltage Vneg 120b) when the magnitude of Vin 100b is lower. The charge pump controller 110 may further adjust the signal 110b to, e.g., increase the charge pump switching frequency when the level of the signal Vin 100a is higher, and decrease the charge pump switching frequency when the level of the signal Vin 100a is lower.
In the exemplary embodiment shown, power to the charge pump 120 is supplied by the voltage Vdd 105a from a switched-mode power supply (SMPS) 105. It will be appreciated that in alternative exemplary embodiments, the voltage Vdd 105a need not be supplied by an SMPS module, and may instead be supplied by any other type of voltage supply known in the art.
In this specification and in the claims, it will be understood that when an element is referred to as being “connected to” or “coupled to” another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected to” or “directly coupled to” another element, there are no intervening elements present.
Those of skill in the art would understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.
Those of skill in the art would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the exemplary aspects disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the exemplary aspects of the invention.
The various illustrative logical blocks, modules, and circuits described in connection with the exemplary aspects disclosed herein may be implemented or performed with a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
The steps of a method or algorithm described in connection with the exemplary aspects disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), flash memory, Read Only Memory (ROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal.
In one or more exemplary aspects, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-Ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.
The previous description of the disclosed exemplary aspects is provided to enable any person skilled in the art to make or use the invention. Various modifications to these exemplary aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other exemplary aspects without departing from the spirit or scope of the invention. Thus, the present disclosure is not intended to be limited to the exemplary aspects shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
This application is related to U.S. patent application Ser. No. 12/041,414, entitled “System and Method for Reducing Power Consumption for Audio Playback,” filed Mar. 3, 2008, and to U.S. patent application Ser. No. 12/407,238, entitled “Digital Filtering in a Class D Amplifier System to Reduce Noise Fold Over,” filed Mar. 19, 2009, the contents of which are hereby incorporated by reference herein in their entirety.