Patent Application
20150192943
1. Field
The present invention relates generally to voltage regulators. More specifically, the present invention relates to embodiments for voltage regulators with a charging sharing loop.
2. Background
Power management plays an important role in the current day electronics industry. Battery powered and handheld devices require power management techniques to extend battery life and improve the performance and operation of the devices. One aspect of power management includes controlling operational voltages. Conventional electronic systems, particularly systems on-chip (SOCs) commonly include various subsystems. The various subsystems may be operated under different operational voltages tailored to specific needs of the subsystems. Voltage regulators may be employed to deliver specified voltages to the various subsystems. Voltage regulators may also be employed to keep the subsystems isolated from one another.
Low dropout (LDO) voltage regulators are commonly used to generate and supply low voltages, and achieve low-noise circuitry. Conventional LDO voltage regulators require a large external capacitor, frequently in the range of a several microfarads. These external capacitors occupy valuable board space, increase the integrated circuit (IC) pin count, and prevent efficient SOC solutions.
As will be appreciated by a person having ordinary skill in the art, a load coupled to a voltage regulator may require a large periodic current (i.e., during an active load period), which may lead to a substantial droop in an output voltage. This droop may adversely affect the functionality of the load. Further, an abrupt current draw from an input voltage port (e.g., an input pin of an integrated circuit) to compensate a load current may generate large ripples at the input voltage, thus causing noise for other blocks supplied by the input voltage.
A need exists for an enhanced linear voltage regulator. More specifically, a need exists for embodiments related to voltage regulators including a charge sharing loop.
The detailed description set forth below in connection with the appended drawings is intended as a description of exemplary embodiments of the present invention and is not intended to represent the only embodiments in which the present invention can be practiced. The term “exemplary” used throughout this description means “serving as an example, instance, or illustration,” and should not necessarily be construed as preferred or advantageous over other exemplary embodiments. The detailed description includes specific details for the purpose of providing a thorough understanding of the exemplary embodiments of the invention. It will be apparent to those skilled in the art that the exemplary embodiments of the invention may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the novelty of the exemplary embodiments presented herein.
With reference again to
Exemplary embodiments, as described herein, are related to voltage regulators. According to one exemplary embodiment, a device may include a first energy storage element coupled between a ground voltage and an output. The device may further include a second energy storage element coupled to the ground voltage and configured to selectively couple to the output. Additionally, the device may include a voltage regulator coupled between an input and the second energy storage element.
According to another exemplary embodiment, a device may include a voltage regulator configured to receive an input voltage and convey an output voltage to a first node. The device may also include a first energy storage element coupled between the first node and a ground voltage, and a second energy storage element coupled between the ground voltage and an output node. Moreover, the device may include a switch configured to couple the first energy storage element to the output node during an active load period.
In accordance with yet another exemplary embodiment, a device may include a first voltage regulator coupled between an input and a first output node, wherein the first output node is configured to couple to a load. Furthermore, the device may comprise a first capacitor coupled between a ground voltage and the first output node. In addition, the device may include a second voltage regulator coupled between the input and a second output node, and a second capacitor coupled between the ground voltage and the second output node. The device may further include a switch configured to couple the second output node to the first output node.
According to another exemplary embodiment, the present invention includes methods related to operation of a voltage regulator. Various embodiments of such a method may include charging a first energy storage element coupled to an output of a voltage regulator to a first voltage and charging a second energy storage element to a second voltage. The method may also include coupling the first energy storage element to the second energy storage element during an active load period. According to another exemplary embodiment, a method may include conveying a first output voltage from a first voltage regulator to a first capacitor coupled between a ground voltage and an output. Additionally, the method may include conveying a second output voltage from a second voltage regulator to a second capacitor coupled to the ground voltage. Further, the method may include selectively coupling the second capacitor to the output during an active load period.
Other aspects, as well as features and advantages of various aspects, of the present invention will become apparent to those of skill in the art through consideration of the ensuing description, the accompanying drawings and the appended claims.
With continued reference to
An input of LDO voltage regulator 404 is coupled to node A is configured to receive the input voltage Vpin and an output of LDO voltage regulator 404 is coupled to a node B and is configured to convey another output voltage Vaux. Node B, which is coupled between a switch S and capacitor Cout_aux, may be switchably coupled to target block 406 via switch S. Further, voltage regulator 404 may be configured to receive a feedback voltage at an output of voltage regulator 402.
As will be appreciated by a person having ordinary skill in the art, in comparison to device 100 illustrated in
In comparison to conventional devices, the output voltage ripple of device 400 may be significantly reduced, a total capacitor size of device 400 may be reduced, or both. Further, an abrupt current draw from node A may be reduced and, therefore, a large ripple may not be induced on the input voltage supplied to voltage regulator 402 and LDO voltage regulator 404. In addition, the second feedback loop (i.e., feedback from output voltage Vout to LDO voltage regulator 404) may avoid under-compensation (i.e. large output ripples), over-compensation (i.e. drift of output voltage to higher than set), or both.
As will be appreciated by a person having ordinary skill in the art, in a case wherein a non periodic portion of a load is very small, the main voltage regulator provides little to no current. Therefore, in accordance with an exemplary embodiment of the present invention, the main LDO voltage regulator may be omitted and the boost loop provides all current for the load.
An input of LDO voltage regulator 404 is coupled to node A and is configured to receive input voltage Vpin and an output of LDO voltage regulator 404 is coupled to node B and is configured to convey another output voltage Vaux. Node B, which is coupled between switch S and capacitor Cout_aux, may be switchably coupled to target block 406 via switch S. Further, voltage regulator 404 may be configured to receive a feedback voltage at an output of voltage regulator 402.
In addition, a gate of transistor M1 may be coupled to a gate of transistor M2, which is further coupled to the drain of transistor M2. A gate of transistor M4 is configured to receive a reference voltage VREF. A transistor M3 is coupled between input voltage Vpin and capacitor Cout_aux, which is further coupled to a ground voltage. More specifically, a source of transistor M3 is coupled to input voltage Vpin and a drain of transistor M3 is coupled to a node C, which is coupled to ground voltage GRND via capacitor S capacitor Cout_aux YS. Moreover, a gate of transistor M3 is coupled to a drain of transistor M1 and a drain of transistor M4. Furthermore, node C is switchably coupled to an output of circuit diagram 600 via switch S. A gate of transistor M5 is coupled to a node D, which is coupled between the output of circuit diagram 900 and capacitor Cout_main. Capacitor Cout_main is further coupled to ground voltage GRND.
Exemplary embodiments of the present invention, voltage regulators with charge-sharing loops may reduce area and/or input/output voltage ripple for periodic loads without loss of efficiency. Exemplary embodiments may be applicable to linear voltage regulators, which are very common building in various analog, mixed signal and RF products. The present invention includes a rather simple yet elegant solution and it is not limited to an specific circuit implementation. Compared to a linear LDO, there is no significant loss of efficiency. For a linear LDO, a total charge may be drawn from a supply voltage and delivered to target block. For the introduced charge sharing LDO, the same charge may be drawn and delivered to load in two steps. Further, the total power consumption may be substantially the same, and the only difference is, compared to power dissipation inside a linear LDO, the power dissipation in the present invention is divided into power dissipation of a main LDO plus an auxiliary LDO and a switch. Any extra overhead due to power need of a second loop may be neglected in practical cases.
Those of skill in the art would understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the exemplary embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the exemplary embodiments of the invention.
The various illustrative logical blocks, modules, and circuits described in connection with the exemplary embodiments disclosed herein may be implemented or performed with a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
In one or more exemplary embodiments, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.
The previous description of the disclosed exemplary embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these exemplary embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the exemplary embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
