Patent Grant
8976099
This nonprovisional application claims priority under 35 U.S.C. §119(a) on Patent Application No. 1009480.3 filed in the United Kingdom on Jun. 7, 2010, the entire contents of which are hereby incorporated by reference.
The invention is a low leakage charge storage circuit, suitable for use in, for example, an active matrix display, a DRAM etc. It also relates to a display incorporating one or more charge storage circuits of the invention.
In use, rows of pixel display data are supplied by the data driver 4 to the source electrodes 9 in synchronism with scan pulses which are supplied by the scan driver 6 to the gate lines 11 in a cyclically repeating sequence. Thus the row of pixels are refreshed one at a time until all of the rows have been refreshed so as to complete the refreshing of a frame of display data. The process is then repeated for the next frame of data.
When the gate line 11 of each pixel receives a scan pulse from the scan driver 6, the voltage on the source electrode 9 causes the storage capacitor 16, and the pixel electrode of the display element, to be charged. When the scan pulse is removed, the transistors 8, 10 isolate the pixel electrode and the storage capacitor from the source electrode 9 so that the optical property of the associated display element 14 corresponds to the stored voltage across the display element 14 until it is refreshed during the next frame. (The voltage across the display element 14 is not necessarily equal to the voltage across the storage capacitor 16, since the counter plate electrode 20 of the display element 14 and the second plate 18 of the storage capacitor 16 may be at different potentials to one another.)
Methods of using capacitive coupling to the pixel electrode in active matrix displays, in order to apply an offset to the data signal voltage, both to minimise the range of signal voltages which is required to produce a full range of pixel luminances from fully off to fully transmissive, and to provide a power efficient means of alternating the polarity of the voltage across the liquid crystal layer in each pixel regions every frame are also well known. Capacitively coupled driving, in which the signal data voltage is supplied to the pixel electrode from the source electrode 9, via transistors 8, 10, during the period the gate line 11 of each pixel receives a scan pulse from the scan driver 6, in order to charge the pixel electrode and storage capacitor 16 to the voltage of the data signal, and then after the scan pulse is removed, an offset is imposed to the data voltage on the pixel electrode via capacitive coupling to the pixel electrode of a second voltage applied to the second plate 18 of the storage capacitor 16, is described in EP0336570A1 (11 Oct. 1989) and U.S. Pat. No. 5,296,847 (22 Mar. 1994, Matsushita) and in Tsunashima et al, SID Digest '07, pp 1014-1017.
The isolation transistors 8, 10 are not perfect. They exhibit a finite leakage drain current as illustrated in
The leakage current results in a degradation of the programmed pixel electrode voltage over time T according to Equation 1 where Vpix is the pixel electrode voltage, Ileak is the leakage current, Cs is the storage capacitance and Clc is display element capacitance.
The pixel electrode voltage degradation due to leakage current requires the display data to be rewritten to minimise image deterioration during the hold time. A frame refresh rate of 60 Hz is typical. This constant refreshing of the display results in significant power consumption. One approach to reducing this power consumption is to reduce the frame refresh rate. Frame rate reduction is only possible if the degradation of the pixel electrode voltage is reduced. Considering Equation 1, the pixel electrode voltage degradation can be reduced by either increasing the size of the storage capacitor 16 or reducing the leakage current. A larger storage capacitor 16 is not desirable since it would result in increased pixel area and also increased pixel electrode charging time during scanning of each row. Thus, the preferred approach to reducing the frame refresh rate is to reduce the leakage current.
One known technique for reducing the electric field induced leakage current is to replace the 2 series transistors 8 and 10 with 3 or more transistors in series. This is in order to further reduce the drain voltage for each transistor. It may be noted however that the common gate voltage means that the leakage current does not scale with the number of series transistors. Another known technique, shown in
a) illustrates another technique to increase the hold time over several frames as disclosed in Japanese laid-open patent application No. 5-142573 (11 Jun. 1993). This technique involves “boot strapping”: a unity gain voltage gain amplifier 22 has its input connected to the charge storage node 12 and the pixel electrode and its output connected to the junction between transistors 8 and 10. In other words the circuit of
U.S. Pat. No. 6,064,362 (16 May 2000) and U.S. Pat. No. 7,573,451 (11 Aug. 2009) disclose a pixel circuit with a feedback buffer amplifier which as in the Japanese laid-open patent application No. 5-142573 aims to reduce the leakage from the storage node. The buffer amplifier in both disclosures consists of at least 2 additional transistors.
The power consumption of each of these 3 previous pixel circuits is dominated by the power consumption of the buffer amplifier which will make a significant contribution to the total power consumption of the active matrix display.
Transistor Characteristics
A first aspect of the invention provides a charge storage circuit for a pixel, the circuit comprising: a charge storage node; first and second transistors for selectively isolating the charge storage node from a first voltage input for supplying a data voltage, the first and second transistors being series-connected; and a voltage follower circuit for replicating a voltage at the charge storage node (12) at another node in the circuit such that the drain-source voltage across the second transistor is reduced; wherein the voltage follower circuit comprises the first transistor.
The present invention employs a voltage follower to reduce the leakage current through the first and second transistors, which are isolation transistors for isolating, in a voltage holding mode, the charge storage node from the voltage input. The voltage follower replicates, as closely as possible, the voltage at the charge storage node at another node in the circuit so that the drain-source voltage across the second transistor is reduced. The drain-source voltage across the second transistor preferably reduced to zero or almost to zero (and is reduced to zero if the voltage follower circuit exactly replicate the voltage at the charge storage node (12) at the other node). This reduction in the drain-source voltage across the second transistor leads to a reduction in the leakage current through the second transistor (and in principle the leakage current through the second transistor may be reduced to zero if the drain-source voltage across the second transistor is reduced to zero). According to the invention, one of the isolation transistors is used as part of the voltage follower, thereby reducing the number of additional components that must be provided for the voltage follower and also reducing the area occupied by the voltage follower. The invention thus reduces the leakage current, and hence reduces the required frame refresh rate, for little or no increase in the area of the pixel.
Advantages of the invention over the prior art include the following:
Preferred embodiments of the invention will be described by way of illustrative example with reference to the accompanying figures in which:
First Embodiment
A first embodiment is shown in
Connections supplied to the pixel are as follows:
Also shown is a load element Clc 14 representing the impedance of the optical element between the charge storage node 12 and the counter plate node 20 in the case of a liquid crystal display. (In the case of an active matrix display, the counter plate node 20 may be common to all pixels of the display and so form a common electrode.)
The circuit is connected as follows:
The source line 9 is connected to the source of the first transistor 8. The drain of first transistor 8 is connected to the source of second transistor 10. The gate line 11 is connected to the gates of the first and second transistors 8, 10. The drain of second transistor 10 is connected to the storage node 12. The storage capacitor Cs 16 is connected between the storage node 12 and the capacitor bias line 18. The load element Clc 14 is connected between storage node 12 and the counter plate node 20 (so that the storage node 12 can also be considered as forming the pixel electrode). The storage node 12 is also connected to the gate of the third transistor 30. The drain of the third transistor 30 is connected to the power supply line 32 and the source of the third transistor 30 is connected to a first node between the first transistor and the second transistor—in this embodiment the first node is connected to the drain of the first transistor 8 and source of the second transistor 10.
The operation of the circuit is as follows:
In operation the circuit performs two functions, first writing a voltage to the storage node 12 and then holding the voltage written on to the storage node 12.
The voltage writing mode is the same as that of a standard active matrix display described in the prior art, for example is the same as described above with reference to the circuit of
If desired, after the scan pulse is removed, an offset may be imposed to the data voltage on the pixel electrode via capacitive coupling to the pixel electrode of a second voltage applied to the second plate 18 of the storage capacitor 16. The voltage holding mode is, in this embodiment, enabled once all rows of the pixel matrix have been written.
During the voltage holding mode, the source line 9 is programmed by the scan driver 6 at a voltage which biases the first transistor 8 in the subthreshold region. This voltage is preferably set to be the same as the low level of the gate line 11 voltage, resulting in the first transistor biased with zero volts gate-source voltage (Vgs). The power supply line 32 is, in use, maintained at a voltage level higher than the highest data voltage during the hold mode (and also during the write function as well). With these bias conditions the third transistor 30 and first transistor 8 forms a voltage follower with the input being the data voltage written on to the storage node 12 and the output connected to the source of the second transistor 8. Alternatively, the Vgs of the first transistor 8 may be set to a non-zero value to allow optimisation of the bias current and therefore the power consumption. (The amount by which the voltage Vgs may vary from zero will depend on the transistor process conditions, but typically may vary from zero by up to a few hundred millivolts.)
The voltage follower replicates, as closely as possible, the voltage at the charge storage node at another node in the circuit so that the drain-source voltage across the second transistor 10 is reduced, and preferably is reduced to zero or almost to zero. In the circuit of
In more detail, the voltage follower operates as follows:
The first transistor 8 is typically biased with a 0V Vgs, which sets the bias current to a first order since the drain current of a transistor biased in the subthreshold region is only weakly dependant on the drain-source voltage (Vds) of a transistor as shown in
The write function is repeated when the storage node data requires updating.
Advantages of this embodiment include the following:
It will be apparent to one skilled in the art that this embodiment could also be implemented with the second transistor 10 formed as a dual gate transistor 10a, 10b as shown in
Second Embodiment
A second embodiment is shown in
The operation of the circuit is the same as the first embodiment. The voltage follower which is necessary for the voltage holding mode is now formed by the four transistors 8a, 8b, 30a and 30b.
This voltage follower operates as follows:
Transistors 8a and 30b have the same function as transistors 8 and 30 in the first embodiment. The voltage follower performs well when the bias conditions of transistors 8 and 30 are the same. As in the first embodiment, transistor 8a is biased in the subthreshold region with typical Vgs of zero volts. The role of transistors 8b and 30a act is to provide similar bias conditions for transistors 8a and 30b as the input voltage. This behaviour can be demonstrated by considering the two cases of pixel electrode voltages, Vpix: a high value close to the power supply line voltage and a low value close to the source line voltage.
For the case of a high value pixel electrode voltage, Vpix:
In this case, transistor 8b has absorbed a large Vds which results in transistors 8a and 30b having very similar bias conditions.
For the case of a low value pixel electrode voltage, Vpix:
In this case, transistor 30a has absorbed a large Vds which results in transistors 8a and 30b having very similar bias conditions.
An advantage of this embodiment is as follows
A third embodiment is shown in
Fourth Embodiment
A fourth embodiment is shown in
In operation the circuit performs two functions, writing a voltage to the storage node 12 and holding the voltage written on to the storage node 12.
The write function is the same as the previous embodiments except transistor 34 is switched off when the gate line 11 receives a scan pulse from the scan driver 6. The write operation on each row is completed when the scan pulse is removed from the gate line 11 to switch off the two transistors 10, 36. This step also switches on transistor 34. The voltage holding mode is enabled on a row by row basis immediately after each row has been written. The switched on transistor 34 passes the bias line 13 voltage to the source of transistor 8. As in the first embodiment, transistors 8 and 30 form a voltage follower with transistor 8 biased in the subthreshold region with a typical 0V Vgs.
An advantage of this embodiment is that once a pixel been written, the voltage holding mode can be activated immediately by using the bias line 13 to bias the voltage follower. Source line 9 can continue to be used to write to pixels of other rows of the active matrix display. Pixel electrode voltage degradation due to source line voltage variations is thus avoided. (The pixel area in this embodiment is likely to be greater than in other embodiments, owing to the need for the additional supply line and transistors.)
It will be apparent to one skilled in the art that this embodiment could also be implemented with the transistor 34 formed as an n-type transistor. In this case a separate gate line is required to control the switch transistor 34. This gate line is then driven with voltage signals that are complementary to those applied to gate line 11.
It will be apparent to one skilled in the art that above embodiments could also be implemented using transistors of a complementary type to those described in these embodiments. Complementary signal and power lines must also be applied, that is active low voltages are applied instead of active high voltages and vice versa.
A circuit of the invention may be applied in an active matrix LCD, for example to the AMLCD of
It will be apparent to one skilled in the art that any of the previous embodiments are not restricted to active matrix LCD. The embodiments may be applied to other active matrix display technologies such as organic light emitting diode (OLED) displays, micro electro-mechanical (MEMs) displays and electro-wetting displays. The embodiments may be applied as a single circuit or as part of an array or as part of a matrix which is used to store voltage data. One example of this type of application is dynamic random access memories (DRAM).
It will be apparent to one skilled in the art that features of the above embodiments may be combined with one another. For example, while the second transistor 10 is described as embodied by a dual gate transistor in
A first aspect of the invention provides a charge storage circuit for a pixel, the circuit comprising: a charge storage node; first and second transistors for selectively isolating the charge storage node from a first voltage input for supplying a data voltage, the first and second transistors being series-connected; and a voltage follower circuit for replicating a voltage at the charge storage node (12) at another node in the circuit such that the drain-source voltage across the second transistor is reduced; wherein the voltage follower circuit comprises the first transistor.
The present invention employs a voltage follower to reduce the leakage current through the first and second transistors, which are isolation transistors for isolating, in a voltage holding mode, the charge storage node from the voltage input. The voltage follower replicates, as closely as possible, the voltage at the charge storage node at another node in the circuit so that the drain-source voltage across the second transistor is reduced. The drain-source voltage across the second transistor preferably reduced to zero or almost to zero (and is reduced to zero if the voltage follower circuit exactly replicate the voltage at the charge storage node (12) at the other node). This reduction in the drain-source voltage across the second transistor leads to a reduction in the leakage current through the second transistor (and in principle the leakage current through the second transistor may be reduced to zero if the drain-source voltage across the second transistor is reduced to zero). According to the invention, one of the isolation transistors is used as part of the voltage follower, thereby reducing the number of additional components that must be provided for the voltage follower and also reducing the area occupied by the voltage follower. The invention thus reduces the leakage current, and hence reduces the required frame refresh rate, for little or no increase in the area of the pixel.
The first and second transistors may be connected in series between the first voltage input and the charge storage node, the second transistor being connected between the first transistor and the charge storage node. In this embodiment the voltage follower may replicates, as closely as possible, the voltage at the charge storage node at a node between the first transistor and the second transistor.
The circuit may further comprise a third transistor connected between (i) a second voltage input and (ii) a first node between the first transistor and the second transistor, a gate of the third transistor being connected to the charge storage node, the voltage follower circuit comprising the first transistor and the third transistor and, in use, replicating a voltage at the charge storage node at the first node.
A source of the first transistor may be connected to the first voltage input, a drain of the third transistor is connected to the second voltage input, and a source of the third transistor is connected to the first node.
The first transistor and the third transistor may be substantially matched with one another. By saying that two transistors are “matched” with one another is meant that they are matched (to within normal manufacturing tolerances) in at least one, and preferably all of, the following: dimensions (width and length of the transistor), threshold voltage, mobility.
The circuit may be arranged such that, in a voltage holding mode, a gate-source bias voltage applied to the first transistor is equal or substantially equal to a gate-source bias voltage applied to the third transistor. If the gate-source bias voltage applied to the first transistor is equal to the gate-source bias voltage applied to the third transistor, then the first transistor and the third transistor pass the same current (assuming they are matched to one another). This results in zero leakage current through the second transistor.
The circuit may be adapted to apply, in a voltage holding mode, a gate-source bias voltage to the first transistor that biases the first transistor in a sub-threshold region of operation, for example in the sub-threshold region described above with reference to
The circuit may be adapted to apply, in a voltage holding mode, a gate-source bias voltage to the first transistor that is zero or substantially zero. This reduces the power consumption of the charge storage circuit.
The second voltage input may provide, in use, a voltage that is greater than the highest data voltage supplied in use by the first voltage input.
The second transistor may be a dual gate transistor.
The first transistor and the third transistor may each comprise two series-connected transistors.
The circuit may further comprise: a fourth transistor connected in series between the first voltage input and the first transistor; and a fifth transistor connected between (i) a third voltage input and (ii) a second node between the first transistor and the fourth transistor; and the circuit may be operable such that in a voltage holding mode the fifth transistor is ON whereby the second node is connected to the third voltage input. In this embodiment the voltage holding mode may be enabled as soon as a voltage has been written to the charge storage node, by biasing the first transistor using he third voltage input.
The circuit may be operable such that in the voltage holding mode the fourth transistor is OFF, and may be operable such that in a voltage writing mode the fourth transistor is ON and the fifth transistor is OFF.
The fourth transistor may be of opposite conductivity type to the fifth transistor and the gate of the fourth transistor may be connected to the gate of the fifth transistor. This is a convenient way of ensuring that the fourth transistor is ON when the fifth transistor is OFF and vice versa. Alternatively the fourth transistor may be of the same conductivity type as the fifth transistor, with the gates of the fourth transistor and the fifth transistor being controlled by complementary gate signals.
The gate of the fourth transistor may be connected to the gate of the first transistor.
The circuit may comprise a first gate line connected to the gate of the first transistor and a second gate line connected to the gate of the second transistor. This allows independent control of the voltage follower bias voltage. Alternatively the gate of the second transistor may be connected to the gate of the first transistor.
The circuit may comprise a storage capacitor connected to the charge storage node. It may comprise a display element connected to the charge storage node. The display element may be a liquid crystal display element.
Each transistor may be a MOSFET.
A second aspect of the invention provides a display comprising a charge storage circuit of the first aspect. The advantage of a lower frame refresh rate will also apply to a display that uses a charge storage circuit of the invention.
The display may be an active matrix liquid crystal display (AMLCD).
The AMLCD may have a matrix of pixels, and each pixel may have a charge storage circuit of the first aspect
The AMLCD may be arranged to have a voltage writing mode for writing voltages to rows of pixels. After voltages have been written to all pixel rows of the AMLCD, the charge storage circuits of the AMLCD are switched to a voltage holding mode.
Alternatively, if each charge storage circuit is a charge storage circuit having the fourth and fifth transistors, the AMLCD may be arranged to have, for each pixel row, a voltage writing mode for writing to that row and a voltage holding mode.
The invention is a low leakage charge storage circuit, suitable for use within pixels in active matrix displays.
The circuit is composed of at least three MOS transistors. The channels of the first two transistors are series connected. The source of the first transistor is connected to an input line and the drain of the second transistor is connected to a storage capacitor, forming a storage node. The storage node is connected to the gate of the third transistor which has its drain connected to a supply line and its source connected to the junction of the series connected first and second transistors.
Pixel data is written to the storage node by applying a scan pulse to the gates of the first and second transistors. When the scan pulse is removed, the pixel electrode voltage is maintained on the storage node by minimising the source-drain electric field of the second transistor by using a voltage follower to create a copy of the pixel electrode voltage and applying this to the source of the second transistor. The voltage follower is formed by the third and first transistors. The storage node forms the input of the voltage follower and the output is connected to the source of the second transistor. The bias current of the voltage follower is set by the gate and source voltages of the first transistor.
The first transistor performs two roles. During the data writing mode it behaves as an isolation switch and during the data hold mode it is used to bias the voltage follower.
Although the invention has been shown and described with respect to certain preferred embodiments, it is obvious that equivalents and modifications will occur to others skilled in the art upon the reading and understanding of the specification. The present invention includes all such equivalents and modifications, and is limited only by the scope of the following claims.
Industrial Applicability
The invention is industrially applicable. A low leakage charge storage circuit of the invention is suitable for use in, for example, an active matrix display or a DRAM.
| Number | Date | Country | Kind |
|---|---|---|---|
| 1009480.3 | Jun 2010 | GB | national |
| Number | Name | Date | Kind |
|---|---|---|---|
| 4623908 | Oshima et al. | Nov 1986 | A |
| 5296847 | Takeda et al. | Mar 1994 | A |
| 5650636 | Takemura et al. | Jul 1997 | A |
| 5903249 | Koyama et al. | May 1999 | A |
| 6064362 | Brownlow et al. | May 2000 | A |
| 6278428 | Smith et al. | Aug 2001 | B1 |
| 7573451 | Tobita | Aug 2009 | B2 |
| 8816347 | Yamazaki et al. | Aug 2014 | B2 |
| 20030142052 | Matsumoto | Jul 2003 | A1 |
| 20080291351 | Han et al. | Nov 2008 | A1 |
| 20090289876 | Chun | Nov 2009 | A1 |
| Number | Date | Country |
|---|---|---|
| 0 336 570 | Oct 1989 | EP |
| 0 807 918 | Nov 1997 | EP |
| 2 101 437 | Jan 1983 | GB |
| 05-142573 | Jun 1993 | JP |
| 2000-010072 | Jan 2000 | JP |
| Entry |
|---|
| European Search Report for corresponding European Application No. EP 11168815.6 dated Sep. 12, 2011. |
| Willem den Boer; “Active Matrix Liquid Crystal Displays”; Elsevier; 2005. |
| British Search Report for corresponding British Application No. GB1009480.3 dated Sep. 9, 2010. |
| Tsunashima et al., “Novel Gamma Correction Method Using an Advanced Capacitive Coupling Driving”, SID 07 Digest, pp. 1014-1017, ISSN/007-0966X/07/3802. |
| Number | Date | Country | |
|---|---|---|---|
| 20110298531 A1 | Dec 2011 | US |
