Charging Method, Terminal Device, and Power Supply Device

Abstract

A charging method includes the follows. A battery of a terminal device is determined to be charged in a charging mode based on that current status of the terminal device satisfies a condition that the battery of the terminal device is operable to be charged in the charging mode. A communication with the terminal device is conducted to determine a charging voltage or a charging current of the charging mode. An output voltage or output current output to the terminal device is adjusted to enter a constant current phase. A communication with the terminal device is conducted during the constant current phase to receive information of a current voltage of the battery. The output current output to the terminal device is adjusted according to the current voltage of the battery in the constant current phase. A related terminal device and power supply device are also provided.

Description

TECHNICAL FIELD

Implementations of the present disclosure relates to charging field, and more particularly to a charging method, a terminal device, and a power supply device.

BACKGROUND

Terminal devices (e.g., smart phones) become more and more popular with consumers. However, the power consumption of terminal devices is great, thus terminal devices need to be charged regularly. As the battery capacity of terminal devices becomes greater and greater, correspondingly, the charging time becomes longer. How to realize quick charging is a problem that may be needed to be solved.

In order to achieve the purpose of quick charging, the output current of a power supply device may be directly increased without consideration of endurance of a terminal device, as such, a phenomenon of the heating and even burnout of the terminal device may occur, which may reduce the lifespan of the terminal device.

SUMMARY

In the present disclosure, a charging method, a power supply device, and a terminal device are provided.

In a first aspect, a charging method is provided. The method includes the follows. A battery of a terminal device is determined to be charged in a charging mode based on that current status of the terminal device satisfies a condition that the battery of the terminal device is operable to be charged in the charging mode by a power supply device. A communication is conducted with the power supply device to determine a charging voltage or a charging current of the charging mode. A communication is conducted with the power supply device to transmit information of a current voltage of the battery to the power supply device after the power supply device adjusts an output voltage or output current of the power supply device according to the charging voltage or the charging current of the charging mode and enters a constant current phase, so as to cause the power supply device to adjust the output current according to the current voltage of the battery.

In a second aspect, a charging method is provided. The method includes the follows. A battery of a terminal device is determined to be charged in a charging mode based on that current status of the terminal device satisfies a condition that the battery of the terminal device is operable to be charged in the charging mode. A communication with the terminal device is conducted to determine a charging voltage or a charging current of the charging mode. An output voltage or output current output to the terminal device is adjusted according to the charging voltage or the charging current of the charging mode to enter a constant current phase. A communication with the terminal device is conducted during the constant current phase to receive information of a current voltage of the battery. The output current output to the terminal device is adjusted according to the current voltage of the battery in the constant current phase.

In a third aspect, a power supply device is provided. The power supply device includes at least one processor and a computer readable memory coupled to the at least one processor and storing at least one computer executable instruction therein which, when executed by the at least one processor, causes the at least one processor to perform following acts. A battery of a terminal device is determined to be charged in a charging mode based on that current status of the terminal device satisfies a condition that the battery of the terminal device is operable to be charged in the charging mode. A communication with the terminal device is conducted to determine a charging voltage or a charging current of the charging mode. An output voltage or output current output to the terminal device is adjusted according to the charging voltage or the charging current of the charging mode to enter a constant current phase. A communication with the terminal device is conducted during the constant current phase to receive information of a current voltage of the battery. The output current output to the terminal device is adjusted according to the current voltage of the battery in the constant current phase.

BRIEF DESCRIPTION OF THE DRAWINGS

To better illustrate the technical solution of implementations of the present disclosure, the following descriptions will briefly illustrate the accompanying drawings described in the implementations. Obviously, the following described accompanying drawings are some implementations of the present disclosure. Those skilled in the art can obtain other accompanying drawings according to the described accompanying drawings without creative work.

FIG. 1 is a schematic diagram illustrating a charging process in accordance with an implementation of the present disclosure.

FIG. 2 is a schematic diagram illustrating that a power supply device implements a data reception and transmission in accordance with an implementation of the present disclosure.

FIG. 3 is a schematic diagram illustrating a communication sequence of a power supply device in accordance with an implementation of the present disclosure.

FIG. 4 is a schematic diagram illustrating a communication sequence of a power supply device in accordance with an implementation of the present disclosure.

FIG. 5 is a schematic diagram illustrating a charging method in accordance with an implementation of the present disclosure.

FIG. 6 is a schematic diagram illustrating a terminal device in accordance with an implementation of the present disclosure.

FIG. 7 is a schematic diagram illustrating a power supply device in accordance with an implementation of the present disclosure.

DETAILED DESCRIPTION

In combination with the first aspect, in an implementation manner of the first aspect, the first instruction further indicates path impedance of the terminal device, the path impedance of the terminal device is configured for the power supply device to determine whether the USB interface is in good contact, or whether impedance of a charge circuit between the power supply device and the terminal device is abnormal.

In combination with the first aspect or any of the above implementation manners, in another implementation manner of the first aspect, a format of the first instruction is 101000YYYYY0, Y indicates 1 bit, and the path impedance of the terminal device equals to YYYYY*5mΩ.

In combination with the first aspect or any of the above implementation manners, in another implementation manner of the first aspect, the method further comprises: receiving, by the terminal device, a reply instruction of the first instruction from the power supply device, wherein the reply instruction of the first instruction indicates that the power supply device supports the quick charging mode, or indicates that the power supply device agrees to charge the battery in the quick charging mode.

In combination with the first aspect or any of the above implementation manners, in another implementation manner of the first aspect, a format of the reply instruction of the first instruction is 101XX, X indicates 1 bit, XX=01 indicates that the power supply device has received the first instruction, and when XX is any value except 01, it indicates that the communication between the terminal device and the power supply device becomes abnormal.

In combination with the first aspect or any of the above implementation manners, in another implementation manner of the first aspect, communicating, by the terminal device, with the power supply device to determine the charging voltage of the quick charging mode comprises: transmitting, by the terminal device, a second instruction to the power supply device, wherein the second instruction indicates that the output voltage of the power supply device is high, low, or proper; and receiving, by the terminal device, a reply instruction of the second instruction from the power supply device, wherein the reply instruction of the second instruction indicates that the power supply device has received the second instruction.

Optionally, the second instruction can indicate a current voltage of the battery, so as to cause the power supply device to directly determine the output voltage according to the current voltage of the battery.

In combination with the first aspect or any of the above implementation manners, in another implementation manner of the first aspect, a format of the second instruction is 101001000YY0, Y indicates 1 bit, YY=11 indicates that the output voltage of the power supply device is proper, YY=10 indicates that the output voltage of the power supply device is high, YY=01 indicates that the output voltage of the power supply device is low, and YY=00 indicates that the communication between the terminal device and the power supply device becomes abnormal.

In combination with the first aspect or any of the above implementation manners, in another implementation manner of the first aspect, a format of the reply instruction of the second instruction is 101XX, X indicates 1 bit, XX=01 indicates that the power supply device has received the second instruction, and when XX is any value except 01, it indicates that the communication between the terminal device and the power supply device becomes abnormal.

In combination with the first aspect or any of the above implementation manners, in another implementation manner of the first aspect, communicating, by the terminal device, with the power supply device to determine the charging current of the quick charging mode comprises: transmitting, by the terminal device, a third instruction to the power supply device, wherein the third instruction indicates a maximum charging current currently supported by the terminal device; and receiving, by the terminal device, a reply instruction of the third instruction from the power supply device, wherein the reply instruction of the third instruction indicates that the power supply device has received the third instruction, or the third instruction indicates that the terminal device is ready to enter the constant current phase.

In combination with the first aspect or any of the above implementation manners, in another implementation manner of the first aspect, a format of the third instruction is 101010YYY000, Y indicates 1 bit, and the maximum charging current currently supported by the terminal device equals to 3000+(YYY*250) mA.

In combination with the first aspect or any of the above implementation manners, in another implementation manner of the first aspect, a format of the reply instruction of the third instruction is 101XX, X indicates 1 bit, XX=01 indicates that the power supply device has received the third instruction, and when XX is any value except 01, it indicates that the communication between the terminal device and the power supply device becomes abnormal.

In combination with the first aspect or any of the above implementation manners, in another implementation manner of the first aspect, communicating, by the terminal device, with the power supply device to constantly transmit the information of the voltage of the battery to the power supply device comprises: transmitting, by the terminal device, a fourth instruction to the power supply device, wherein the fourth instruction indicates the voltage of the battery; and receiving, by the terminal device, a reply instruction of the fourth instruction from the power supply device, wherein the reply instruction of the fourth instruction indicates that the power supply device has received the fourth instruction.

In combination with the first aspect or any of the above implementation manners, in another implementation manner of the first aspect, a format of the fourth instruction is 101011YYYYYY, Y indicates 1 bit, and the voltage of the battery equals 3404+(YYYYYY*16) mV.

In combination with the first aspect or any of the above implementation manners, in another implementation manner of the first aspect, the reply instruction of the fourth instruction further indicates that the USB interface is in bad contact, or indicates that the impedance of the charge circuit between the power supply device and the terminal device is abnormal, and is ready to exit the quick charging mode, or indicates that the quick charging communication process needs to be reactivated.

In combination with the first aspect or any of the above implementation manners, in another implementation manner of the first aspect, a format of the reply instruction of the fourth instruction is 101XX, X indicates 1 bit, XX=01 indicates that the power supply device has received the fourth instruction, XX=11 indicates that the USB interface is in bad contact, or indicates that the impedance of the charge circuit between the power supply device and the terminal device is abnormal, and is ready to exit the quick charging mode, or indicates that the quick charging communication process needs to be reactivated, and when XX is any value except 01 and 11, it indicates that the communication between terminal device and the power supply device becomes abnormal.

In combination with the first aspect or any of the above implementation manners, in another implementation manner of the first aspect, the method further comprises: transmitting, by the terminal device, a fifth instruction to the power supply device, wherein the fifth instruction indicates a maximum voltage of the battery; and receiving, by the terminal device, a reply instruction of the fifth instruction from the power supply device, wherein the reply instruction of the fifth instruction indicates that the power supply device has received the fifth instruction.

In combination with the first aspect or any of the above implementation manners, in another implementation manner of the first aspect, a format of the fifth instruction is 101100YYYYYY, Y indicates 1 bit, and the maximum voltage of the battery is 4100+YYYYYY*10 mV.

In combination with the first aspect or any of the above implementation manners, in another implementation manner of the first aspect, a format of the reply instruction of the fifth instruction is 101XX, X indicates 1 bit, XX=01 indicates that the power supply device has received the fifth instruction, and when XX is any value except 01, it indicates that the communication between the terminal device and the power supply device becomes abnormal.

In combination with the first aspect or any of the above implementation manners, in another implementation manner of the first aspect, the method further comprises: executing, by the terminal device, at least one of following operations when the communication between the power supply device and the terminal device becomes abnormal, wherein the following operations comprise: exiting the quick charging mode, charging the battery in the normal charging mode, stopping charging, or reactivating the quick charging communication process.

In combination with the first aspect or any of the above implementation manners, in another implementation manner of the first aspect, an instruction transmitted from the terminal device to the power supply device comprises multiple bits, when the terminal device transmits any instruction, the terminal device firstly transmits a most significant bit (MSB) of the multiple bits of the any instruction; or an instruction received from the power supply device by the terminal device comprises multiple bits, when the terminal device receives an instruction, the terminal device firstly receives a MSB of the multiple bits of the instruction.

In combination with the first aspect or any of the above implementation manners, in another implementation manner of the first aspect, clock signals used in the communication between the power supply device and the terminal device are provided by the power supply device.

In combination with the first aspect or any of the above implementation manners, in another implementation manner of the first aspect, an instruction transmitted from the power supply device to the terminal device comprises multiple bits, during a process of transmitting each of the multiple bits, the power supply device firstly transmits each bit, and then transmits a clock interrupt signal; or a reply instruction received from the terminal device by the power supply device comprises multiple bits, during a process of receiving each of the multiple bits, the power supply device firstly transmits the clock interrupt signal, and then receives each bit after a preset time interval.

In combination with the first aspect or any of the above implementation manners, in another implementation manner of the first aspect, each instruction received from the terminal device by the power supply device comprises a 12-bit data, the power supply device receives the 12-bit data from the terminal device via twelve continuous clock periods of the clock signal, level of previous 500 μs of each of the twelve continuous clock periods is high, and level of latter 10 μs of each of the twelve continuous clock periods is low; or each instruction transmitted from the power supply device to the terminal device comprises a 5-bit data, the power supply device transmits the 5-bit data to the terminal device via five continuous clock periods of the clock signal, level of previous 10 μs of each of the five continuous clock periods is low, and level of latter 500 μs of each of the five continuous clock periods is high.

In combination with the first aspect or any of the above implementation manners, in another implementation manner of the first aspect, during a process that the power supply device receives an instruction from the terminal device, a minimum value of high level of the clock signal used between the power supply device and the terminal device equals to VDD of the power supply device minus 0.7V; or during the process that the power supply device receives an instruction from the terminal device, a maximum value of low level of the clock signal used between the power supply device and the terminal device is 0.8V; or during a process that the power supply device transmits an instruction to the terminal device, a minimum value of high level of the clock signal used between the power supply device and the terminal device equals to 0.25VDD+0.8V; or during the process that the power supply device transmits an instruction to the terminal device, a maximum value of the high level of the clock signal used between the power supply device and the terminal device is 4.5V; or during the process that the power supply device transmits an instruction to the terminal device, a maximum value of low level of the clock signal used between the power supply device and the terminal device is 0.15VDD. The VDD is a work voltage of the power supply device, and/or the VDD is greater than 3.2V and less than 4.5V.

In combination with the second aspect, in an implementation manner of the second aspect, the first instruction further indicates path impedance of the terminal device, the path impedance of the terminal device is configured for the power supply device to determine whether the USB interface is in good contact, or to determine whether impedance of a charge circuit between the power supply device and the terminal device is abnormal.

In combination with the second aspect or any of the above implementation manners, in another implementation manner of the second aspect, a format of the first instruction is 101000YYYYY0, Y indicates 1 bit, and the path impedance of the terminal device equals to YYYYY*5mΩ.

In combination with the second aspect or any of the above implementation manners, in another implementation manner of the second aspect, the method further comprises: transmitting, by the power supply device, a reply instruction of the first instruction to the terminal device, wherein the reply instruction of the first instruction indicates that the power supply device supports the quick charging mode, or indicates that the power supply device agrees to charge the battery in the quick charging mode.

In combination with the second aspect or any of the above implementation manners, in another implementation manner of the second aspect, a format of the reply instruction of the first instruction is 101XX, X indicates 1 bit, XX=01 indicates that the power supply device has received the first instruction, and when XX is any value except 01, it indicates that the communication between the terminal device and the power supply device becomes abnormal.

In combination with the second aspect or any of the above implementation manners, in another implementation manner of the second aspect, communicating, by the power supply device, with the terminal device to determine the charging voltage of the quick charging mode comprises: receiving, by the power supply device, a second instruction from the terminal device, wherein the second instruction indicates that the output voltage of the power supply device is high, low, or proper; and transmitting, by the power supply device, a reply instruction of the second instruction to the terminal device, wherein the reply instruction of the second instruction indicates that the power supply device has received the second instruction.

In combination with the second aspect or any of the above implementation manners, in another implementation manner of the second aspect, a format of the second instruction is 101001000YY0, Y indicates 1 bit, YY=11 indicates that the output voltage of the power supply device is proper, YY=10 indicates that the output voltage of the power supply device is high, YY=01 indicates that the output voltage of the power supply device is low, and YY=00 indicates that the communication between the terminal device and the power supply device becomes abnormal.

In combination with the second aspect or any of the above implementation manners, in another implementation manner of the second aspect, a format of the reply instruction of the second instruction is 101XX, X indicates 1 bit, XX=01 indicates that the power supply device has received the second instruction, and when XX is any value except 01, it indicates that the communication between the terminal device and the power supply device becomes abnormal.

In combination with the second aspect or any of the above implementation manners, in another implementation manner of the second aspect, communicating, by the power supply device, with the terminal device to determine the charging current of the quick charging mode comprises: receiving, by the power supply device, a third instruction from the terminal device, wherein the third instruction indicates a maximum charging current currently supported by the terminal device; and transmitting, by the power supply device, a reply instruction of the third instruction to the terminal device, wherein the reply instruction of the third instruction indicates that the power supply device has received the third instruction, or the third instruction indicates that the terminal device is ready to enter the constant current phase.

In combination with the second aspect or any of the above implementation manners, in another implementation manner of the second aspect, a format of the third instruction is 101010YYY000, Y indicates 1 bit, and the maximum charging current currently supported by the terminal device equals to 3000+(YYY*250) mA.

In combination with the second aspect or any of the above implementation manners, in another implementation manner of the second aspect, a format of the reply instruction of the third instruction is 101XX, X indicates 1 bit, XX=01 indicates that the power supply device has received the third instruction, and when XX is any value except 01, it indicates that the communication between the terminal device and the power supply device becomes abnormal.

In combination with the second aspect or any of the above implementation manners, in another implementation manner of the second aspect, communicating, by the power supply device, with the terminal device to constantly receive the information of the voltage of the battery from the terminal device comprises: receiving, by the power supply device, a fourth instruction from the terminal device, wherein the fourth instruction indicates the voltage of the battery; and transmitting, by the power supply device, a reply instruction of the fourth instruction to the terminal device, wherein the reply instruction of the fourth instruction indicates that the power supply device has received the fourth instruction.

In combination with the second aspect or any of the above implementation manners, in another implementation manner of the second aspect, a format of the fourth instruction is 101011YYYYYY, Y indicates 1 bit, and the voltage of the battery equals 3404+(YYYYYY*16) mV.

In combination with the second aspect or any of the above implementation manners, in another implementation manner of the second aspect, the reply instruction of the fourth instruction further indicates that the USB interface is in bad contact, or indicates that the impedance of the charge circuit between the power supply device and the terminal device is abnormal, and is ready to exit the quick charging mode, or indicates that the quick charging communication process needs to be reactivated.

In combination with the second aspect or any of the above implementation manners, in another implementation manner of the second aspect, a format of the reply instruction of the fourth instruction is 101XX, X indicates 1 bit, XX=01 indicates that the power supply device has received the fourth instruction, XX=11 indicates that the USB interface is in bad contact, or indicates that the impedance of the charge circuit between the power supply device and the terminal device is abnormal, and is ready to exit the quick charging mode, or indicates that the quick charging communication process needs to be reactivated, and when XX is any value except 01 and 11, it indicates that the communication between terminal device and the power supply device becomes abnormal.

In combination with the second aspect or any of the above implementation manners, in another implementation manner of the second aspect, the method further comprises: receiving, by the power supply device, a fifth instruction from the terminal device, wherein the fifth instruction indicates a maximum voltage of the battery; and transmitting, by the power supply device, a reply instruction of the fifth instruction to the terminal device, wherein the reply instruction of the fifth instruction indicates that the power supply device has received the fifth instruction.

In combination with the second aspect or any of the above implementation manners, in another implementation manner of the second aspect, a format of the fifth instruction is 101100YYYYYY, Y indicates 1 bit, and the maximum voltage of the battery is 4100+YYYYYY*10 mV.

In combination with the second aspect or any of the above implementation manners, in another implementation manner of the second aspect, a format of the reply instruction of the fifth instruction is 101XX, X indicates 1 bit, XX=01 indicates that the power supply device has received the fifth instruction, and when XX is any value except 01, it indicates that the communication between the terminal device and the power supply device becomes abnormal.

In combination with the second aspect or any of the above implementation manners, in another implementation manner of the second aspect, the method further comprises: executing, by the power supply device, at least one of following operations when the communication between the power supply device and the terminal device becomes abnormal, wherein the following operations comprise: exiting the quick charging mode, charging the battery in the normal charging mode, stopping charging, or reactivating the quick charging communication process.

In combination with the second aspect or any of the above implementation manners, in another implementation manner of the second aspect, an instruction received from the terminal device by the power supply device comprises multiple bits, when the power supply device receives any instruction, the power supply device firstly receives a MSB of the multiple bits of the any instruction; or an instruction transmitted from the power supply device to the terminal device comprises multiple bits, when the power supply device transmits an instruction, the power supply device firstly transmits a MSB of the multiple bits of the instruction.

In combination with the second aspect or any of the above implementation manners, in another implementation manner of the second aspect, clock signals used in the communication between the power supply device and the terminal device are provided by the power supply device.

In combination with the second aspect or any of the above implementation manners, in another implementation manner of the second aspect, an instruction transmitted from the power supply device to the terminal device comprises multiple bits, during a process of transmitting each of the multiple bits, the power supply device firstly transmits each bit, and then transmits a clock interrupt signal; or a reply instruction received from the terminal device by the power supply device comprises multiple bits, during a process of receiving each of the multiple bits, the power supply device firstly transmits the clock interrupt signal, and then receives each bit after a preset time interval.

In combination with the second aspect or any of the above implementation manners, in another implementation manner of the second aspect, each instruction received from the terminal device by the power supply device comprises a 12-bit data, the power supply device receives the 12-bit data from the terminal device via twelve continuous clock periods of the clock signal, level of previous 500 μs of each of the twelve continuous clock periods is high, and level of latter 10 μs of each of the twelve continuous clock periods is low; or each reply instruction transmitted from the power supply device to the terminal device comprises a 5-bit data, the power supply device transmits the 5-bit data to the terminal device via five continuous clock periods of the clock signal, level of previous 10 μs of each of the five continuous clock periods is low, and level of latter 500 μs of each of the five continuous clock periods is high.

In combination with the second aspect or any of the above implementation manners, in another implementation manner of the second aspect, during a process that the power supply device receives an instruction from the terminal device, a minimum value of high level of the clock signal used between the power supply device and the terminal device equals to VDD of the power supply device minus 0.7V; or during the process that the power supply device receives an instruction from the terminal device, a maximum value of low level of the clock signal used between the power supply device and the terminal device is 0.8V; or during a process that the power supply device transmits an instruction to the terminal device, a minimum value of high level of the clock signal used between the power supply device and the terminal device equals to 0.25VDD+0.8V; or during the process that the power supply device transmits an instruction to the terminal device, a maximum value of the high level of the clock signal used between the power supply device and the terminal device is 4.5V; or during the process that the power supply device transmits an instruction to the terminal device, a maximum value of low level of the clock signal is 0.15VDD. The VDD is a work voltage of the power supply device, and/or the VDD is greater than 3.2V and less than 4.5V.

In combination with the third aspect, in an implementation manner of the third aspect, the first instruction further indicates path impedance of the terminal device, the path impedance of the terminal device is configured for the power supply device to determine whether the USB interface is in good contact, or to determine whether impedance of a charge circuit between the power supply device and the terminal device is abnormal.

In combination with the third aspect or any of the above implementation manners, in another implementation manner of the third aspect, a format of the first instruction is 101000YYYYY0, Y indicates 1 bit, and the path impedance of the terminal device equals to YYYYY*5mΩ.

In combination with the third aspect or any of the above implementation manners, in another implementation manner of the third aspect, the communication control circuit is further configured to receive a reply instruction of the first instruction from the power supply device, and the reply instruction of the first instruction indicates that the power supply device supports the quick charging mode, or indicates that the power supply device agrees to charge the battery in the quick charging mode.

In combination with the third aspect or any of the above implementation manners, in another implementation manner of the third aspect, a format of the reply instruction of the first instruction is 101XX, X indicates 1 bit, XX=01 indicates that the power supply device has received the first instruction, and when XX is any value except 01, it indicates that the communication between the terminal device and the power supply device becomes abnormal.

In combination with the third aspect or any of the above implementation manners, in another implementation manner of the third aspect, the communication control circuit is configured to transmit a second instruction to the power supply device, and the second instruction indicates that the output voltage of the power supply device is high, low, or proper. The communication control circuit is configured to receive a reply instruction of the second instruction, and the reply instruction of the second instruction indicates that the power supply device has received the second instruction.

In combination with the third aspect or any of the above implementation manners, in another implementation manner of the third aspect, a format of the second instruction is 101001000YY0, Y indicates 1 bit, YY=11 indicates that the output voltage of the power supply device is proper, YY=10 indicates that the output voltage of the power supply device is high, YY=01 indicates that the output voltage of the power supply device is low, and YY=00 indicates that the communication between the terminal device and the power supply device becomes abnormal.

In combination with the third aspect or any of the above implementation manners, in another implementation manner of the third aspect, a format of the reply instruction of the second instruction is 101XX, X indicates 1 bit, XX=01 indicates that the power supply device has received the second instruction, and when XX is any value except 01, it indicates that the communication between the terminal device and the power supply device becomes abnormal.

In combination with the third aspect or any of the above implementation manners, in another implementation manner of the third aspect, the communication control circuit is configured to transmit a third instruction to the power supply device, and the third instruction indicates a maximum charging current currently supported by the terminal device. The communication control circuit is configured to receive a reply instruction of the third instruction from the power supply device, and the reply instruction of the third instruction indicates that the power supply device has received the third instruction, or the third instruction indicates that the terminal device is ready to enter the constant current phase.

In combination with the third aspect or any of the above implementation manners, in another implementation manner of the third aspect, a format of the third instruction is 101010YYY000, Y indicates 1 bit, and the maximum charging current currently supported by the terminal device equals to 3000+(YYY*250) mA.

In combination with the third aspect or any of the above implementation manners, in another implementation manner of the third aspect, a format of the reply instruction of the third instruction is 101XX, X indicates 1 bit, XX=01 indicates that the power supply device has received the third instruction, and when XX is any value except 01, it indicates that the communication between the terminal device and the power supply device becomes abnormal.

In combination with the third aspect or any of the above implementation manners, in another implementation manner of the third aspect, the communication control circuit is configured to constantly transmit a fourth instruction to the power supply device, and the fourth instruction indicates the voltage of the battery. The communication control circuit is configured to receive a reply instruction of the fourth instruction from the power supply device, and the reply instruction of the fourth instruction indicates that the power supply device has received the fourth instruction.

In combination with the third aspect or any of the above implementation manners, in another implementation manner of the third aspect, a format of the fourth instruction is 101011YYYYYY, Y indicates 1 bit, and the voltage of the battery equals 3404+(YYYYYY*16) mV.

In combination with the third aspect or any of the above implementation manners, in another implementation manner of the third aspect, the reply instruction of the fourth instruction further indicates that the USB interface is in bad contact, or indicates that the impedance of the charge circuit between the power supply device and the terminal device is abnormal, and is ready to exit the quick charging mode, or indicates that the quick charging communication process needs to be reactivated.

In combination with the third aspect or any of the above implementation manners, in another implementation manner of the third aspect, a format of the reply instruction of the fourth instruction is 101XX, X indicates 1 bit, XX=01 indicates that the power supply device has received the fourth instruction, XX=11 indicates that the USB interface is in bad contact, or indicates that the impedance of the charge circuit between the power supply device and the terminal device is abnormal, and is ready to exit the quick charging mode, or indicates that the quick charging communication process needs to be reactivated, and when XX is any value except 01 and 11, it indicates that the communication between terminal device and the power supply device becomes abnormal.

In combination with the third aspect or any of the above implementation manners, in another implementation manner of the third aspect, the communication control circuit is further configured to transmit a fifth instruction to the power supply device, and the fifth instruction indicates a maximum voltage of the battery. The communication control circuit is further configured to receive a reply instruction of the fifth instruction, and the reply instruction of the fifth instruction indicates that the power supply device has received the fifth instruction.

In combination with the third aspect or any of the above implementation manners, in another implementation manner of the third aspect, a format of the fifth instruction is 101100YYYYYY, Y indicates 1 bit, and the maximum voltage of the battery is 4100+YYYYYY*10 mV.

In combination with the third aspect or any of the above implementation manners, in another implementation manner of the third aspect, a format of the reply instruction of the fifth instruction is 101XX, X indicates 1 bit, XX=01 indicates that the power supply device has received the fifth instruction, and when XX is any value except 01, it indicates that the communication between the terminal device and the power supply device becomes abnormal.

In combination with the third aspect or any of the above implementation manners, in another implementation manner of the third aspect, the communication control circuit is further configured to execute at least one of following operations when the communication between the power supply device and the terminal device becomes abnormal, and the following operations comprise: exiting the quick charging mode, charging the battery in the normal charging mode, stopping charging, or reactivating the quick charging communication process.

In combination with the third aspect or any of the above implementation manners, in another implementation manner of the third aspect, an instruction transmitted from the terminal device to the power supply device comprises multiple bits, when the terminal device transmits any instruction, the terminal device firstly transmits a most significant bit (MSB) of the multiple bits of the any instruction; or an instruction received from the power supply device by the terminal device comprises multiple bits, when the terminal device receives an instruction, the terminal device firstly receives a MSB of the multiple bits of the instruction.

In combination with the third aspect or any of the above implementation manners, in another implementation manner of the third aspect, clock signals used in the communication between the power supply device and the terminal device are provided by the power supply device.

In combination with the third aspect or any of the above implementation manners, in another implementation manner of the third aspect, an instruction transmitted from the power supply device to the terminal device comprises multiple bits, during a process of transmitting each of the multiple bits, the power supply device firstly transmits each bit, and then transmits a clock interrupt signal; or a reply instruction received from the terminal device by the power supply device comprises multiple bits, during a process of receiving each of the multiple bits, the power supply device firstly transmits the clock interrupt signal, and then receives each bit after a preset time interval.

In combination with the third aspect or any of the above implementation manners, in another implementation manner of the third aspect, each instruction received from the terminal device by the power supply device comprises a 12-bit data, the power supply device receives the 12-bit data from the terminal device via twelve continuous clock periods of the clock signal, level of previous 500 μs of each of the twelve continuous clock periods is high, and level of latter 10 μs of each of the twelve continuous clock periods is low; or each reply instruction transmitted from the power supply device to the terminal device comprises a 5-bit data, the power supply device transmits the 5-bit data to the terminal device via five continuous clock periods of the clock signal, level of previous 10 μs of each of the five continuous clock periods is low, and level of latter 500 μs of each of the five continuous clock periods is high.

In combination with the third aspect or any of the above implementation manners, in another implementation manner of the third aspect, during a process that the power supply device receives an instruction from the terminal device, a minimum value of high level of the clock signal used between the power supply device and the terminal device equals to VDD of the power supply device minus 0.7V; or during the process that the power supply device receives an instruction from the terminal device, a maximum value of low level of the clock signal used between the power supply device and the terminal device is 0.8V; or during a process that the power supply device transmits an instruction to the terminal device, a minimum value of high level of the clock signal used between the power supply device and the terminal device equals to 0.25VDD+0.8V; or during the process that the power supply device transmits an instruction to the terminal device, a maximum value of the high level of the clock signal used between the power supply device and the terminal device is 4.5V; or during the process that the power supply device transmits an instruction to the terminal device, a maximum value of low level of the clock signal is 0.15VDD. The VDD is a work voltage of the power supply device, and/or the VDD is greater than 3.2V and less than 4.5V.

In combination with the fourth aspect, in an implementation manner of the fourth aspect, the first instruction further indicates path impedance of the terminal device, the path impedance of the terminal device is configured for the power supply device to determine whether the USB interface is in good contact, or to determine whether impedance of a charge circuit between the power supply device and the terminal device is abnormal.

In combination with the fourth aspect or any of the above implementation manners, in another implementation manner of the fourth aspect, a format of the first instruction is 101000YYYYY0, Y indicates 1 bit, and the path impedance of the terminal device equals to YYYYY*5mΩ.

In combination with the fourth aspect or any of the above implementation manners, in another implementation manner of the fourth aspect, the communication control circuit is further configured to transmit a reply instruction of the first instruction to the terminal device, and the reply instruction of the first instruction indicates that the power supply device supports the quick charging mode, or indicates that the power supply device agrees to charge the battery in the quick charging mode.

In combination with the fourth aspect or any of the above implementation manners, in another implementation manner of the fourth aspect, a format of the reply instruction of the first instruction is 101XX, X indicates 1 bit, XX=01 indicates that the power supply device has received the first instruction, and when XX is any value except 01, it indicates that the communication between the terminal device and the power supply device becomes abnormal.

In combination with the fourth aspect or any of the above implementation manners, in another implementation manner of the fourth aspect, the communication control circuit is configured to receive a second instruction from the terminal device, and the second instruction indicates that the output voltage of the power supply device is high, low, or proper. The communication control circuit is configured to transmit a reply instruction of the second instruction to the terminal device, and the reply instruction of the second instruction indicates that the power supply device has received the second instruction.

In combination with the fourth aspect or any of the above implementation manners, in another implementation manner of the fourth aspect, a format of the second instruction is 101001000YY0, Y indicates 1 bit, YY=11 indicates that the output voltage of the power supply device is proper, YY=10 indicates that the output voltage of the power supply device is high, YY=01 indicates that the output voltage of the power supply device is low, and YY=00 indicates that the communication between the terminal device and the power supply device becomes abnormal.

In combination with the fourth aspect or any of the above implementation manners, in another implementation manner of the fourth aspect, a format of the reply instruction of the second instruction is 101XX, X indicates 1 bit, XX=01 indicates that the power supply device has received the second instruction, and when XX is any value except 01, it indicates that the communication between the terminal device and the power supply device becomes abnormal.

In combination with the fourth aspect or any of the above implementation manners, in another implementation manner of the fourth aspect, the communication control circuit is configured to receive a third instruction from the terminal device, and the third instruction indicates a maximum charging current currently supported by the terminal device. The communication control circuit is configured to transmit a reply instruction of the third instruction to the terminal device, and the reply instruction of the third instruction indicates that the power supply device has received the third instruction, or the third instruction indicates that the terminal device is ready to enter the constant current phase.

In combination with the fourth aspect or any of the above implementation manners, in another implementation manner of the fourth aspect, a format of the third instruction is 101010YYY000, Y indicates 1 bit, and the maximum charging current currently supported by the terminal device equals to 3000+(YYY*250) mA.

In combination with the fourth aspect or any of the above implementation manners, in another implementation manner of the fourth aspect, a format of the reply instruction of the third instruction is 101XX, X indicates 1 bit, XX=01 indicates that the power supply device has received the third instruction, and when XX is any value except 01, it indicates that the communication between the terminal device and the power supply device becomes abnormal.

In combination with the fourth aspect or any of the above implementation manners, in another implementation manner of the fourth aspect, the communication control circuit is configured to constantly receive a fourth instruction from the terminal device, and the fourth instruction indicates the voltage of the battery. The communication control circuit is configured to transmit a reply instruction of the fourth instruction to the terminal device, and the reply instruction of the fourth instruction indicates that the power supply device has received the fourth instruction.

In combination with the fourth aspect or any of the above implementation manners, in another implementation manner of the fourth aspect, a format of the fourth instruction is 101011YYYYYY, Y indicates 1 bit, and the voltage of the battery equals 3404+(YYYYYY*16) mV.

In combination with the fourth aspect or any of the above implementation manners, in another implementation manner of the fourth aspect, the reply instruction of the fourth instruction further indicates that the USB interface is in bad contact, or indicates that the impedance of the charge circuit between the power supply device and the terminal device is abnormal, and is ready to exit the quick charging mode, or indicates that the quick charging communication process needs to be reactivated.

In combination with the fourth aspect or any of the above implementation manners, in another implementation manner of the fourth aspect, a format of the reply instruction of the fourth instruction is 101XX, X indicates 1 bit, XX=01 indicates that the power supply device has received the fourth instruction, XX=11 indicates that the USB interface is in bad contact, or indicates that the impedance of the charge circuit between the power supply device and the terminal device is abnormal, and is ready to exit the quick charging mode, or indicates that the quick charging communication process needs to be reactivated, and when XX is any value except 01 and 11, it indicates that the communication between terminal device and the power supply device becomes abnormal.

In combination with the fourth aspect or any of the above implementation manners, in another implementation manner of the fourth aspect, the communication control circuit is further configured to receive a fifth instruction from the terminal device, and the fifth instruction indicates a maximum voltage of the battery. The communication control circuit is further configured to transmit a reply instruction of the fifth instruction to the terminal device, and the reply instruction of the fifth instruction indicates that the power supply device has received the fifth instruction.

In combination with the fourth aspect or any of the above implementation manners, in another implementation manner of the fourth aspect, a format of the fifth instruction is 101100YYYYYY, Y indicates 1 bit, and the maximum voltage of the battery is 4100+YYYYYY*10 mV.

In combination with the fourth aspect or any of the above implementation manners, in another implementation manner of the fourth aspect, a format of the reply instruction of the fifth instruction is 101XX, X indicates 1 bit, XX=01 indicates that the power supply device has received the fifth instruction, and when XX is any value except 01, it indicates that the communication between the terminal device and the power supply device becomes abnormal.

In combination with the fourth aspect or any of the above implementation manners, in another implementation manner of the fourth aspect, the communication control circuit is further configured to execute at least one of following operations when the communication between the power supply device and the terminal device becomes abnormal, and the following operations comprise: exiting the quick charging mode, charging the battery in the normal charging mode, stopping charging, or reactivating the quick charging communication process.

In combination with the fourth aspect or any of the above implementation manners, in another implementation manner of the fourth aspect, an instruction received from the terminal device by the power supply device comprises multiple bits, when the power supply device receives any instruction, the power supply device firstly receives a most significant bit (MSB) of the multiple bits of the any instruction; or an instruction transmitted from the power supply device to the terminal device comprises multiple bits, when the power supply device transmits an instruction, the power supply device firstly transmits a MSB of the multiple bits of the instruction.

In combination with the fourth aspect or any of the above implementation manners, in another implementation manner of the fourth aspect, clock signals used in the communication between the power supply device and the terminal device are provided by the power supply device.

In combination with the fourth aspect or any of the above implementation manners, in another implementation manner of the fourth aspect, an instruction transmitted from the power supply device to the terminal device comprises multiple bits, during a process of transmitting each of the multiple bits, the power supply device firstly transmits each bit, and then transmits a clock interrupt signal; or a reply instruction received from the terminal device by the power supply device comprises multiple bits, during a process of receiving each of the multiple bits, the power supply device firstly transmits the clock interrupt signal, and then receives each bit after a preset time interval.

In combination with the fourth aspect or any of the above implementation manners, in another implementation manner of the fourth aspect, each instruction received from the terminal device by the power supply device comprises a 12-bit data, the power supply device receives the 12-bit data from the terminal device via twelve continuous clock periods of the clock signal, level of previous 500 μs of each of the twelve continuous clock periods is high, and level of latter 10 μs of each of the twelve continuous clock periods is low; or each instruction transmitted from the power supply device to the terminal device comprises a 5-bit data, the power supply device transmits the 5-bit data to the terminal device via five continuous clock periods of the clock signal, level of previous 10 μs of each of the five continuous clock periods is low, and level of latter 500 μs of each of the five continuous clock periods is high.

In combination with the fourth aspect or any of the above implementation manners, in another implementation manner of the fourth aspect, during a process that the power supply device receives an instruction from the terminal device, a minimum value of high level of the clock signal used between the power supply device and the terminal device equals to VDD of the power supply device minus 0.7V; or during the process that the power supply device receives an instruction from the terminal device, a maximum value of low level of the clock signal used between the power supply device and the terminal device is 0.8V; or during a process that the power supply device transmits an instruction to the terminal device, a minimum value of high level of the clock signal used between the power supply device and the terminal device equals to 0.25VDD+0.8V; or during the process that the power supply device transmits an instruction to the terminal device, a maximum value of the high level of the clock signal used between the power supply device and the terminal device is 4.5V; or during the process that the power supply device transmits an instruction to the terminal device, a maximum value of low level of the clock signal used between the power supply device and the terminal device is 0.15VDD. The VDD is a work voltage of the power supply device, and/or the VDD is greater than 3.2V and less than 4.5V.

The technical solution of implementations of the present disclosure will be described clearly and completely in combination with the accompanying drawings of the implementations of the present disclosure. Obviously, the described implementations are a part of implementations of the present disclosure, and not all of the implementations. According to the implementations of the present disclosure, other implementations obtained by those skilled in the art without creative work all fall within the protection scope of the present disclosure.

FIG. 1 is a schematic diagram illustrating a charging process in accordance with an implementation of the present disclosure.

As illustrated by FIG. 1, a charging communication process may include five phases. The charging communication process may generally refer to a charging communication process in which a charging mode having a great charging speed is adopted. Hereinafter, for the sake of easy understanding, the charging communication process may be referred as a quick charging communication process. The quick charging communication process may be conducted between a power supply device such as a power adapter and a terminal device such as a mobile phone, a tablet computer and the like.

Phase 1:

A terminal device can detect a type of a power supply device via a positive data (D+) line and a negative data (D−) line. When it is determined that the power supply device is a non-USB charging device, a current absorbed by the terminal device can be greater than a preset current threshold I2. When the power supply device determines that within a preset time length (for example, continuous T1 time length) an output current of the power supply device is greater than or equal to I2, the power supply device determines that the terminal device has recognized the type of the power supply device, and the power supply device activates a handshake communication between the power supply device and the terminal device. The power supply device transmits a first instruction to query whether the terminal device agrees to activate a first charging mode. The terminal device can be charged in the first charging mode and a second charging mode. A charging speed of the first charging mode is greater than that of the second charging mode. That is to say, the time consumed by charging the terminal device in the first charging mode is less than that consumed by charging the terminal device in the second charging mode. Hereinafter, for the sake of easy understanding, the first charging mode may be referred as a quick charging mode, and the second charging mode may be referred as a normal charging mode.

When a reply instruction received from the terminal device by the power supply device indicates that the terminal device disagrees to activate the quick charging mode, the power supply device redetects the output current of the power supply device. When the output current of the power supply device is still greater than or equal to I2, the power supply device retransmits the request to query whether the terminal device is to activate the quick charging mode, and the above steps of the phase 1 are repeated until the terminal device agrees to activate the quick charging mode or the output current of the power supply device is no longer greater than or equal to I2.

When the terminal device agrees to activate quick charging, the quick charging communication process enters a phase 2.

Phase 2:

The power supply device can output different voltage levels. The power supply device transmits a second instruction to the terminal device to query the terminal device for whether an output voltage of the power supply device is proper (that is, whether the output voltage is proper to be a charging voltage of the quick charging mode).

The terminal device transmits a reply to the power supply device to inform the power supply device that the output voltage of the power supply device is high, low, or proper. If the reply the power supply device received from the terminal device indicates that the output voltage of the power supply device is high or low, the power supply device selects another output voltage level, and retransmits the second instruction to the terminal device to re-query the terminal device for whether the output voltage of the power supply device is proper.

The above steps of the phase 2 are repeated until the terminal device returns a reply to the power supply device to inform the power supply device that the output voltage of the power supply device is proper, and the quick charging communication process enters a phase 3.

Phase 3:

The power supply device transmits a third instruction to the terminal device to query a maximum charging current currently supported by the terminal device. The terminal device transmits a reply to the power supply device to inform the power supply device of the maximum charging current currently supported by the terminal device, and the quick charging communication process enters a phase 4.

Phase 4:

The power supply device sets the output current of the power supply device to be the maximum charging current currently supported by the terminal device, and the quick charging communication process enters a constant current phase, that is, a phase 5.

Phase 5:

After entering the constant current phase, the power supply device transmits a fourth instruction every a time interval to query a current voltage of a battery of the terminal device. The terminal device can transmit a reply to the power supply device to inform the power supply device of the current voltage of the battery of the terminal device. The power supply device can determine whether a USB interface is in good contact and whether it is needed to decrease the current charging current value of the terminal device according to the reply for indicating the current voltage of the battery of the terminal device. When the power supply device determines that the USB interface is in bad contact, the power supply device transmits a fifth instruction to the terminal device, and then resets to reenter the phase 1.

It can be understood that in the constant current phase the output current of the power supply device does not keep unchanged all the time. The constant current phase is a multi-stage constant current phase, and the output current of the power supply device keeps unchanged within a period, i.e., in the constant current phase, multiple constant current charging stages corresponding to different charging currents are conducted successively.

For the above quick communication process applied between the power supply device and the terminal device, a quick charging communication instruction set applied between the power supply device and the terminal device can be defined. For example, the quick charging communication instruction set is illustrated by FIG. 1.

TABLE 1
Quick charging communication instruction set
Instruction 1: requesting for quick charging
Power supply	10101000	0xA8
device−>Terminal
device
Terminal	101XYYYYYY	X: 1−>Agree 0−>Disagree,
device−>Power		Path impedance =
supply device		YYYYYY*5(mΩ)
Instruction 2: querying whether a voltage of the power supply
device is proper
Power supply	10100100	0xA4
device−>Terminal
device
Terminal	1010XX0000	XX: 11−>Proper 10−>High
device−>Power		01−>Low 00−>Error
supply device
Instruction 3: querying for a maximum charging current currently
supported by the terminal device
Power supply	10100110	0xA6
device−>Terminal
device
Terminal	1010XXXXXX	Maximum charging current
device−>Power		currently supported
supply device		by the terminal
		device = 3000 +
		(XXXXXX*250)(mA)
Instruction 4: querying for a current voltage of a battery of the
terminal device
Power supply	10100010	0xA2
device−>Terminal
device
Terminal	101XYYYYYY	X: 1−>Being charged
device−>Power		0−>Uncharged, Battery
supply device		voltage = 3404 +
		(YYYYYY*16)(mV)
Instruction 5: informing the terminal device that USB connection is
poor and quick charging should be stopped
Power supply	10110010	0xB2
device−>Terminal
device
Terminal	NONE
device−>Power
supply device

From table 1, it can be seen that for each communication the power supply device first transmits an 8-bit data, and then the terminal device returns a 10-bit data. When the power supply device transmits a data, the power supply device can firstly transmit a most significant bit (MSB). Similarly, when the power supply device receives a data, the power supply device first receives a MSB. Clock signals for data transmission and data reception of the power supply device can be provided by the power supply device.

When the power supply device transmits a data, the power supply device transmits each bit of the data before transmitting a clock interrupt signal, which can guarantee the accuracy of the data received by the terminal device. When the power supply device receives a data, the power supply device can first transmit the clock interrupt signal, and then receive each bit of the data after a certain time, which can guarantee the accuracy and reliability of the data received by the power supply device.

FIG. 2 is a schematic view illustrating that the power supply device implements a data reception and data transmission in accordance with an implementation of the present disclosure. For FIG. 2, there are a number of methods for parsing a data to determine whether the data is valid. For example, previous n bits of a data can be defined as 101 in advance. When previous 3 bits of a data received by the power supply device is not 101, the data is determined as an invalid data, and communication fails. Or, a received data is defined to include 10 bits in advance. If a received data does not include 10 bits, the received data is determined as an invalid data, and communication fails.

FIG. 3 is a schematic view of a communication sequence of the power supply device in accordance with an implementation of the present disclosure. From FIG. 3, a relationship between a communication sequence indicated by the clock signals which are transmitted by the D+ data line and data signals transmitted by the D− data line. FIG. 4 illustrates a detailed example. In FIG. 4, after the power supply device transmits the instruction 10101000 to the terminal device, the power supply device receives the reply instruction 1011001111 from the terminal device.

The above quick charging communication process is finished based on negotiation between the power supply device and the terminal device, and safety of quick charging can be ensured.

From the above, it can be seen that during the whole process, the power supply device acts as a host, and conducts a handshake communication with the terminal device actively. The power supply device firstly determines whether to activate the quick charging communication process. After activating the quick charging communication process, the power supply device transmits an instruction to the terminal device actively. A condition that causes the power supply device to determine to activate the quick charging process is that the power supply device determines that within the preset time period the output current of the power supply device is greater than or equal to I2. When the power supply device determines that the condition is satisfied, the power supply device determines that the terminal device has recognized the type of the power supply device, that is, determines that the terminal device has recognized that the power supply device is a non-USB charging device (or has recognized that the power supply device is a standard charging device, and is not a non-standard charging device, such as a computer, or has recognized that the power supply device is not a computer, that is, the non-USB charging device can refer to any other charging device except a computer). By means of such a detection manner, the power supply device can be acted as a host, and the quick charging communication process is simplified. However, this manner is similar to a blind detection manner, that is, the power supply device guesses that the terminal device has recognized the type of the power supply device. Adopting the blind detection manner, certain errors may occur. For example, if a standard charging current of some terminal devices is I2 (or about I2), the current detected by the power supply device may not be exactly right, and the power supply device determines that the charging current of such terminal devices is less than I2, which may result in that such terminal devices cannot activate quick charging communication all the time and have to adopt a standard charging method for charging.

To avoid the above problem, the following will illustrate a quick charging method in accordance with another implementation of the present disclosure in combination with FIG. 5. In an implementation illustrated by FIG. 5, the quick communication process between the terminal device and the power supply device is activated by the terminal device, that is, the terminal device actively transmits a quick charging request to the power supply device. What needs to be illustrated is that after the terminal device transmits the quick charging request, the subsequent process can be still the same as the process illustrated by FIGS. 1-4. That is, the power supply device actively activates the quick charging communication with the terminal device to query a voltage, a current, and other parameters of the quick charging. Or, after the terminal device activates the quick charging, in the subsequent communication process the terminal device actively transmits instructions to the power supply device, that is, the terminal device actively provides the terminal device with the voltage of the battery, the maximum charging current currently supported by the terminal device, and so on. The power supply device may do not reply, or simply reply that the power supply device has received the instruction, the power supply device does not receive the instruction, or the power supply device agrees or disagrees. What needs to be further illustrated is that the quick charging communication instruction set and the communication sequence relationship illustrated by the above (for example, table 1, FIGS. 2-4) can be still applied in the implementations that the terminal device actively activates the quick charging request directly or after simple variation. For example, after the terminal device activates the quick charging request, if the subsequent communication process is still activated by the power supply device (in the subsequent phases of the quick charging process the power supply device actively activates the handshake request, that is, actively transmits the above instructions 2-5), the above instructions 2-5 can be still used, and the terminal device transmits the instruction 1. If the subsequent communication process is finished by the terminal device, an instruction set suitable for that the terminal device actively initiates the communication can be defined. The instruction set illustrated by FIG. 2 can be used.

TABLE 2
Quick charging communication instruction set
Instruction type	Instruction format	Instruction illustration
Fourth instrution□tell_volt□
Terminal	101011YYYYYY	Battery voltage = 3404 +
device−>Power		(YYYYYY * 16)
supply device
Power supply	101XX	XX□01−>Received□11−>
device−>Terminal		USB contact is not good,
device		impedance is too high; other
		formats−>abnormal
		communication
Second instruction□tell_is_vbus_ok□
Terminal	101001000YY0	YY: 11−>an output voltage of
device−>Power		the power supply device is
supply device		proper; 10−>the output
		voltage of the power supply
		device is too high; 01−> the
		output voltage of the power
		supply device is too low;
		00−>abnormal communication
Power supply	101XX	XX: 01−>Received□Other
device−>terminal		formats−>abnormal
device		communication
First instrution□tell_fastchg_ornot□
Terminal	101000YYYYY0	R = YYYYY*5
device−>Power
supply device
Power supply	101XX	XX: 01−>Received□Other
device−>Terminal		formats−>Abnormal
device		communication
Third instruction□tell_adapter_current_level□
Terminal	101010YYY000	Maximum charging current
device>Power supply		currently supported by the
device		terminal device = 3000 +
		(YYY * 250)
Power supply	101XX	XX: 01−>Received; Other
device−>Terminal		formats −>Abnormal
device		communication
Fifth instruction□tell_adapter_battery_max_volt□
Terminal	101100YYYYYY	Maximum voltage of the
device−>Power		battery = 4100 +
supply device		(YYYYYY * 10)
Power supply	101XX	XX□01−>Received; Other
device−>Terminal		formats−>Abnormal
device		communication

What needs to be illustrated is that in the above table 3404 is 3404 mV (3.404V), 4100 is 4100 mV (4.1V), 3000 is 3000 mA (3A), and 250 is 250 mA (0.25 A).

Certainly, after the terminal device actively initiates the quick charging request, in the subsequent communication process the terminal device and the power supply device can be respectively in charge of initiation work of some of the communication process. For example, the power supply device actively queries the terminal device for whether the output voltage is proper, the terminal device actively provides the power supply device with the battery voltage, and so on. In FIG. 5, from the perspective of the terminal device, the terminal device actively transmitting an instruction to the power supply device is taken as an example for illustration. It can be understood that steps or operations illustrated by FIG. 5 are just examples. The implementations of the present disclosure can further execute other steps or variations of the steps of FIG. 5. In addition, the steps of FIG. 5 can be executed in other sequences different from the sequence of FIG. 5, and furthermore some of the operations of FIG. 5 may not be executed.

FIG. 5 includes the follows.

A: the terminal device recognizes a type of the power supply device when the power supply device is coupled to the terminal device.

When it is detected that the coupling device is a USB device, it indicates that the coupling device is not a specified adapter, and may be a computer.

B: the terminal device determines whether the self status satisfies a quick charging condition. When the self status satisfies the quick charging condition, an operation at C is executed, otherwise an operation at D is executed.

C: when the terminal device detects that self status satisfies the quick charging condition, the terminal device transmits an instruction 1 (corresponding to the first instruction described above) via D+ and/or D− to initiate the quick charging request.

D: if the self status does not satisfy the quick charging condition, for example, when the remaining capacity of the battery is great, or the interior temperature of the terminal device is not proper for quick charging, the terminal device may not transmit the quick charging request, and is charged in a standard charging mode (corresponding to the normal charging mode described above).

E: the terminal device determines whether a reply instruction of the instruction 1 which indicates whether the power supply device supports a quick charging mode is received, and the reply instruction of the instruction 1 indicates whether the power supply device supports the quick charging mode. When the reply instruction of the instruction 1 is received, an operation at F is executed, otherwise the operation at D is executed.

When the power supply device supports the quick charging mode, the operation at F is executed. When the power supply device does not support the quick charging mode or the communication becomes abnormal (for example, the reply instruction of the instruction 1 is not received), the terminal device is charged in the standard charging mode.

F: the terminal device transmits an instruction 2 to the power supply device to inform the power supply device that the current output voltage is high, low, or proper.

The power supply device can output different voltage levels. When the power supply device receives the instruction 2, the power supply device outputs another voltage level according to the instruction 2 until the received instruction 2 indicates that the output voltage of the power supply device is proper.

Optionally, in an implementation, the instruction 2 can indicate the current battery voltage, so as to cause the power supply device to adjust the output voltage according to the battery voltage. Specifically, a mapping relationship between battery voltages and charging voltages of the quick charging mode can be established beforehand. In actual use, the power supply device can determine the voltage of quick charging corresponding to the current battery voltage according to the mapping relationship, and then the power supply device adjusts the output voltage to be the voltage of the quick charging.

G: the terminal device determines whether the reply instruction of the instruction 2 from the power supply device is received. When the reply instruction of the instruction 2 is received, an operation at H is executed, otherwise the operation at D is executed.

The operation at G is an optional operation. The reply instruction of the instruction 2 can indicate that the power supply device has received the instruction 2, or the power supply device has adjusted the output voltage according to the battery voltage.

H: the power supply device transmits an instruction 3 to the power supply device.

The instruction 3 can indicates a maximum charging current currently supported by the terminal device. After the power supply device receives the instruction 3, the power supply device can reply that the instruction 3 has been received.

I: the quick charging is activated and the charging process enters a constant current phase.

J: the terminal device constantly transmits an instruction 4 to the power supply device to inform the power supply device of the battery voltage, so as to cause the power supply device to finish impedance detection and adjustment of constant current.

The power supply device can transmit an instruction 4 to the power supply device in a certain period. Or, the terminal device can transmit the instruction 4 in a preset mode, and the preset mode is established according to charging characteristics of the battery.

In addition, the power supply device can be requested to transmit a reply each time the instruction 4 is received. If the terminal device does not receive a reply, the terminal device determines that the communication becomes abnormal, and the terminal device is charged in the standard charging mode.

K: the terminal device determines whether a reply instruction of the instruction 4 which indicates whether the power supply device has received the instruction 4 is received. When the reply instruction of the instruction 4 is received, step L is executed, otherwise the operation at D is executed.

L: the power supply device computes path impedance according to the battery voltage and adjusts constant current.

In the implementation of the present disclosure, after the terminal device recognizes the type of the power supply device, the terminal device actively initiates the quick charging request, thus the whole quick charging process is reliable and reasonable.

In combination with FIGS. 6-7, the following will specifically describe the terminal device and the power supply device of the implementations of the present disclosure. It can be understood that the terminal device of FIG. 6 can implement various functions described in the quick charging method, and the power supply device of FIG. 7 can implement various functions described in the quick charging method. To avoid repetition, detailed description will be omitted.

FIG. 6 is a schematic diagram illustrating a terminal device in accordance with an implementation of the present disclosure. A terminal device 600 of FIG. 6 is coupled to a power supply device via a USB interface. Power lines of the USB interface are used for charging a battery of the terminal device 600. Data lines of the USB interface are used for communication between the terminal device 600 and the power supply device. The terminal device 600 supports a normal charging mode and a quick charging mode. A charging speed of the quick charging mode is greater than that of the normal charging mode. The terminal device 600 includes a communication control circuit 610 and a charging circuit 620. It shall be noted that the terminal device 600 may be implemented in the form of one or more processors and a computer readable memory. The computer readable memory stores one or more instructions therein which may be invoked by the one or more processors to realize functions realized by the communication control circuit 610 and the charging circuit 620.

The communication control circuit 610 is configured to determine to charge the battery of the terminal device in the quick charging mode based on that current status of the terminal device satisfies a condition that the battery of the terminal device is operable to be charged in the quick charging mode by the power supply device, communicate with the power supply device to determine a charging voltage or a charging current of the quick charging mode, and communicate with the power supply device to transmit information of a current voltage of the battery to the power supply device after the power supply device adjusts an output voltage or output current of the power supply device according to the charging voltage or the charging current of the charging mode and enters a constant current phase, so as to cause the power supply device to adjust the output current according to the current voltage of the battery. An implementation is the follows. The communication control circuit 610 is configured to determine a type of the power supply device when it is detected that the power supply device is coupled to the terminal device 600, activate a quick charging communication process between the terminal device 600 and the power supply device when it is determined that the power supply device is a non-USB power supply device, and transmit a first instruction to the power supply device, and the first instruction is configured to request the power supply device to charge the battery in the quick charging mode. The communication control circuit 610 is further configured to communicate with the power supply device to determine a charging voltage of the quick charging mode, communicate with the power supply device to determine a charging current of the quick charging mode, and communicate with the power supply device to constantly transmit information of a voltage of the battery to the power supply device when the power supply device adjusts an output voltage and output current of the power supply device to be the charging voltage and the charging current of the quick charging mode respectively and enters a constant current phase, so as to cause the power supply device to adjust the output current according to the voltage of the battery, and charge the battery in a multi-stage constant current mode via the charging circuit 620.

In implementations of the present disclosure, the power supply device does not increase the charging current blindly for quick charging, but negotiates with the terminal device via communication with the terminal device 600 to determine whether the quick charging mode can be adopted. Compared with the present technology, the security of the quick charging process is improved.

In an alternative implementation, the first instruction further indicates path impedance of the terminal device 600. The path impedance of the terminal device 600 is configured for the power supply device to determine whether the USB interface is in good contact, or whether impedance of a charge circuit between the power supply device and the terminal device 600 is abnormal.

In an alternative implementation, a format of the first instruction is 101000YYYYY0, Y indicates 1 bit, and the path impedance of the terminal device 600 equals to YYYYY*5mΩ.

In an alternative implementation, the communication control circuit 610 is further configured to receive a reply instruction of the first instruction from the power supply device, and the reply instruction of the first instruction indicates that the power supply device supports the quick charging mode, or that the power supply device agrees to charge the battery in the quick charging mode.

In an alternative implementation, a format of the reply instruction of the first instruction is 101XX, X indicates 1 bit, XX=01 indicates that the power supply device has received the first instruction, and when XX is any value except 01, it indicates that the communication between the terminal device 600 and the power supply device becomes abnormal.

In an alternative implementation, the communication control circuit 610 is configured to transmit a second instruction to the power supply device, and the second instruction indicates that the output voltage of the power supply device is high, low, or proper. The communication control circuit 610 is configured to receive a reply instruction of the second instruction, and the reply instruction of the second instruction indicates that the power supply device has received the second instruction.

In an alternative implementation, a format of the second instruction is 101001000YY0, Y indicates 1 bit, YY=11 indicates that the output voltage of the power supply device is proper, YY=10 indicates that the output voltage of the power supply device is high, YY=01 indicates that the output voltage of the power supply device is low, and YY=00 indicates that the communication between the terminal device 600 and the power supply device becomes abnormal.

In an alternative implementation, a format of the reply instruction of the second instruction is 101XX, X indicates 1 bit, XX=01 indicates that the power supply device has received the second instruction, and when XX is any values except 01, it indicates that the communication between the terminal device 600 and the power supply device becomes abnormal.

In an alternative implementation, the communication control circuit 610 is configured to transmit a third instruction to the power supply device, and the third instruction indicates a maximum charging current currently supported by the terminal device 600. The communication control circuit 610 is configured to receive a reply instruction of the third instruction from the power supply device, and the reply instruction of the third instruction indicates that the power supply device has received the third instruction, or the third instruction indicates that the terminal device 600 is ready to enter the constant current phase.

In an alternative implementation, a format of the third instruction is 101010YYY000, and Y indicates 1 bit. The maximum charging current currently supported by the terminal device 600 equals to 3000+(YYY*250) mA.

In an alternative implementation, a format of the reply instruction of the third instruction is 101XX, X indicates 1 bit, XX=01 indicates that the power supply device has received the third instruction, and when XX is any value except 01, it indicates that the communication between the terminal device 600 and the power supply device becomes abnormal.

In an alternative implementation, the communication control circuit 610 is configured to constantly transmit a fourth instruction to the power supply device, and the fourth instruction indicates the current voltage of the battery. The communication control circuit 610 is configured to receive a reply instruction of the fourth instruction from the power supply device, and the reply instruction of the fourth instruction indicates that the power supply device has received the fourth instruction.

In an alternative implementation, a format of the fourth instruction is 101011YYYYYY, and Y indicates 1 bit. The voltage of the battery equals 3404+(YYYYYY*16) mV.

In an alternative implementation, the reply instruction of the fourth instruction further indicates that the USB interface is in bad contact, or indicates that impedance of the charge circuit between the power supply device and the terminal device 600 is abnormal, and is ready to exit the quick charging mode, or indicates that the quick charging communication process needs to be reactivated.

In an alternative implementation, a format of the reply instruction of the fourth instruction is 101XX, X indicates 1 bit, XX=01 indicates that the power supply device has received the fourth instruction, XX=11 indicates that the USB interface is in bad contact, or indicates that the impedance of the charge circuit between the power supply device and the terminal device 600 is abnormal, and is ready to exit the quick charging mode, or indicates that the quick charging communication process needs to be reactivated, and when XX is any value except 01 and 11, it indicates that the communication between terminal device 600 and the power supply device becomes abnormal.

In an alternative implementation, the communication control circuit 610 is further configured to transmit a fifth instruction to the power supply device, and the fifth instruction indicates a maximum voltage of the battery. The communication control circuit 610 is further configured to receive a reply instruction of the fifth instruction, and the reply instruction of the fifth instruction indicates that the power supply device has received the fifth instruction.

In an alternative implementation, a format of the fifth instruction is 101100YYYYYY, and Y indicates 1 bit. The maximum voltage of the battery is 4100+YYYYYY*10 mV.

In an alternative implementation, a format of the reply instruction of the fifth instruction is 101XX, X indicates 1 bit, XX=01 indicates that the power supply device has received the fifth instruction, and when XX is any value except 01, it indicates that the communication between the terminal device 600 and the power supply device becomes abnormal.

In an alternative implementation, the communication control circuit 610 is further configured to execute at least one of following operations when the communication between the power supply device and the terminal device 600 becomes abnormal, and the following operations include: exiting the quick charging mode, charging the battery in the normal charging mode, stopping charging, or reactivating the quick charging communication process.

In an alternative implementation, an instruction transmitted from the terminal device 600 to the power supply device contains multiple bits. When the terminal device 600 transmits any instruction, the terminal device 600 first transmits a MSB of the multiple bits of the any instruction. Or, an instruction received from the power supply device by the terminal device 600 contains multiple bits. When the terminal device 600 receives a certain instruction, the terminal device 600 first receives a MSB of the multiple bits of the certain instruction.

In an alternative implementation, clock signals used in the communication between the power supply device and the terminal device 600 are provided by the power supply device.

In an alternative implementation, an instruction transmitted from the power supply device to the terminal device 600 contains multiple bits. During a process of transmitting each of the multiple bits, the power supply device first transmits each bit, and then transmits a clock interrupt signal. Or, a reply instruction received from the terminal device 600 by the power supply device contains multiple bits. During a process of receiving each of the multiple bits, the power supply device first transmits the clock interrupt signal, and then receives each bit after a preset time interval.

In an alternative implementation, each instruction received from the terminal device 600 by the power supply device contains a 12-bit data. The power supply device receives the 12-bit data from the terminal device 600 via twelve continuous clock periods of the clock signal. Level of previous 500 μs of each of the twelve continuous clock periods is high, and level of latter 10 μs of each of the twelve continuous clock periods is low. Or, each reply instruction transmitted from the power supply device to the terminal device 600 contains a 5-bit data. The power supply device transmits the 5-bit data to the terminal device 600 via five continuous clock periods of the clock signal. Level of previous 10 μs of each of the five continuous clock periods is low, and level of latter 500 μs of each of the five continuous clock periods is high.

In an alternative implementation, during a process that the power supply device receives an instruction from the terminal device 600, a minimum value of high level of the clock signal used between the power supply device and the terminal device 600 equals to VDD of the power supply device minus 0.7V. Or, during the process that the power supply device receives an instruction from the terminal device 600, a maximum value of low level of the clock signal used between the power supply device and the terminal device 600 is 0.8V. Or, during a process that the power supply device transmits an instruction to the terminal device 600, a minimum value of high level of the clock signal used between the power supply device and the terminal device 600 equals to 0.25VDD+0.8V. Or, during the process that the power supply device transmits an instruction to the terminal device 600, a maximum value of the high level of the clock signal used between the power supply device and the terminal device 600 is 4.5V. Or, during the process that the power supply device transmits an instruction to the terminal device 600, a maximum value of low level of the clock signal used between the power supply device and the terminal device 600 is 0.15VDD. The VDD is a work voltage of the power supply device, and/or the VDD is greater than 3.2V and less than 4.5V.

FIG. 7 is a schematic diagram illustrating a power supply device in accordance with an implementation of the present disclosure. A power supply device 700 of FIG. 7 is coupled to a terminal device via a USB interface. Power lines of the USB interface are used for the power supply device 700 to charge a battery of the terminal device. Data lines of the USB interface are used for communication between the power supply device 700 and the terminal device. The power supply device 700 supports a normal charging mode and a quick charging mode. A charging speed of the quick charging mode is greater than that of the normal charging mode. The power supply device 700 includes a communication control circuit 710 and a charging circuit 720. It shall be noted that the power supply device 700 may be implemented in the form of one or more processors and a computer readable memory. The computer readable memory stores one or more instructions therein which may be invoked by the one or more processors to realize functions realized by the communication control circuit 710 and the charging circuit 720.

The communication control circuit 710 is configured to determine to charge the battery of the terminal device in the quick charging mode based on that current status of the terminal device satisfies a condition that the battery of the terminal device is operable to be charged in the quick charging mode, communicate with the terminal device to determine a charging voltage or a charging current of the quick charging mode, adjust an output voltage or output current output to the terminal device according to the charging voltage or the charging current of the quick charging mode to enter a constant current phase, communicate with the terminal device during the constant current phase to receive information of a current voltage of the battery, and adjusts the output current output to the terminal device according to the current voltage of the battery in the constant current phase. An implementation is the follows. The communication control circuit 710 is configured to receive a first instruction from the terminal device when the terminal device determines that the power supply device 700 is a non-USB power supply device, and activates quick charging communication between the power supply device 700 and the terminal device, and the first instruction requests the power supply device 700 to charge the battery in the quick charging mode. The communication control circuit 710 is further configured to communicate with the terminal device to determine a charging voltage of the quick charging mode, communicate with the terminal device to determine a charging current of the quick charging mode, and adjust an output voltage and output current of the power supply device 700 to be the charging voltage and the charging current of the quick charging mode respectively to enter a constant current phase, communicate with the terminal device during the constant current phase to constantly receive information of a current voltage of the battery from the terminal device, adjust the output current according to the voltage of the battery, and charge the battery in a multi-stage constant current mode via the charging circuit 720.

In implementations of the present disclosure, the power supply device does not increase the charging current blindly for quick charging, but negotiates with the terminal device via communication with the terminal device 600 to determine whether the quick charging mode can be adopted. The security of the quick charging process is improved.

In an alternative implementation, the first instruction further indicates path impedance of the terminal device. The path impedance of the terminal device is configured for the power supply device 700 to determine whether the USB interface is in good contact, or whether impedance of a charge circuit between the power supply device 700 and the terminal device is abnormal.

In an alternative implementation, a format of the first instruction is 101000YYYYY0, Y indicates 1 bit, and the path impedance of the terminal device equals to YYYYY*5mΩ.

In an alternative implementation, the communication control circuit 710 is further configured to transmit a reply instruction of the first instruction to the terminal device, and the reply instruction of the first instruction indicates that the power supply device 700 supports the quick charging mode, or indicates that the power supply device 700 agrees to charge the battery in the quick charging mode.

In an alternative implementation, a format of the reply instruction of the first instruction is 101XX, X indicates 1 bit, XX=01 indicates that the power supply device 700 has received the first instruction, and when XX is any value except 01, it indicates that the communication between the terminal device 600 and the power supply device becomes abnormal.

In an alternative implementation, the communication control circuit 710 is configured to receive a second instruction from the terminal device, and the second instruction indicates whether the output voltage of the power supply device is proper. The communication control circuit 710 is configured to transmit a reply instruction of the second instruction to the terminal device, and the reply instruction of the second instruction indicates that the power supply device 700 has received the second instruction.

In an alternative implementation, a format of the second instruction is 101001000YY0, Y indicates 1 bit, YY=11 indicates that the output voltage of the power supply device 700 is proper, YY=10 indicates that the output voltage of the power supply device 700 is high, YY=01 indicates that the output voltage of the power supply device 700 is low, and YY=00 indicates that the communication between the terminal device and the power supply device 700 becomes abnormal.

In an alternative implementation, a format of the reply instruction of the second instruction is 101XX, X indicates 1 bit, XX=01 indicates that the power supply device has received the second instruction, and when XX is any value except 01, it indicates that the communication between the terminal device and the power supply device 700 becomes abnormal.

In an alternative implementation, the communication control circuit 710 is configured to receive a third instruction from the terminal device, and the third instruction indicates a maximum charging current currently supported by the terminal device. The communication control circuit 710 is configured to transmit a reply instruction of the third instruction to the terminal device, and the reply instruction of the third instruction indicates that the power supply device 700 has received the third instruction, or the third instruction indicates that the terminal device is ready to enter the constant current phase.

In an alternative implementation, a format of the third instruction is 101010YYY000, and Y indicates 1 bit. The maximum charging current currently supported by the terminal device equals to 3000+(YYY*250) mA.

In an alternative implementation, a format of the reply instruction of the third instruction is 101XX, X indicates 1 bit, XX=01 indicates that the power supply device 700 has received the third instruction, and when XX is any value except 01, it indicates that the communication between the terminal device and the power supply device 700 become abnormal.

In an alternative implementation, the communication control circuit 710 is configured to constantly receive a fourth instruction from the terminal device, and the fourth instruction indicates the voltage of the battery. The communication control circuit 710 is configured to transmit a reply instruction of the fourth instruction to the terminal device, and the reply instruction of the fourth instruction indicates that the power supply device 700 has received the fourth instruction.

In an alternative implementation, a format of the fourth instruction is 101011YYYYYY, and Y indicates 1 bit. The voltage of the battery equals 3404+(YYYYYY*16) mV.

In an alternative implementation, the reply instruction of the fourth instruction further indicates that the USB interface is in bad contact, or indicates that the impedance of the charge circuit between the power supply device 700 and the terminal device is abnormal, and is ready to exit the quick charging mode, or indicates that the quick charging communication process needs to be reactivated.

In an alternative implementation, a format of the reply instruction of the fourth instruction is 101XX, X indicates 1 bit, XX=01 indicates that the power supply device 700 has received the fourth instruction, XX=11 indicates that the USB interface is in bad contact, or indicates that the impedance of the charge circuit between the power supply device 700 and the terminal device is abnormal, and is ready to exit the quick charging mode, or indicates that the quick charging communication process needs to be reactivated, and when XX is any value except 01 and 11, it indicates that the communication between terminal device and the power supply device 700 becomes abnormal.

In an alternative implementation, the communication control circuit 710 is further configured to receive a fifth instruction from the terminal device, and the fifth instruction indicates a maximum voltage of the battery. The communication control circuit 710 is further configured to transmit a reply instruction of the fifth instruction to the terminal device, and the reply instruction of the fifth instruction indicates that the power supply device 700 has received the fifth instruction.

In an alternative implementation, a format of the fifth instruction is 101100YYYYYY, and Y indicates 1 bit. The maximum voltage of the battery is 4100+YYYYYY*10 mV.

In an alternative implementation, a format of the reply instruction of the fifth instruction is 101XX, X indicates 1 bit, XX=01 indicates that the power supply device 700 has received the fifth instruction, and when XX is any value except 01, it indicates that the communication between the terminal device and the power supply device 700 becomes abnormal.

In an alternative implementation, the communication control circuit 710 is further configured to execute at least one of following operations when the communication between the power supply device 700 and the terminal device becomes abnormal, and the following operations include: exiting the quick charging mode, charging the battery in the normal charging mode, stopping charging, or reactivating the quick charging communication process.

In an alternative implementation, an instruction transmitted from the terminal device to the power supply device 700 contains multiple bits. When the power supply device 700 receives any instruction, the power supply device 700 first receives a MSB of the multiple bits of the any instruction. Or, an instruction transmitted from the power supply device 700 to the terminal device contains multiple bits. When the power supply device 700 transmits a certain instruction, the power supply device 700 first transmits a MSB of the multiple bits of the certain instruction.

In an alternative implementation, clock signals used in the communication between the power supply device 700 and the terminal device are provided by the power supply device 700.

In an alternative implementation, an instruction transmitted from the power supply device 700 to the terminal device contains multiple bits. During a process of transmitting each of the multiple bits, the power supply device 700 first transmits each bit, and then transmits a clock interrupt signal. Or, a reply instruction received from the terminal device by the power supply device 700 contains multiple bits. During a process of receiving each of the multiple bits, the power supply device 700 first transmits the clock interrupt signal, and then receives each bit after a preset time interval.

In an alternative implementation, each instruction received from the terminal device by the power supply device 700 contains a 12-bit data. The power supply device 700 receives the 12-bit data from the terminal device 600 via twelve continuous clock periods of the clock signal. Level of previous 500 μs of each of the twelve continuous clock periods is high, and level of latter 10 μs of each of the twelve continuous clock periods is low. Or, each reply instruction transmitted from the power supply device 700 to the terminal device includes a 5-bit data. The power supply device 700 transmits the 5-bit data to the terminal device via five continuous clock periods of the clock signal. Level of previous 10 μs of each of the five continuous clock periods is low, and level of latter 500 μs of each of the five continuous clock periods is high.

In an alternative implementation, during a process that the power supply device 700 receives an instruction from the terminal device, a minimum value of high level of the clock signal used between the power supply device 700 and the terminal device equals to VDD of the power supply device minus 0.7V. Or, during the process that the power supply device 700 receives an instruction from the terminal device, a maximum value of low level of the clock signal used between the power supply device 700 and the terminal device is 0.8V. Or, during a process that the power supply device 700 transmits an instruction to the terminal device, a minimum value of high level of the clock signal used between the power supply device 700 and the terminal device equals to 0.25VDD+0.8V. Or, during the process that the power supply device 700 transmits an instruction to the terminal device, a maximum value of the high level of the clock signal used between the power supply device 700 and the terminal device is 4.5V. Or, during the process that the power supply device 700 transmits an instruction to the terminal device, a maximum value of low level of the clock signal is 0.15VDD. The VDD is a work voltage of the power supply device, and/or the VDD is greater than 3.2V and less than 4.5V.

Those skilled in the art should appreciate that units and programming steps of various examples described in the implementations of the present disclosure can be realized by electronic hardware or a combination of computer software and electronic hardware. Whether these functions are realized by hardware or software depends on particular applications and design constraint conditions. For each particular application, professionals can employ different methods to realize described functions, but this realization should fall into the scope of the present disclosure.

For convenience and simplicity, those skilled in the art can clearly understand that when the specific work processes of the above described systems, devices, and units are described, the corresponding processes of the above method implementations can be referred, which will not be repeated herein.

In several implementations provided by the present disclosure, it can be understood that the disclosed systems, devices, and methods can be implemented by other manners. For example, the device implementations described above are only schematic. For example, the units are divided according to logic functions and can be divided by another manner in an actual implementation. For example, several units or assemblies can be combined or can be integrated into another system, or some features can be ignored, or are not executed. Another point is that mutual coupling or direct coupling or communication connection shown or discussed herein can be indirect coupling or communication connection through certain interfaces, devices, or units, and can be in the form of electricity, machine, or other.

The units illustrated as separate units can be or cannot be physically separated, and components shown in units can be or cannot be physical units, that is, can be in a place, or can be distributed in several network units. A part of the units or all the units can be selected according to actual need to realize the purpose of the solution of the implementations.

Additionally, various functional units in the implementations of the present disclosure can be integrated into one processing unit, or various functional units can exist alone, or two or more units can be integrated into one unit.

If the functions can be realized in the form of software functional units and can be sold or used as stand-alone products, they can be stored in a computer-readable storage medium. Based on such understanding, the technical solution of the present disclosure or the part that contributes to the existing technology or a part of the technical solution can be embodied in the form of a software product. The computer software product can be stored in a storage medium, and include a plurality of instructions configured to direct a computer device (personal computer, server, or network device) to execute all of or a part of steps of various implementations of the present disclosure. The storage mediums described above include a U disk, a mobile disk, a read-only memory (ROM), a random access memory (RAM), a disc, a compact disc, or other medium storing program codes.

The foregoing descriptions are merely preferred implementations of the present disclosure, rather than limiting the present disclosure. Any one skilled in the art can easily make change or alterations within the technology range of the present disclosure, and those change or alterations shall fall within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be limited by the protection scope of the claims.

Claims

1. A method of charging, comprising: determining to charge a battery of a terminal device in a charging mode based on that a current status of a terminal device satisfies a condition that the battery of the terminal device is operable to be charged in the charging mode by a power supply device;communicating with the power supply device to determine a charging voltage or a charging current of the charging mode; andcommunicating with the power supply device to transmit information of a current voltage of the battery to the power supply device after the power supply device adjusts an output voltage or output current of the power supply device according to the charging voltage or the charging current of the charging mode and enters a constant current phase to cause the power supply device to adjust the output current according to the current voltage of the battery.

2. The method of claim 1, further comprising: communicating with the power supply device to inform the power supply device of an impedance of a charging path of the terminal device, wherein the power supply device determines whether coupling with the terminal device is bad according to the impedance of the charging path of the terminal device, and exits the charging mode based on a determination that the coupling with the terminal device is bad.

3. The method of claim 1, wherein in the constant current phase, multiple constant current charging stages corresponding to different charging currents are conducted successively.

4. The method of claim 1, further comprising: determining to charge the battery of the terminal device in another charging mode based on that the current status of the terminal device satisfies a condition that the battery of the terminal device is operable to be charged in the another charging mode, a charging speed of the another charging mode is slower than that of the charging mode.

5. The method of claim 1, wherein the communication with the power supply device is conducted via instruction transmission and instruction reception, and wherein: an instruction transmitted comprises multiple bits, during a process of transmitting each of the multiple bits, one bit is first transmitted via a negative (D−) data line, and then a clock interrupt signal is transmitted via a positive (D+) data line; ora reply instruction received comprises multiple bits, during a process of receiving each of the multiple bits, the clock interrupt signal is first received via the D+ data line, and then one bit is received via the D− data line.

6. A method of charging, comprises: determining to charge a battery of a terminal device in a charging mode based on that current status of the terminal device satisfies a condition that the battery of the terminal device is operable to be charged in the charging mode;communicating with the terminal device to determine a charging voltage or a charging current of the charging mode;adjusting an output voltage or output current output to the terminal device according to the charging voltage or the charging current of the charging mode to enter a constant current phase;communicating with the terminal device during the constant current phase to receive information of a current voltage of the battery; andadjusting the output current output to the terminal device according to the current voltage of the battery in the constant current phase.

7. The method of claim 6, further comprising: receiving an impedance of a charging path of the terminal device;determining whether coupling with the terminal device is bad according to the impedance of the charging path of the terminal device; andexiting the charging mode based on a determination that the coupling with the terminal device is bad.

8. The method of claim 6, wherein in the constant current phase, multiple constant current charging stages corresponding to different charging currents are conducted successively.

9. The method of claim 6, further comprising: executing, when the communication with the terminal device becomes abnormal, at least one of following operations: exiting the charging mode, charging the battery in another charging mode a charging speed of which is slower than that of the charging mode, and stopping charging the battery in the charging mode.

10. The method of claim 6, wherein adjusting the output current output to the terminal device according to the current voltage of the battery in the constant current phase comprises: adjusting the output current output to the terminal device according to a mapping relationship between voltages of the battery and charging voltages of the charging mode.

11. The method of claim 6, further comprising: determining to charge the battery of the terminal device in another charging mode based on that the current status of the terminal device satisfies a condition that the battery of the terminal device is operable to be charged in the another charging mode, a charging speed of the another charging mode is slower than that of the charging mode.

12. The method of claim 6, wherein the communication with the power supply device is conducted via instruction transmission and instruction reception; an instruction transmitted comprises multiple bits, during a process of transmitting each of the multiple bits, one bit is first transmitted via a negative (D−) data line, and then a clock interrupt signal is transmitted via a positive (D+) data line; ora reply instruction received comprises multiple bits, during a process of receiving each of the multiple bits, the clock interrupt signal is first received via the D+ data line, and then one bit is received via the D− data line.

13. A power supply device comprising: at least one processor; anda computer readable memory, coupled to the at least one processor and storing at least one computer executable instruction therein which, when executed by the at least one processor, causes the at least one processor to: determine to charge a battery of a terminal device in a charging mode based on that current status of the terminal device satisfies a condition that the battery of the terminal device is operable to be charged in the charging mode;communicate with the terminal device to determine a charging voltage or a charging current of the charging mode;adjust an output voltage or output current output to the terminal device according to the charging voltage or the charging current of the charging mode to enter a constant current phase;communicate with the terminal device during the constant current phase to receive information of a current voltage of the battery; andadjust the output current output to the terminal device according to the current voltage of the battery in the constant current phase.

14. The power supply device of claim 13, wherein the at least one processor is further caused to: receiving an impedance of a charging path of the terminal device;determining whether coupling with the terminal device is bad according to the impedance of the charging path of the terminal device; andexiting the charging mode based on a determination that the coupling with the terminal device is bad.

15. The power supply device of claim 13, wherein in the constant current phase, multiple constant current charging stages corresponding to different charging currents are conducted successively.

16. The power supply device of claim 13, the at least one processor is further caused to: execute, when the communication with the terminal device becomes abnormal, at least one of following operations: exiting the charging mode, charging the battery in another charging mode a charging speed of which is slower than that of the charging mode, and stopping charging the battery in the charging mode.

17. The power supply device of claim 13, wherein the at least one processor caused to adjust the output current output to the terminal device according to the current voltage of the battery in the constant current phase is further caused to: adjust the output current output to the terminal device according to a mapping relationship between voltages of the battery and charging voltages of the charging mode.

18. The power supply device of claim 13, wherein the at least one processor is further caused to: determine to charge the battery of the terminal device in another charging mode based on that the current status of the terminal device satisfies a condition that the battery of the terminal device is operable to be charged in the another charging mode, a charging speed of the another charging mode is slower than that of the charging mode.

19. The power supply device of claim 13, wherein the communication with the power supply device is conducted via instruction transmission and instruction reception, and wherein: an instruction transmitted comprises multiple bits, during a process of transmitting each of the multiple bits, one bit is first transmitted via a negative (D−) data line, and then a clock interrupt signal is transmitted via a positive (D+) data line; ora reply instruction received comprises multiple bits, during a process of receiving each of the multiple bits, the clock interrupt signal is first received via the D+ data line, and then one bit is received via the D− data line.

20. The power supply device of claim 19, wherein an instruction received by the power supply device comprises a 12-bit data, the 12-bit data is received via twelve continuous clock periods of the clock interrupt signal, a level of previous 500 μs of each of the twelve continuous clock periods is high, and a level of latter 10 μs of each of the twelve continuous clock periods is low; or a reply instruction transmitted by the power supply device comprises a 5-bit data, the 5-bit data is transmitted via five continuous clock periods of the clock interrupt signal, the level of previous 10 μs of each of the five continuous clock periods is low, and the level of latter 500 μs of each of the five continuous clock periods is high.