For the purposes of promoting an understanding of the principles disclosed herein, reference will now be made to a number of embodiments.
Referring now to
In an embodiment, the charge-control unit 12 is implemented within, i.e., housed within, an electronic device 14, although this disclosure contemplates embodiments in which the charge-control unit 12 may be separate from, i.e., housed separately from and/or remote from, the electronic device 14. The electronic device 14 is, for example, a portable electronic device. Examples of the portable electronic device 14 may include, but are not limited to, a laptop or notebook computer, a tablet computer or other tablet device, a hand-held electronic device, a cellular telephone, and the like. In alternative embodiments, the electronic device 14 may be a non-portable electronic device. The electronic device 14 includes one or more electrical circuits and/or subsystems that consume electrical energy, and in
The charge control unit 12 has an input 24 that is electrically coupled to one end of a supply line 25 and to the + output of the AC adapter 16The opposite end of the supply line 25 defines an output 26 of the charge control unit 12 that is electrically coupled to the system load 20. The “−” output of the AC adapter 16 is electrically coupled to a reference node 27 of the charge control unit 12. As used herein, the terms “reference voltage” and “reference node” refer to an electrical connection identified in the drawings by a down-arrow, which reference connection is maintained at a predefined reference potential. In an embodiment, the predefined reference potential (and therefore the reference voltage) is ground potential, although other predetermined reference potentials (and corresponding reference voltages) are contemplated by this disclosure. In an embodiment, the reference node 27 of the charge-control unit 12 is electrically coupled to the “−” output of the AC adapter 16 and also to the reference nodes of the system load 20, the chargeable power source 22, the electronic device 14, and adaptive charge controller 28.
The charge-control unit 12 also includes an adaptive charge controller 28 and switching circuitry in the form of one or more switches coupled in-line with the supply line 25 between the charge-control-unit input 24 and output 26. The switching circuitry is responsive to control signals produced by the adaptive charge controller 28 to controllably supply voltage and current to the output 26 of the charge control circuit 12, e.g., to the system load 20. In the embodiment illustrated in
One node of the pair of switches, i.e., the output of the switch S2, is electrically coupled to the reference voltage, and another node, i.e., the signal input of the switch S1, is electrically coupled through a resistor RIN disposed in-line (i.e., series-coupled) with the supply line 25 to the input 24 of the charge control unit 12. Another node of the pair of switches, i.e., the connection of the output of the switch S1 and the signal input of the switch S2, is electrically coupled through a series combination of an inductor L disposed in-line (i.e., series-connected) with the supply line 25 and another resistor ROUT also disposed in-line (i.e., series-connected) with the supply line 25 to the output 26 of the charge control unit 12. The inductor L is positioned between the resistor ROUT and the common connection of the output of the switch S1 and the input of the switch S2, and a capacitor C is electrically coupled at one end to the reference voltage and at an opposite end to the common connection of the inductor L and the resistor ROUT. Together the inductor, L, and the capacitor, C, make up a conventional low-pass filter circuit used in the charge-control unit 12 to filter out high-frequency effects that may be introduced onto the supply line 25 by switching of the switches S1 and/or S2. In some alternate embodiments, the inductor L and/or the capacitor C may be replaced by one or more other conventional electrical components to form a low-pass or other type of signal filtering circuit, and in other embodiments either or both of the inductor L and the capacitor C may be omitted from the charge control circuit 12.
The electronic device 14 includes a switching device S3 having one node, e.g., an input/output node, electrically coupled to the output 26 of the charge-control unit 12, another node, e.g., an input/output node, electrically coupled to one end of the chargeable power source 22, and a control input electrically coupled to a pulse-width-modulated charge output, PWMC, of the adaptive charge controller 28. In alternative embodiments, the switching device S3 may be included within the charge-control unit 12, and in any case the opposite end of the chargeable power source 22 is electrically coupled to the reference voltage. The adaptive charge controller 28 is operable, as will be described in greater detail hereinafter, to control the duty cycles of the control signals PWMI, PWMV, and PWMC applied to the switches S1-S3 respectively to control the magnitudes of the output current IOUT and the output voltage VOUT produced at the output 26 of the charge-control unit 12 and to control, e.g., partition, consumption of the output current IOUT as between a load current IL supplied to the system load 20 and a charge current ICH supplied to the chargeable power source 22 under various operating conditions in which the AC adapter 16 is electrically coupled to the charge-control unit 12.
In the embodiment shown in
The charge-control unit 12 further includes an input current sensor electrically coupled between the input 24 of the charge control unit 12 and the signal input of the switch S1, which operates to sense the input current IIN of the charge control unit 12, which input current is also the output current IOA produced by the AC adapter 16. In the illustrated embodiment, the input current sensor is implemented in the form of the combination of the resistor RIN and a current sense amplifier 30 having one input electrically coupled to the common connection of the input 24 of the charge-control unit 12 and one end of the resistor RIN, and another input electrically coupled to the common connection of the signal input of the switch S1 and the opposite end of the resistor RIN. The output of the current-sense amplifier 30 is electrically coupled to an input-current input, VIIN, of the adaptive charge controller 28. The output of the current-sense amplifier 30 produces the voltage, VIIN, which is proportional to the input current IIN supplied to the charge-control unit 12 by the AC adapter 16. The output voltage VOA produced by the AC adapter 16 is the input voltage VIN at the input 24 of the charge control unit 12, and the input 24 is electrically coupled to an input-voltage input, VIN, of the adaptive charge controller 28. In alternative embodiments, one or more other conventional current and/or voltage sensors may be used to determine the input current and voltage respectively of the charge-control unit 12. In any case, signals corresponding to the DC current (IIN) supplied to the charge-control unit 12 (which is, in the illustrated embodiment, the output current IOA of the AC adapter 16) and the DC voltage (VIN) supplied to the charge-control unit 12 (which is, in the illustrated embodiment, the output voltage VOA of the AC adapter 16) are supplied as inputs to the adaptive charge controller 28. The charge-control unit 12 further includes an output-current sensor electrically coupled between the output 26 of the charge-control unit 12 and the output of the filter circuit (e.g., the output of the inductor L), which operates to sense the output current IOUT produced by the charge control unit 12 (where IOUT is the sum of the load current, IL, consumed by the system load 20 and the charge current, ICH, consumed by the chargeable power source 22). In the illustrated embodiment, the output-current sensor is implemented in the form of the combination of the resistor ROUT and a current-sense amplifier 32 having one input electrically coupled to the common connection of the output 26 of the charge-control unit 12 and one end of the resistor ROUT, and another input electrically coupled to the common connection of the input of the inductor L and the opposite end of the resistor ROUT. The output of the current-sense amplifier 32 is electrically coupled to an output-current input, VIOUT, of the adaptive charge controller 28, and the output of the current-sense amplifier 32 produces the voltage, VIOUT, which is proportional to the output current IOUT supplied by the charge-control unit 12. The output voltage VOUT produced at the output 26 of the charge-control unit 12 is electrically coupled to an output voltage input, VOUT, of the adaptive charge controller 28. In alternative embodiments, one or more other conventional current and/or voltage sensors may be used to determine the output current and voltage respectively of the charge-control unit 12. In any case, signals corresponding to the output current of the charge-control unit 12 and the output voltage of the charge-control unit 12 are supplied as inputs to the adaptive charge controller 28.
Referring now to
Referring to
Referring now to
In some conventional charge control systems, the maximum output power produced by the AC adapter 16 when the input current IIN demanded by the combination of the charge control unit 12 and the system load 20 or by the combination of the system load 20, the chargeable power source 22 and the charge control unit 12 exceeds that which can be produced by the AC adapter 16, is regulated at the output power that is produced when the output current, IOA, produced by the AC adapter 16 reaches IRA or some other static output current value. In other conventional charge control systems the maximum allowable output power produced by the AC adapter 16 under such conditions is regulated at the output power that is produced when the output voltage, VOA, produced by the AC adapter 16 drops to some predefined static voltage value, VE, after the output current IOA reaches and increases beyond IRA. In such conventional charge control systems which include an input dynamic power management unit, such as IDPM unit 54 for example, the output voltage, VOA, is the reference control signal input to the IDPM unit, and the IDPM unit is configured to be activated when the output voltage, VOA, produced by the AC adapter 16 drops below the predefined static voltage value, VE. The PWM controller 40 is then responsive to control signals produced by the IDPM unit when VOA drops below VE to control PWMV such that the output voltage VOA produced by the AC adapter 16 is maintained at the constant voltage VE. The magnitude of the output current, IOA, produced by the AC adapter 16 under such conditions, i.e., in which the input current IIN demanded by the combination of the system load 20 and the charge control unit 12 or by the combination of the system load 20, the chargeable power source 22 and the charge control unit 12 exceeds that which can be produced by the AC adapter 16, will be that (but less than IM) at which the output voltage, VOA, intersects the boundary of the characteristic current-voltage curve 55 of the particular AC adapter 16. The PWM controller 40 controls PWMI under such conditions in a conventional manner to thereby control the output current IOA of the AC adapter 16 to such a magnitude. The PWM controller 40 also controls PWMC under such conditions to partition IOUT produced by the charge control unit 12 into appropriate magnitudes of IL and ICH.
In contrast to the conventional charge control systems just described, and referring now to
In some alternative embodiments, the magnitude of the reference control signal, VR, produced by the APM unit 52 may be proportional to the output voltage, VOA, at which the AC adapter 16 produces maximum output power, and in such embodiments the IDPM unit 54 may be configured to be responsive to such a magnitude of VR to produce appropriate control signals to which the PWM controller 40 is responsive to control PWMV such that VOA produced by the AC adapter 16 results in maximum power output by the AC adapter 16 under such operating conditions. Any modifications to the IDPM unit 54 required for such alternative operation would be a mechanical step for a skilled artisan.
In other alternative embodiments, the reference control signal produced by the APM unit 52 may be VIR, and the IDPM unit 54 may in such embodiments be configured to produce control signals to which the PWM controller 40 is responsive to control PWMI such that IOA produced by the AC adapter 16 is the magnitude of output current at which the maximum output power is produced (i.e., the magnitude MP as illustrated in
Referring now to
The process 100 will, for purposes of description, be described as being implemented and executed by the APM unit 52, the IDPM unit 54 and the PWM controller 40 as just described with respect to
In any case, the Input Dynamic Power Management (IDPM) unit 54 is responsive in a conventional manner to the reference control signal to produce control signals from which the PWM controller 40 controls the duty cycle of the control signal PWMI or PWMV in a manner that controls the switches S1 or S2 respectively to draw from the AC adapter 16 an input current, IIN (corresponding to the output current, IOA, of the AC adapter 16), or an input voltage, VIN, (corresponding to the output voltage, VOA, of the AC adapter 16), that corresponds to the maximum available output power, M, that can be produced by the AC adapter 16. By so controlling the switching circuitry of the charge control unit 12, the maximum output power that can be produced by the AC adapter 16 is supplied to the input of the charge control unit 12. Via conventional control of the device S3 in combination with the diode D1, electrical power required by the system load 20 is provided thereto, and all remaining electrical power is applied to the rechargeable power source 22 for recharging thereof. In this manner, all output power available from the AC adapter 16 that is not used by the combination of the system load 20 and the charge controller 12 is used to recharge the rechargeable power source 22, thereby maximizing the recharging current/voltage and minimizing charge time under such conditions.
Referring now to
The APM unit 58 further includes an adaptive gain and filter circuit 60 which receives at one input the input voltage, VIN, (i.e., corresponding to the output voltage of the AC adapter 16) and which produces as an output an adjusted voltage, VA. The adjusted voltage, VA, is provided to one input of a conventional analog-to-digital converter (ADC) circuit 62. Another adaptive gain and filter circuit 64 receives at one input the input current signal, VIIN, (i.e., a voltage signal having a value which corresponds to the output current of the AC adapter 16) and produces as an output an adjusted current signal, VIA, which is illustratively a voltage signal having a value corresponding to the output current of the AC adapter 16 adjusted by the adaptive gain and filter circuit 62. The adjusted current signal VIA is provided to another input to the ADC circuit 62. The ADC circuit 62 is operable in a conventional manner to convert the adjusted analog signals VA and VIA to digital signals VAD and VIAD produced at separate respective outputs of the ADC circuit 62. The VAD output of the ADC circuit 62 is provided to one input of a conventional digital multiplier circuit 66 and also to another input of the adaptive gain and filter circuit 60. The VIAD output of the ADC circuit 62 is provided to another input of the digital multiplier circuit 66 and also to another input of the adaptive gain and filter circuit 64. In one illustrative embodiment, the ADC circuit 62 is a 10-bit analog-to-digital converter such that the full count range is 1024 (e.g., 210), although the ADC circuit 62 may alternatively have more or fewer bits of resolution.
The ADC circuit 62 illustratively receives as another input the enable signal, E, produced by the comparator 58, and the ADC circuit 62 is therefore operable to convert analog signals to digital signals only when the enable signal, E, is activated, e.g., when the value of VIN is sufficiently less than the value of VE1 so as to cause E to assume its activated state or is sufficiently greater than the value of VE2 so as to cause E to assume its activated state. Conversely, when the enable signal, E, is deactivated, e.g., when the value of VIN is sufficiently greater than the value of VE1 so as to cause E to assume its deactivated state or when the value of VIIN is sufficiently less than the value of VE2 so as to cause E to assume its deactivated state, the ADC circuit 62 is disabled and therefore not operable to convert analog signals to digital signals. Under such conditions, the output of the APC unit 50 should not affect operation of the adaptive charge controller 28 as the adaptive charge controller 28 will under such conditions be in an operating mode controlled by one of the other operating mode controlling units 42-48. The outputs of the ADC circuit 62 under such conditions may therefore be set to a default value that causes the output, VR (or VIR) of the ADM unit 52 to have no affect on the operation of the IDPM unit 54 and/or that causes the output of the IDPM unit 54 to have no affect on the operation of the adaptive charge controller 28.
The filter portion of each adaptive gain and filter circuit 60, 64 is illustratively provided to remove any noise or ripple that the analog input signal(s) VIN and/or VIIN may contain. In this regard, the filter portion in one illustrative embodiment of each adaptive gain and filter circuit 60, 64 is a conventional low-pass filter. However, this disclosure contemplates that the filter portions of the adaptive gain and filter circuits 60, 64 may alternatively or additionally include one or more other known types of signal filtering circuits. Illustratively, the filter portion of each adaptive gain and filter circuit 60, 64 is located at the front end of each circuit 60, 64 such that any gain applied by the circuits 60, 64 is applied to the filtered signal(s). By way of designation, the filtered analog input signals will be referred to herein as F(VIN) and F(VIIN) respectively.
The adaptive gain portion of each adaptive gain and filter circuit 60, 64 is illustratively configured to apply (e.g., as a multiplier) an adaptively determined gain to the filtered analog input signals F(VIN) and F(VIIN) such that each resulting adjusted analog signal VA, VIA has a value that falls within a window defined by predefined low and high values. For purposes of illustrating operation of the adaptive gain and filter circuits 60, 64, the gain applied by the adaptive gain and filter circuit 60 to the filtered analog signal F(VIN) will be designated herein as G60 and the gain applied by the adaptive gain and filter circuit 64 to the filtered analog signal F(VIIN) will be designated herein as G64. Thus, in accordance with these designations, VA=G60*F(VIN) and VIA=G64*F(VIIN).
Each of the adaptive gain and filter circuits 60, 64 is illustratively designed to compare the respective output of the ADC circuit 62 with the predefined low and high values, and to lower the value of its gain if the value of the respective output of the ADC circuit 62 is greater than the predefined high value and to raise the value of its gain if the value of the respective output of the ADC circuit 62 is less than the predefined low value. It will be understood that one or both of the low and high values used for the adaptive gain and filter circuit 60 may or may not be the same as those used for the adaptive gain and filter circuit 64, and that this disclosure contemplates that such low and high values may be selected in various different ways. It will further be understood that the circuits 60, 64 may be configured to raise and lower its respective gain value by the same or different amount, and that within each circuit the amount by which the gain is raised may or may not be the same as the amount by which the gain is lowered. This disclosure contemplates that the amount by which either or both of the circuits 60, 64 raises and/or lowers its respective gain value may vary between applications.
In one illustrative example of the adaptive gain portions of the adaptive gain and filter circuits 60, 64, the predefined low value for each circuit 60, 64 is 25% of the full range of the ADC circuit 62 (i.e., the maximum count value of the ADC circuit 62) and the predefined high value for each circuit 60, 64 is 75% of the full range of the ADC circuit 62, and the amount by which each gain value G60 and G64 is raised or lowered is ½ of the current gain value. Using as an example a 10-bit ADC circuit 62, the full range of such an ADC circuit 62 is 1024. The predefined low value is therefore (0.25*1024)=256, and the predefined high value is (0.75*1024)=768. In this example implementation of the adaptive gain and filter circuits 60, 64, each circuit 60, 64 thus operates identically by comparing the count value of VA and VIA respectively to 256 and 768. If the count value of VA is less than 256, the gain value G60 is doubled (e.g., G60=2*G60), and if the count value of VIA is less than 256 the gain value G64 is likewise doubled (e.g., G64=2*G64). If the count value of VA is instead greater than 768, the gain value G60 is halved (e.g., G60=G60/2), and if the count value of VIA is greater than 768 the gain value G64 is likewise halved (e.g., G64=G64/2). If instead either count value VA or VIA is between 256 and 768, the corresponding gain value G60 or G64 respectively is not changed. This process continues until both VA and VIA are between the predefined low and high values, e.g., 256 and 768 respectively. It will be understood that this particular implementation is provided only by way of example, and should not be considered to be limiting in any way.
The digital multiplier circuit 66 may be conventional and is operable to multiply the digital signal VAD and VIAD to produce at an output of the multiplier circuit 66 an input power, PIN=VAD*VIAD, which represents the electrical power received by the charge control unit 12 (i.e., the electrical power produced by the AC adapter 16). The input power, PIN, is provided as an input to a store and compare circuit 68. The store and compare circuit 68 illustratively includes a one or more memory registers which store therein the most recent value of the input power, PIN. The store and compare circuit 68 further includes conventional comparison circuitry, e.g., one or more conventional comparators, configured to compare the current value of the input power, PIN, with the stored value of PIN. The store and compare circuit 68 further includes conventional circuitry which determines a step value, e.g., a step size based on the difference between the current and stored values of PIN, and a direction, e.g., one of two values based on whether the current value of PIN is greater or less than the stored value of PIN. The step value determination may or may not be weighted, and may be a simple arithmetic difference or include a more complex difference determination. In any case, the step and direction values produced at an output of the store and compare circuit 68 are provided as an input to a conventional digital-to-analog converter (DAC) circuit 70 which converts the current step and direction values to a current value of the reference control signal, e.g., reference control voltage, VR, or reference control current, IR, e.g., in the form a voltage VIR as described hereinabove with respect to
The IDPM circuit 54 is illustratively responsive to the reference control signal, VR or VIR, to produce control signals from which the PWM controller 40 controls the duty cycle of the control signals PWMI and/or PWMV as described hereinabove. Under conditions in which the electrical power demanded by the system load 20 or the combination of the system load 20 and the chargeable power source 22 is greater than that which can be produced by the AC adapter, controlling one or the other of VIN and IIN in this manner will necessarily cause the AC adapter 16 to produce the other of VIN or IIN in accordance with the particular characteristics of the AC adapter 16 being used, thereby controlling the input power to the charge control unit 12 (i.e., the output power produced by the AC adapter 16) to its maximum value. Illustratively, the DAC circuit 70 is configured using conventional circuitry to produce the reference control signal (VR or VIR) in a manner that gradually implements changes in the step value.
The store and compare circuit 68 is illustratively configured to determine the step value in accordance with one or more conventional input power maximization algorithms. In one embodiment, for example, the store and compare circuit 68 is configured to determine the step value using a conventional maximum power point tracking (MPPT) algorithm designed to move VR (or VIR) to a value which maximizes the input power, PIN, (i.e., the output power produced by the AC adapter 16). In one specific embodiment, the MPPT algorithm is illustratively implemented in the form of a conventional perturb-and-observe method, although this disclosure contemplates other embodiments in which the MPPT algorithm may be alternatively or additionally implemented using one or more other conventional MPPT algorithms such as a conventional incremental conductance method, a constant voltage method, or the like. Those skilled in the art will recognize that any modifications required to implement any such additional or alternate MPPT algorithm(s) would be a mechanical step for a person of ordinary skill in the art to which this disclosure pertains. In still other embodiments, the store and compare circuit 68 may alternatively be configured to determine the step value in accordance with other conventional maximum value determining techniques, examples of which may include, but are not limited to, one or more numerical hunting techniques, one or more conventional iterative techniques, or the like.
In one embodiment, at least the APM unit 52, including the maximum power value determining algorithm, is illustratively implemented entirely using analog circuitry. In another embodiment, the entire charge control unit 12 is implemented entirely using analog circuitry, and in still another embodiment the adaptive charge controller 28 is an entirely analog circuit fabricated on a single, monolithic integrated circuit (or “chip”). The structures and techniques described herein for extracting maximum electrical power from the AC adapter 16 are applicable to a wide range of electrical power sources including, but not limited to, solar panels and AC adapters having different voltage, current and/or power ratings than those described herein.
Referring now to
The time t5 ends the first complete set of events carried out by the APM unit 52. Referring again to
While one or more embodiments have been illustrated and described in detail in the foregoing drawings and description, the same is to be considered as illustrative and not restrictive in character, it being understood that only illustrative embodiments thereof have been shown and described and that all changes and modifications that come within the spirit of the invention are desired to be protected.
This application claims the benefit of, and priority to, U.S. Provisional Patent Application Ser. No. 61/452,819, filed Mar. 15, 2011, U.S. Provisional Patent Application Ser. No. 61/478,575, filed Apr. 25, 2011, and U.S. Provisional Patent Application Ser. No. 61/604,226, filed Feb. 28, 2012 the disclosures of which are each incorporated herein by reference.
Number | Date | Country | |
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61452819 | Mar 2011 | US | |
61478575 | Apr 2011 | US | |
61604226 | Feb 2012 | US |