Patent Grant
9588844
The invention relates generally to the field of fault tolerant computing and more specifically to checkpointing, networking and virtualization systems.
There are a variety of ways to achieve fault tolerant computing. Specifically, fault tolerant hardware and software may be used either alone or together. As an example, it is possible to connect two (or more) computers, such that one computer, the active computer or host, actively makes calculations while the other computer (or computers) is idle or on standby in case the active computer, or hardware or software component thereon, experiences some type of failure. In these systems, the information about the state of the active computer must be saved periodically to the standby computer so that the standby computer can substantially take over at the point in the calculations where the active computer experienced a failure. This method can be extended to the modern day practice of using a virtualized environment as part of a cloud or other computing system.
Virtualization is used in many fields to reduce the number of servers or other resources needed for a particular project or organization. Present day virtual machine computer systems utilize virtual machines (VM) operating as guests within a physical host computer. Each virtual machine includes its own virtual operating system and operates under the control of a managing operating system or hypervisor executing on the host physical machine. Each virtual machine executes one or more applications and accesses physical data storage and computer networks as required by the applications. In addition, each virtual machine may in turn act as the host computer system for another virtual machine.
Multiple virtual machines may be configured as a group to execute one or more of the same programs. Typically, one virtual machine in the group is the primary or active virtual machine and the remaining virtual machines are the secondary or standby virtual machines. If something goes wrong with the primary virtual machine, one of the secondary virtual machines can take over and assume its role in the fault tolerant computing system. This redundancy allows the group of virtual machines to operate as a fault tolerant computing system. The primary virtual machine executes applications, receives and sends network data, and reads and writes to data storage while performing automated or user initiated tasks or interactions. The secondary virtual machines have the same capabilities as the primary virtual machine, but do not take over the relevant tasks and activities until the primary virtual machine fails or is affected by an error.
For such a collection of virtual machines to function as a fault tolerant system, the operating state, memory and data storage contents of a secondary virtual machine must be equivalent to the operating state, memory and data storage contents of the primary virtual machine. If this condition is met, the secondary virtual machine may take over for the primary virtual machine without a loss of any data. To assure that the state of the secondary machine and its memory is equivalent to the state of the primary machine and its memory, it is necessary for the primary virtual machine periodically to transfer its state and memory contents, or at least changes to the memory contents since the last update, to the secondary virtual machine.
The periodic transfer of data to maintain synchrony between the states of the virtual machines is termed checkpointing. A checkpoint defines a point in time when the data is to be transferred. During a checkpoint, the processing on the primary virtual machine is paused, so that the final state of the virtual machine and associated memory is not changed during the checkpoint interval. Once the relevant data is transferred, both the primary and secondary virtual machines are in the same state. The primary virtual machine is then resumed and continues to run the application until the next checkpoint, when the process repeats.
Checkpoints can either be determined by the passage of a fixed amount of elapsed time from the last checkpoint or by the occurrence of some event, such as the number of memory accesses (termed dirty pages); the occurrence of a network event (such as network acknowledgement output from the primary virtual machine); or the occurrence of excessive buffering on the secondary virtual machine (as compared to available memory) during the execution of the application. Elapsed time checkpointing is considered fixed checkpointing, while event based checkpointing is considered dynamic or variable-rate checkpointing.
Checkpointing is a resource intensive operation that has different operating periods during which the demand for processing cycles increases, such that the demand is uneven between some of the periods. These processor demanding stages can result in increased network latency for out-bound traffic from the VM or other system being checkpointed. A need therefor exists for ways to reduce the cost of checkpoint processing during certain demanding periods and in turn reduce network latency of out-bound traffic.
Embodiments of the invention address this need and others.
In one aspect, the invention relates to a fault tolerant computing system. In one embodiment, the system includes a first computing device comprising a primary virtual machine and a second computing device comprising a secondary virtual machine, wherein the first computing device and the second computing device are in communication, wherein the primary virtual machine comprises a first checkpointing engine and a first network interface, wherein the secondary virtual machine comprises a second network interface, wherein the first checkpointing engine forwards a page of memory of the primary virtual machine to the secondary virtual machine such that the first checkpointing engine can checkpoint the page of memory without pausing the primary virtual machine. In another embodiment, the first computing device further includes a buffer cache in communication with the checkpointing engine; and a memory tracking module in communication with the checkpointing engine, wherein the buffer cache is configured to receive working set of memory pages and wherein the memory tracking module monitors the memory of the first computing device and identifies when an infrequently used memory page is modified relative to the working set of memory pages in the buffer cache. In yet another embodiment, the first computing device further comprises an I/O module in communication with a network interface and a block interface. In still yet another embodiment, the checkpointing engine pauses the primary virtual machine once a checkpoint is declared.
In one embodiment, the checkpointing engine captures the state of the paused primary virtual machine and restarts the paused primary virtual machine once the state is captured. In another embodiment, the checkpointing engine forwards a page of memory to the secondary virtual machine while the checkpointing engine is idle and the primary virtual machine is running.
In one aspect, the invention relates to a method of distributing checkpointing load in a virtual machine system. The method includes identifying a set of candidate pages for page forwarding based on at least one criterion of a set of criteria; selecting one or more of the candidate pages; and forwarding the candidate pages from a primary virtual machine to a secondary virtual machine while the primary virtual machine is running. In one embodiment, the set of criteria is that: the one or more candidate pages are not elements in a set of working memory, the one or more candidate pages were involved in a storage input or output transfer, and the one or more candidate pages were successfully forwarded during a previous VM operating cycle. In another embodiment, the selection of a candidate page is modified in response to the instruction in the primary virtual machine that modified the page of memory.
In one aspect, the invention relates to a method of reducing processing cycles during one or more high processor demand periods (capture, transfer, act-wait) of the checking pointing cycle. The method can also be implemented to reduce network latency of out-bound traffic in conjunction with alleviating processing demands during one or more high processor demand periods.
The structure and function of the invention can be best understood from the description herein in conjunction with the accompanying figures. The figures are not necessarily to scale, emphasis instead generally being placed upon illustrative principles. The figures are to be considered illustrative in all aspects and are not intended to limit the invention, the scope of which is defined only by the claims.
Detailed embodiments of the invention are disclosed herein, however, it is to be understood that the disclosed embodiments are merely exemplary of the invention, which may be embodied in various forms. Therefore, specific functional details disclosed herein are not to be interpreted as limiting, but merely as a basis for the claims and as a representative basis for teaching one skilled in the art to variously employ the invention in virtually any appropriately detailed embodiment.
In a variable-rate checkpoint system, an excessive checkpoint rate can occur when checkpoint cycles are initiated on the primary virtual machine in response to the occurrence of an event on the primary virtual machine such as outbound network data transmission or traffic or other events which result in a page of memory being modified. Normally, outbound traffic causes an immediate checkpoint cycle to ensure lower-latency exchanges between the primary virtual machine and the computer on the network receiving the transmission from the virtual machine. This is indeed the case for file-level operations such as folder enumeration, file deletion, attribute manipulation, and even single-threaded transaction exchanges.
On a checkpoint based system that monitors a running primary or guest virtual machine's memory page modifications to replicate those state changes to another system, significant latency can occur between the time a checkpoint is deemed necessary and the point at which the guest's out-bound network frames can be published or transmitted. This latency is a function of many factors such as memory speed, processor speed, interconnect speed, interconnect latency, and of course the number of guest pages which need to be delivered. The process of checkpointing a primary virtual machine often results in the pausing of its operations in order to initiate the checkpoint.
Checkpoint processing encounters significant processing demands during the time-critical portion of the cycle which includes the following steps:
The exact order of these steps may vary from one implementation to another, and may include fewer or more steps. However all implementations will have to deal with the transferring of memory pages, step 2 above. This transfer is where much of the checkpoint time and effort will be spent.
As noted herein, the process of checkpointing a primary virtual machine often results in the pausing of its operations in order to initiate the checkpoint. Various events can trigger a checkpoint as described herein. Unfortunately, given the various events which can declare a checkpoint, numerous pages of memory can require checkpointing.
These pages of memory can include the set of all pages modified between pause and run operations. This results in a distribution of memory pages per checkpoints that is uneven and results in increased delays for the primary virtual machine while the pages of memory are checkpointed.
According to one embodiment of the invention, it is desirable to even-out the distribution of memory pages and reduce the checkpointing load. This can be achieved by selecting pages unlikely to undergo further changes while a primary virtual machine is running for a period of time such as a page forwarding interval. These types of infrequently modified or dirtied pages can be forwarded for checkpointing while the virtual machine continues to run. This approach is in contrast with such infrequently modified or dirtied pages being checkpointed along with frequently modified pages while the VM is paused.
Memory page transfer time can be reduced by selectively using page forwarding with regard to suitable candidate pages as shown in
Referring to
The virtual machine 100 typically performs a set of core tasks and frequently accesses certain types of stored data. These core tasks and frequently used sets of data affect a certain set of memory pages or region of a given page of memory. This set of pages or regions effectively define a set of working memory which is characteristic of a given virtual machine. This working set is frequently changed and thus memory associated with it is routinely dirtied. In light of these changes, pages of memory in the working group are typically not suitable candidates for forwarding for checkpointing while the virtual machine is running. This follows because the pages of memory are likely to change before a checkpoint can be completed resulting in wasted processing and data exchanges.
Referring to
When the checkpointing engine 122 is idle, network data (if any) remains in a buffered state by 110, and will only be released after the next checkpoint reaches its Commit/Release stage (230). At that time, network data (if any) is transferred 134 from the I/O module to the network interface 118. When a checkpoint is declared, the virtual machine 100 is paused and the dirty page data is processed by the checkpointing engine 122. Referring to
In
As noted above, forwarding of a selected page of memory occurs in parallel with VM 100 executing or running. As a result, the forwarded page may not be the final version of the page. Further, because there is the possibility of further changes to a forwarded page, the checkpoint mechanism must have a means of detecting modifications that occur between the forwarded copy and the final page (at checkpoint time).
One way to detect modifications that occur between the forwarded page and the final page is to reset the dirty-bit associated with the page prior to copying it. This reset approach is coupled with flushing the page table entry from the processor's translation lookaside buffer (TLB). Then, at checkpoint time, the step of determining if the page has been modified again is performed. Another approach to detecting modifications that occur between the forwarded page and the final page is to keep a local copy of the forwarded page and use that copy for direct comparison at checkpoint time. In either case, the objective is to reduce the amount of guest page data that must be transferred at checkpoint time. In turn, this process reduces the latency of the checkpoint cycle and a primary virtual machine's network ‘Release’ shown as stage (230) in
As part of the process of distributing a portion of the checkpointing load while the primary virtual machine is still running, it is useful to identify or establish various categories of information and tasks that can be performed by the checkpointing engine or other components of a virtual machine. These tasks and categories of information include:
The benefit of page forwarding can be lost or reduced if those pages must be retransmitted again during the same checkpointing cycle. Hence, the selection of which pages to send is an important part of a successful implementation. A candidate for a forwardable page is evaluated to include at least one of these characteristics:
In more detail and referring to
A page of memory A, identified as forwardable based on compliance with one or more selection criteria, is forwarded while the primary VM is running. This occurs before a checkpoint is declared (210) during which the primary VM is paused. While the primary virtual machine is paused, the state of the primary virtual machine is captured (215). Once the state data is captured (215), the checkpointing engine resumes the primary virtual machine which again executes one or more applications.
The captured state data is then transferred (220) to the secondary virtual machine. The primary VM starts to run, leaving a paused state, in parallel with the Transfer state (220) or after the Transfer state (220) depending on implementation. During the states following the transfer (220) of the checkpoint data, page forwarding can occur as shown by the left-most arrows which bound the Transfer (220), the ACK (225), the Release (230), and the Idle (235) stages. Once the data has been transferred, the checkpointing engine waits for an acknowledgement (ACK) to be received 225 from the secondary virtual machine or agent thereof, indicating that the data has been received. At this point, the checkpoint data is released or committed (230), for example by releasing 134 a frame of buffered data to the network interface 118. The checkpointing engine next enters an Idle state (235) until the next checkpoint occurs. As shown in
In another embodiment, the checkpointing engine 122 working in concert with memory tracking 126 can inspect the instruction in virtual machine 100 at the time that a page is first modified. The type of instruction used to modify the page of memory may provide a hint to the intended use of the page. This hint can be used to determine if a page is a candidate for a forwardable page.
For example, in the x86 architecture, REP MOVS (repeat move string instruction) that writes an entire page to zero is commonly used to clear a page of memory prior to returning that page to the available memory pool. Such a page is a good candidate for a forwardable page. Conversely, a page modified using the XCHG (exchange) instruction is a poor candidate because the XCHG is commonly used to implement semaphores, implying that this page will be frequently modified.
Unless specifically stated otherwise as apparent from the following discussion, it is appreciated that throughout the description, discussions utilizing terms such as “processing” or “computing” or “calculating” or “delaying” or “comparing”, “generating” or “determining” or “forwarding or “deferring” “committing” or “checkpointing” or “interrupting” or “handling” or “receiving” or “buffering” or “allocating” or “displaying” or “flagging” or Boolean logic or other set related operations or the like, refer to the action and processes of a computer system, or electronic device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's or electronic devices' registers and memories into other data similarly represented as physical quantities within electronic memories or registers or other such information storage, transmission or display devices.
The algorithms presented herein are not inherently related to any particular computer or other apparatus. Various general purpose systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct more specialized apparatus to perform the required method steps. The required structure for a variety of these systems will appear from the description below. In addition, the present invention is not described with reference to any particular programming language, and various embodiments may thus be implemented using a variety of programming languages.
The aspects, embodiments, features, and examples of the invention are to be considered illustrative in all respects and are not intended to limit the invention, the scope of which is defined only by the claims. Other embodiments, modifications, and usages will be apparent to those skilled in the art without departing from the spirit and scope of the claimed invention.
In the application, where an element or component is said to be included in and/or selected from a list of recited elements or components, it should be understood that the element or component can be any one of the recited elements or components and can be selected from a group consisting of two or more of the recited elements or components. Further, it should be understood that elements and/or features of a composition, an apparatus, or a method described herein can be combined in a variety of ways without departing from the spirit and scope of the present teachings, whether explicit or implicit herein.
The use of the terms “include,” “includes,” “including,” “have,” “has,” or “having” should be generally understood as open-ended and non-limiting unless specifically stated otherwise.
It should be understood that the order of steps or order for performing certain actions is immaterial so long as the present teachings remain operable. Moreover, two or more steps or actions may be conducted simultaneously.
It is to be understood that the figures and descriptions of the invention have been simplified to illustrate elements that are relevant for a clear understanding of the invention, while eliminating, for purposes of clarity, other elements. Those of ordinary skill in the art will recognize, however, that these and other elements may be desirable. However, because such elements are well known in the art, and because they do not facilitate a better understanding of the invention, a discussion of such elements is not provided herein. It should be appreciated that the figures are presented for illustrative purposes and not as construction drawings. Omitted details and modifications or alternative embodiments are within the purview of persons of ordinary skill in the art.
The invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The foregoing embodiments are therefore to be considered in all respects illustrative rather than limiting on the invention described herein. Scope of the invention is thus indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are intended to be embraced therein.
This application claims priority to U.S. provisional patent application 61/921,730 filed on Dec. 30, 2013 and owned by the assignee of the current application, the contents of which are herein incorporated by reference in their entirety.
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