Patent Application
20240289054
This patent document claims the priority and benefits of Korean Patent Application No. 10-2023-0027146, filed at the Korean Intellectual Property Office on Feb. 28, 2023, the entire contents of which are incorporated herein by reference for all purposes.
Various embodiments of the present disclosure relate to a chiplet-based storage device and a method of transmitting control codes to a chiplet.
A storage device is a device capable of storing data based on a request from an external device such as a computer, a mobile terminal such as a smart phone or tablet, or various electronic devices.
The storage device may include a memory and a memory controller for controlling the memory. The memory controller may receive a command from the external device and perform or control operations for reading data from the memory, writing data to the memory/performing programming of data, or erasing data from the memory based on the received command.
Various embodiments of the present disclosure provide a method of transmitting control codes such as firmware of each chiplet in a memory controller having a chiplet-based structure.
The technical tasks to be achieved in the present disclosure are not limited to the technical tasks mentioned above, and other technical tasks not mentioned can be clearly understood by those of ordinary skill in the art to which the present disclosure belongs from the description below.
In one aspect, a memory controller includes a first chip (e.g., front-end chip 210) configured to perform a first operation of the memory controller, a plurality of second chips (e.g., back-end chip 220) configured to perform a second operation of the memory controller, a plurality of data links configured to connect the first chip and each of the plurality of second chips on a one-to-one basis and provide data transmission between the first chip and each of the plurality of second chips, a control link connected to the first chip and all the plurality of second chips and configured to transmit control codes for performing the second operation of the plurality of second chips, and a memory connected to the first chip and configured to store the control codes. In some implementations, the first chip may obtain the control code of the plurality of second chips from the memory, and transmit the control code to the plurality of second chips through the control link, and repeatedly transmit the control code until a reception completion message for the control code is received from all of the plurality of second chips.
In another aspect, a memory controller includes a first chip configured to perform a first operation of the memory controller, a second chip configured to perform a second operation of the memory controller, a third hip configured to perform a third operation of the memory controller, a first data link configured to connect the first chip and the second chip on a one-to-one basis and provide data transmission between the first chip and the second chip, a second data link configured to connect the first chip and the third chip on a one-to-one basis and provide data transmission between the first chip and the third chip, a control link connected to the first chip, the second chip, and the third chip to transmit a first control code for performing the second operation of the second chip and a second control code for performing the third operation of the third chip, and a memory connected to the first chip and configured to store the first control code and the second control code. In some implementations, the first chip may obtain the first control code and the second control code, and repeatedly transmit the first control code and the second control code through the control link.
In another aspect, a method of a memory controller includes obtaining, by a first chip included in the memory controller, a control code for performing an operation of a second chip included in the memory controller from a memory connected to the first chip, transmitting, by the first chip, the control code to all of a plurality of second chips connected through a control link, determining, by the first chip, whether a reception completion message indicating that the control code has been received from all of the plurality of second chips, and repeatedly transmitting, by the first chip, the control code to the plurality of second chips connected to the control link in response to a determination by the first chip that the reception completion message has not been received from at least one of the plurality of second chips.
Various embodiments of the present disclosure relate to a chiplet-based storage device and a method of transmitting control codes to a caplet. The memory controller is configured to support memory interfaces of various specifications, but in the case of using a conventional single skeleton integrated circuit or a single system-on-chip (SoC), there is a limit in supporting memory interfaces of various specifications. Some embodiments of the present disclosure provide a memory controller having a chiplet-based structure which can support memory interfaces of various specification.
Hereinafter, embodiments will be described with reference to the accompanying drawings. Herein, when it is mentioned that a component (or an area, a layer, a part, etc.) is “on”, “connected to”, or “coupled to” another component, it may mean that the component may be directly connected/coupled to the other component or a third component may be disposed therebetween.
Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.
Referring to
The memory 110 may operate in response to control of the controller 120. Here, the operation of the memory 110 may include, for example, a read operation, a program operation (also referred to as “write operation”), and an erase operation.
For example, the memory 110 may include various types of non-volatile memories, such as NAND flash memory, 3D NAND flash memory, NOR flash memory, resistive random access memory (RRAM), Phase-Change Memory (PRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), Spin Transfer Torque Random Access Memory (STT-RAM), or others.
The memory 110 may be implemented as a three-dimensional array structure. The embodiments of the present disclosure may be applied not only to a flash memory in which a charge storage layer is made of a conductive floating gate, but also to a charge trap flash (CTF) in which a charge storage layer is made of an insulating film.
The memory 110 may also include a plurality of chips or cores, and according to an embodiment, each of the plurality of chips may have a different interface for communication with the controller 120.
The memory 110 may receive a command, an address, and/or others from the controller 120 (also referred to as a memory controller), and access a region of a memory cell array selected by the address. Thus, the memory 110 may perform an operation indicated by a command on the region selected by the address.
For example, the memory 110 may perform at least one of a program operation, a read operation, or an erase operation. During a program operation, the memory 110 may program data in the region selected by the address. During a read operation, the memory 110 may read data from the region selected by the address. During an erase operation, the memory 110 may erase data stored in the region selected by the address.
The controller 120 may control program (write), read, erase, and background operations with respect to the memory 110. Here, the background operation may include one or more of Garbage Collection (GC), Wear Leveling (WL), Read Reclaim (RR), or Bad Block Management (BBM) operations.
The controller 120 may control an operation of the memory 110 according to a request from an external device (e.g., a host) located outside the storage device 100. The operation of the memory 110 may be controlled according to a request from the host. In some other embodiments, the controller 120 may control an operation of the memory 110 regardless of a request from an external device.
The external device may include a computer, a UMPC (Ultra Mobile PC), a workstation, a PDA (Personal Digital Assistant), a tablet, a mobile phone, a smart phone, an e-book, a PMP (portable multimedia player), a portable game machine, a navigation device, a black box, a digital camera, a DMB (Digital Multimedia Broadcasting) player, a smart television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a storage constituting a data center, one of various electronic devices constituting a home network, one of various electronic devices constituting a computer network, one of various electronic devices constituting a telematics network, a radio frequency identification (RFID) device, a mobility device (e.g., vehicle, robot, drone) that travels on the ground, water, or air under human control or autonomously travels, or others.
The external device may include at least one operating system (OS). The operating system may generally manage and control functions and operations of the external device, and provide mutual operation between the external device and the storage device 100. The operating system may be classified into a general operating system and a mobile operating system according to the mobility of an external device.
The controller 120 and an external device may be separate devices. In some cases, the controller 120 and the external device may be implemented as an integrated device. Hereinafter, for convenience of description, a description will be given by taking, as an example, a case in which the controller 120 and an external device are separate devices will be described.
Referring to
The host interface 121 may provide an interface for communication with an external device. For example, the host interface 121 may include an interface using at least one of various interface protocols such as a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnection (PCI) protocol, a PCI-express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial-ATA protocol, a parallel-ATA protocol, an SCSI (small computer small interface) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a system management bus (SMBus) protocol, an inter-integrated circuit (I2C) protocol, an improved inter-integrated circuit (I3C) protocol, a proprietary protocol, or others.
The memory interface 122 may be connected to the memory 110 to provide an interface for communication with the memory 110. That is, the memory interface 122 may be configured to provide an interface between the memory 110 and the controller 120 in response to control by the control circuit 123.
The control circuit 123 may receive a command through the host interface 121 and perform an operation for processing the received command.
The control circuit 123 may control the operation of the memory 110 by performing overall control operations of the controller 120. To this end, according to an embodiment, the control circuit 123 may include a processor 124, and may also include a working memory 125 and/or an error detection and correction circuit (ECC Circuit) 126 optionally.
The processor 124 may control overall operation of the controller 120.
The processor 124 may communicate with an external device through the host interface 121 and communicate with the memory 110 through the memory interface 122.
The processor 124 may perform a function of a Flash Translation Layer (FTL). The processor 124 may translate a logical address provided by an external device into a physical address through a flash translation layer (FTL). The flash translation layer may receive a logical address and translate the logical address into a physical address using a mapping table. Here, the logical address and the physical address may be a logical block address or a physical block address representing one memo area.
There are several methods for address mapping of the flash translation layer according to mapping units. Representative address mapping methods may include a page mapping method, a block mapping method, and a hybrid mapping method.
The processor 124 may randomize data received from an external device. For example, the processor 124 may randomize data received from an external device using a set randomizing seed. The randomized data may be provided to the memory 110 and programmed in the memory 110.
The processor 124 may de-randomize data received from the memory 110 during a read operation. For example, the processor 124 may derandomize data received from the memory 110 using a de-randomizing seed. The de-randomized data may be output to the external device.
The processor 124 may perform background functions for the memory 110 such as a garbage collection (GC) function, a wear leveling (WL) function, and a bad block management function.
The garbage collection function may refer to a function of collecting pieces of data partially recorded in memory blocks and moving and recording the data to and in another memory block in order to secure a free space to record data when there is not enough space to record data in the memory 110.
The wear leveling function may be a function for evenly writing data to all memory blocks of the memory 110 to prevent excessive use of a specific block in order to prevent errors and data loss of the memory 110 in advance and improve durability and stability of a product.
The bad block management function may be a function of detecting a bad block in the memory 110 and, when there is a reserved block, preventing data from being written to the bad block by replacing the bad block with the reserved block.
The processor 124 may control the operation of the controller 120 by executing firmware. In other words, the processor 124 may control overall operations of the controller 120 and execute (drive) firmware stored in the working memory 125 during booting. Hereinafter, the operation of the storage device 100 to be described in the embodiments of the present disclosure may be implemented in a manner in which the processor 124 executes firmware in which a corresponding operation is defined.
The firmware is a program executed in the storage device 100 to drive the storage device 100 and may include various functional layers. For example, the firmware may include binary data in which a code for executing each of the above-described functional layers is defined.
For example, the firmware may include a flash translation layer that performs a translation function between a logical address for transmission from an external device to the storage device 100 and a physical address of the memory 110, a host interface layer (HIL) that interprets a command received from an external device through the host interface 121 and transfers the command to a flash translation layer, and a flash Interface layer (FIL) that transfers a command instructed by the flash translation layer to the memory 110.
Also, the firmware may include a garbage collection function, a wear leveling function, and a bad block management function.
The firmware may be loaded into the working memory 125 from, for example, the memory 110 or a separate non-volatile memory (e.g., ROM, NOR Flash) located outside the memory 110. When executing a booting operation after power-on, the processor 124 may first load all or part of the firmware into the working memory 125.
The processor 124 may perform logic operations defined in firmware loaded into the working memory 125 to control the overall operation of the controller 120. The processor 124 may store a result of performing the logic operation defined in the firmware in the working memory 125. The processor 124 may allow the controller 120 to generate a command or a signal according to the result of performing the logic operation defined in the firmware. When the part of the firmware in which the logical operation to be performed is defined is not loaded into the working memory 125, the processor 124 may generate an event (e.g., interrupt) for loading the corresponding part of the firmware into the working memory 125.
The processor 124 may load meta data required to drive the firmware from the memory 110. The meta data is data for managing the memory 110 and may include management information about user data stored in the memory 110.
The firmware may be updated while the storage device 100 is being produced or the storage device 100 is running. The controller 120 may download new firmware from the outside of the storage device 100 and update existing firmware to new firmware.
The working memory 125 may store firmware, program codes, commands, or data required to drive the controller 120. The working memory 125 is, for example, a volatile memory, and may include one or more of static RAM (SRAM), dynamic RAM (DRAM), and synchronous DRAM (SDRAM).
An error detection and correction circuit 126 may detect an error bit of target data using an error correction code and correct the detected error bit. Here, the target data may be, for example, data stored in the working memory 125 or data read from the memory 110.
The error detection and correction circuitry 126 may be implemented to decode data with an error correction code. The error detection and correction circuitry 126 may be implemented with a variety of decoders. For example, a decoder performing non-systematic decoding or a decoder performing systematic decoding may be used.
For example, the error detection and correction circuitry 126 may detect an error bit in units of sectors set for each read data. That is, each read data may be composed of a plurality of sectors. A sector may refer to a data unit smaller than a page, which is a read unit of a flash memory. Sectors constituting each read data may be associated with each other through addresses.
The error detection and correction circuit 126 may calculate a bit error rate (BER) and determine whether correction is possible in units of sectors. For example, when the bit error rate (BER) is higher than a set reference value, the error detection and correction circuit 126 may determine that a corresponding sector is uncorrectable or fail. On the other hand, when the bit error rate (BER) is lower than the reference value, the error detection and correction circuit 126 may determine that a corresponding sector is correctable or pass.
The error detection and correction circuit 126 may perform error detection and correction operation on all pieces of read data, sequentially. When a sector included in read data is correctable, the error detection and correction circuit 126 may omit an error detection and correction operation for a corresponding sector of next read data. When the error detection and correction operation has been performed on for all pieces of read data, the error detection and correction circuit 126 may detect sectors finally determined to be uncorrectable. The number of sectors determined to be uncorrectable may be one or more. The error detection and correction circuit 126 may transfer information (e.g., address information) on sectors determined to be uncorrectable to the processor 124.
The bus 127 may be configured to provide a channel between the components 121, 122, 124, 125, and 126 of the controller 120. The bus 127 may include, for example, a control bus for transferring various control signals, commands, and/or others, and a data bus for transferring a variety of data.
On the other hand, some of the aforementioned components 121, 122, 124, 125, and 126 of the controller 120 may be deleted, or the aforementioned components 121, 122, 124, 125, and 126 of the controller 120 may be integrated into one component. In some cases, one or more other components may be added in addition to the above-described components of the controller 120.
Referring to
Although only two back-end chips 220 are shown in
In an embodiment, the front-end chip 210 may be a chip including the host interface 121, the processor 124, the error detection and correction circuit 126, and/or others of
The front-end chip 210 and the back-end chips 220 may be configured in a chiplet structure. The front-end chip 210 and the back-end chips 220 may have physically-separated chip structures so as to function independently of each other, and may transmit data and signals through a bus between the chips. In general, the external device 150 may operate at a higher speed than the memory 110. Accordingly, the front-end chip 210 may be configured to support high-speed communication with the external device 150. On the other hand, the back-end chips 220 may be configured to support low-speed communication with the memory 110. According to various embodiments of the present disclosure, “high speed” and “low speed” are merely used to express a relative speed difference, and do not mean absolute speeds.
The front-end chip 210 may include a host interface 121 for communication with a host device. Also, the front-end chip 210 may also include links 230 and 240 for communication with the back-end chips 220. The back-end chips 220 may include links 230 and 240 for communication with the front-end chip 210, respectively.
The controller 120 with the chiplet-based structure as described above may flexibly replace the back-end chips 220 according to an interface of the memory 110 connected thereto, and also flexibly replace only the front-end chip 210 according to a host interface supported by the external device 150, thus resulting in a controller structure capable of flexibly responding to various requirements.
Referring to
The data link 230 may be used to transmit data to be written to or read from the memory 110 and to transmit related control data during normal operation of the controller 120. The normal operation may refer to an operation of the memory controller, which is performed after booting.
The control link 240 may be used to transmit a control code such as firmware for normally operating the functions of the back-end chip 220 when the controller 120 is newly powered and booted and may not be used after booting is completed. The front-end chip 210 may read firmware for the back-end chip 220 stored in a non-volatile memory 250 and transmit the firmware to the back-end chip 220 via the control link 240 and the back-end chip 220 may execute the firmware received via the control link 240, so that booting is completed.
In an embodiment, the control link 240 may connect the front-end chip 210 and all the back-end chips 220 using a single physical line. In addition, in an embodiment, the control link 240 may be implemented as one-way communication means via which only the front-end chip 210 is able to transmit data and all of the back-end chips 220 are able to only receive a control code. However, this is only one embodiment, and other embodiments are also possible. Thus, in another embodiment, the control link 240 may be implemented to enable bi-directional communication, which may increase implementation complexity and protocol complexity in the case of transmitting a control code.
In
Referring to
Referring to
In addition, the front-end chip 210 may require additional control to transmit data after identifying whether the back-end chips 220a and 220b to which the front-end chip 210 is to transmit data are ready to receive data. Additionally, the back-end chips 220a and 220b may require logic to determine whether the control code currently being received is for the back-end chip 220a or 220b itself or for another back-end chip. Accordingly, additional control may be required for synchronization between the front-end chip 210 and the back-end chips 220a and 220b.
Due to the need for such additional control, the control link 240 between the front-end chip 210 and the back-end chips 220a and 220b may need to perform bi-directional communication as shown in
In the example of
Referring to
In the example of
The front-end chip FE may determine whether the message indicating that control code reception is completed has been received from all back-end chips BE at the time of completion of first control code transmission (610), and repeatedly transmit the control code when the message indicating that control code reception is completed is not received from all back-end chips BE (615). In addition, when the message indicating that control code reception is completed is received from all back-end chips BE, the process may be terminated without additional transmission of control codes.
In an embodiment, the front-end chip FE may limit the number of times the control code is transmitted or may limit the control code to be repeatedly transmitted only for a preset period of time. In addition, the back-end chip that has not completed receiving the control code within the limited period of time or within the limited number of times may be determined to be in an abnormal state. In this case, the back-end chip may not be used during normal operation of the memory controller. In some embodiments, an alarm indicating the abnormal state of the second-end chip may be provided to a user.
The example of
Referring to
In the example of
The front-end chip FE may determine whether a code reception completion message is received from all of the back-end chips BE that are supposed to receive the second control code when the first transmission of the first control code is completed at 710, and when the code reception completion message is not received from all of the back-end chips BE that are supposed to receive the second control code, transmit the second control code at 712. In addition, the front-end chip FE may determine whether the code reception completion message is received from all of the back-end chips BE that are supposed to receive the first control code when the first transmission of the second control code is completed at 712, and when the code reception completion message is not received from all of the back-end chips BE that are supposed to receive the first control code, repeat the transmission of the first control code at 714. When the code reception completion message is received from all of the back-end chips BE that are supposed to receive the first control code, the front-end chip FE may transmit the second control code without additional transmission of control codes according to the determination of whether the message indicating that code reception completion message is received from all of the back-end chips BE. Similarly, the front-end chip FE may determine whether a code reception completion message is received from all of the back-end chips BE that are supposed to receive the second control code when the transmission of the first control code is completed at 714, and when the code reception completion message is not received from all of the back-end chips BE that are supposed to receive the control code, again transmit the second control code at 716. When the code reception completion message is received from all of the back-end chips BE that are supposed to receive the second control code, the front-end chip FE may transmit the first control code without additional transmission of control codes according to the determination of whether the code reception completion message is received from all of the back-end chips BE. The above-described operation may be terminated without additional transmission when the back-end chips BE to use control codes have received all the control codes.
Although it is described to separately manage and control the first control code and the second control code in the example of
When a plurality of control codes including a first control code and a second control code needs to be transmitted, a method shown in
Referring to
In the example of
After the second transmission of the first control code, the front-end chip FE may determine that a code reception completion message is received from all back-end chips BE #1 and BE #3 using the first control code, and repeatedly transmit a second control code (814, 816).
The back-end chip BE #2 and the back-end chip BE #4 are already ready before the first transmission of the second control code at 814, so that the back-end chip BE #2 and the back-end chip BE #4 may receive the entire second control code during the same time period 830 and transmit a code reception completion message 835 or 855.
When a back-end chip transmits a code reception completion message through the data link 230, the front-end chip FE is able to transmit the second control code at the second time at 816 as shown in
Referring to
When all back-end chips use the same control code as in the embodiment of
When back-end chips use different control codes as in the embodiment of
Referring to
In operation S1020, the front-end chip 210 may transmit the control code to all of the back-end chips 220.
In operation S1030, the front-end chip 210 may determine whether a reception completion message indicating that the control code has been received are received from all of the back-end chips 220.
When a result of the determination in operation S1030 determines that the reception completion message has not been received from at least one of the back-end chips 220, the front-end chip 210 may return to operation S1020 and then transmit the control code again. When a result of the determination in operation S1030 determines that the reception complete message has been received from all of the back-end chips 220, transmission of the control code to the back-end chips 220 may be completed.
Referring to
The front-end chip FE may transmit indexes (second index and first index) and data for each clock. In the case of the first control code, the front-end chip FE may transmit K+1 indexes and data to all back-end chips through the control link 240 using K+1 clocks. In the case of the first control code, the front-end chip FE may transmit M+1 indexes and data to all back-end chips through the control link 240 using M+1 clocks.
In operation S1120, the back-end chip BE may receive the control code, extract an index and data included in the control code obtained at each clock, determine whether the index is within the index area to be received set in operation S1010, and store data when the index is within the index area to be received.
In an embodiment, when the back-end chip BE is in a receivable state while the front-end chip FE is transmitting a control code, the back-end chip BE may receive and store the control code from the middle of the index area. For example, when the index area to be received by the back-end chip is 0 to 100, a control code may be stored from the index 45. When the front-end chip FE transmits a control code such that the index increases monotonically, the back-end chip BE may receive and store a control code from 45 to 100. Then, the back-end chip BE receives the control code from 0 to 44 when the front-end chip FE transmits the control code again from the index 0.
In operation S1130, the back-end chip BE may determine whether data of all indexes within the index area has been received. When it is determined that data of all indexes has not been received, the back-end chip BE may return to operation S1120 and continue to receive the control code. When it is determined that data of all indexes has been received, the back-end chip BE may transmit a code reception completion message in operation S1140. In an embodiment, the back-end chip BE has performed booting using the received and stored control code and then transmits a message indicating that the back-end chip BE is ready to the front-end chip FE. In this case, such message indicating that the back-end chip BE is ready can be considered as the code reception completion message.
In an embodiment, in a case where the back-end chip stores data from index 45, when the back-end chip receives the control code of index 44 and stores data, that is, when the back-end chip stores data at the same index as the value obtained by subtracting one from an initial index, the back-end chip may determine that control code reception is completed. The back-end chip BE may determine whether control code reception is completed in various other ways. In one embodiment, when a parity check code is added to the control code to secure data integrity, the back-end chip BE may perform a parity check and when the parity check is passed, determine that control code reception is completed.
As described above, some embodiments of the present disclosure provide a method for each chiplet to efficiently obtain a control code such as firmware in a chiplet-based memory controller.
In some embodiments, the present disclosure provides transmission of control codes by connecting a front-end chip and a back-end chip using only one line in terms of hardware.
In some embodiments of the present disclosure, a control code may be transmitted only through data transmission in one direction from the front-end chip to the back-end chip through a single line as described above.
Some embodiments of the present disclosure provide a method of arbitrarily transmitting a control code without any additional controls, such as the front-end chip determining whether the back-end chip is able to receive data or synchronizing with the back-end chip, and without any state information on the back-end chip.
Some embodiments of the present disclosure provide a method by which the back-end chip simply receives a control code without complicated control.
Accordingly, it is possible to minimize the number of lines for transmitting a control code to a plurality of back-end chips.
In addition, some embodiments of the present disclosure can reduce complexity and increase a speed by minimizing synchronization overhead in transmitting a control code from a front-end chip to a plurality of back-end chips.
Although a chiplet-based structure and a method for transmitting a control code (firmware) in the chiplet-based structure have been described based on a memory controller of a storage device, it is noted that the above description can be equally applied to any electronic device implemented with a chiplet-based structure.
In the above description, chips having the chiplet-based structure have been referred to as a front-end chip and a plurality of back-end chips, but the embodiments of the present disclosure can be applied to various chips without being limited thereto. For example, the method of transmitting a control code (firmware) proposed in the present disclosure can be effectively used or applied even when the front-end chip is generally called a first chip performing a first operation and the back-end chip is generally called a second chip performing a second operation.
According to various embodiments of the present disclosure, it is possible to reduce the number of input/output pins required to transmit a control code to each chiplet, and optimize complexity and speed for control code transmission.
While this patent document contains many specifics, these should not be construed as limitations on the scope of any subject matter or of what may be claimed, but rather as descriptions of features that may be specific to particular embodiment of particular techniques. Certain features that are described in this patent document in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.
Only a few implementations and examples are described and other implementations, enhancements and variations can be made based on what is described and illustrated in this patent document.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2023-0027146 | Feb 2023 | KR | national |
