The present invention relates to signal processing and is particularly applicable but not limited to circuits for amplifying amplitude and phase modulated signals.
The communications revolution of the 1990's has led to an increasing need for further and better means of transporting both data and voice communications. One offshoot of this revolution has been the burgeoning growth in wireless communications as more and more data is being transmitted by wireless means. For wireless handsets, wireless PDAs (personal digital assistants), and other wireless devices, one overarching concern is power consumption—the less power a device consumes the more desirable it is. To this end, higher efficiency components, such as amplifiers, are desirable in these wireless devices.
One type of architecture which was used in the past but has fallen out of recent favor is the so called Chireix architecture. First suggested by Henry Chireix in 1935, the technique also known as “outphasing” involves separately phase modulating two signals and recombining them in a combiner or combining network. By judiciously adjusting the phase modulation of the two signals, the combined resulting signal can become amplitude modulated as well as phase modulated. This technique enables the use of saturated amplifiers or switching amplifiers for amplitude modulated signals.
Also called “ampliphase” by the RCA Corporation when used in some of their radio transmitters, the technique has recently fallen out of favor due to its seeming inapplicability when amplifying signals. Previous attempts used common forms of linear and saturating amplifiers such as Class A and Class AB amplifiers to try and amplify the two signals prior to their being combined. Unfortunately, these efforts have yielded unacceptable results as the resulting circuits were found to be insufficiently efficient. A Chireix based architecture, if properly working with sufficient efficiency, would offer advantages in not only power consumption but in other areas as well.
Based on the above, there is a need for, methods or circuits which overcome or at least mitigate the drawback of the prior art. Such a solution should provide the advantages of a Chireix or outphasing architecture while providing sufficient amplification efficiency to be useful.
The present invention provides circuits and methods for use in amplifying amplitude and phase modulated signals. A circuit uses a combiner with dual parallel signal amplifiers feeding it. The signal amplifiers have a low output impedance while the combiner does not provide any isolation between its inputs from the signal amplifiers. As in other Chireix architectures, the signals from the signal amplifiers are phase modulated prior to being fed to the combiner. The combiner then combines these two signals and, depending on how these two signals are phase modulated, the resulting output of the combiner is amplitude modulated as well as phase modulated. The signal amplifiers may be Class D or Class F amplifiers to provide high efficiency amplification of the signals.
In a first aspect, the present invention provides a circuit for providing amplification to signals, the circuit comprising:
In a second aspect, the present invention provides a circuit for providing amplification to signals, the circuit comprising:
A better understanding of the invention will be obtained by considering the detailed description below, with reference to the following drawings in which:
Referring to
As in well known Chireix architectures, the signals received and amplified by the signal amplifiers 20a, 20B are phase modulated signals. These phase modulated signals, after being amplified by the signal amplifiers 20A, 20B, are combined or added by the combiner 30 to result in the output signal 40. By judiciously phase modulating the signals using appropriate phase modulators (not shown), the resulting signal 40 from the addition of the two signals is an amplitude modulated signal. Not only that, but the resulting signal is, in effect, an amplified version of a phase and an amplitude modulated signal.
It should be noted that similar architectures as that illustrated in
The dynamic nature of the load impedance is a result of the appropriate combiner for a Chireix architecture. Such an appropriate combiner not only reinserts the amplitude modulation to the resulting signal 40, it also provides a dynamic adjustment of the load impedance presented to each one of the signal amplifiers. This outphasing adjustment of the load impedance is such that the DC current through each signal amplifier decreases as the combined output amplitude decreases thereby maintaining high efficiency.
Two appropriate combiners are illustrated in
Another appropriate combiner is a modified Wilkinson combiner 110 as illustrated in
Regarding a proper choice of amplifiers for use in the block diagram of
As is known, Class F amplifiers provide a good approximation to a voltage square-wave across the output terminals of a device by “shorting” all even-harmonic voltages and “supporting” all odd-harmonic voltages. As a result, the voltage waveform across the output terminals of a device contains only odd-harmonic components. In addition, this sorting of odd- and even-harmonics results in a current passing through the output terminals of the device that contains the fundamental, and only even-harmonic components.
This “shorting” and “supporting” of harmonics is conveniently achieved with a shorted quarter-wave shunt-stub connected across the device's output terminals, a shown in
In a practical situation, with a stub effectively shorting only the second harmonic voltage, and passing only the fundamental and third harmonic voltage, the power-added efficiency can be more than 85%.
As an example of a Class D amplifier which may be used with the invention,
For such Class D (voltage switching) amplifiers, the active device passes no current between its output terminals when the voltage across its output terminals is at the voltage rail, and passes maximum current between its output terminals when the voltage across its output terminals is zero. As a result, the device does not absorb any power, and all power taken from the bias supply is converted into the output signal (100% power-added efficiency).
It should be noted that the amplifiers in the amplifier pair 20A, 20B in
It should also be noted that while the circuit of
A person understanding this invention may now conceive of alternative structures and embodiments or variations of the above all of which are intended to fall within the scope of the invention as defined in the claims that follow.
Number | Name | Date | Kind |
---|---|---|---|
2220201 | Bliss | Nov 1940 | A |
2624041 | Evans | Dec 1952 | A |
3170127 | Cramer | Feb 1965 | A |
3919656 | Sokal et al. | Nov 1975 | A |
5621351 | Puri et al. | Apr 1997 | A |
6133788 | Dent | Oct 2000 | A |
6285251 | Dent et al. | Sep 2001 | B1 |
6930547 | Chandrasekaran et al. | Aug 2005 | B2 |
Number | Date | Country |
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0011464 | May 1980 | EP |
S55-102906 | Aug 1980 | JP |
08204507 | Dec 1982 | WO |
Number | Date | Country | |
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Parent | 10272725 | Oct 2002 | US |
Child | 11648698 | US |