Chopper type comparator

Abstract

The present invention provides a logic circuit comprising a first power terminal, a second power terminal set at a higher potential than the first power terminal, a first FET of a first conductivity having a current path coupled to the first power terminal, a second FET of a second conductivity having a current path coupled to the second power terminal, and an input terminal commonly coupled to gate terminals of the first and second FETs, the first FET and the second FET having a relationship expressed approximately by the following equation: ##EQU1## where R.sub.S is a resistance of a resistor element parasitically produced between the first power terminal and the current path of the first FET. R.sub.D is a resistance of a resistor element parasitically produced between the second power terminal and the current path of the second FET, W.sub.N is a channel width of the first FET, W.sub.P is a channel width of the second FET, L.sub.N is a channel length of the first FET, L.sub.P is a channel length of the second FET, .mu..sub.N is a first carrier mobililty of the first FET, and .mu..sub.P is a second carrier mobility of the second FET.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an inverter and a chopper type comparator using the same, and, more particularly, to a technique of making the layout of a power source of an analog circuit in a semiconductor integrated circuit and setting a circuit constant.

2. Description of the Related Art

A description will be given below of a chopper type comparator for typical use in conventional A/D comparators. FIG. 3 exemplifies the use of a chopper type comparator. In this diagram, reference numeral 1 denotes the main part of a chopper type comparator, reference numeral 2 a sample and hold circuit of the comparator, Q.sub.1 and Q.sub.2 N and P channel field effect transistors (IG-FET) which constitute an inverter 3, Q.sub.3 and Q.sub.4 feedback switching transistors, V.sub.DD and V.sub.SS power sources, C a capacitor, SW1 and SW2 switches whose switching operations are controlled by signals .phi. and .phi., V.sub.ref a reference voltage, and A.sub.in a comparator input.

Referring to FIG. 3, the switch SW1 on the A.sub.in side and the feedback switches Q.sub.3, Q.sub.4 of the inverter 3 are turned ON to accumulate charges in the capacitor C. Since the inverter 3 has its input and output short-circuited at this time, the potential at the point A equals a threshold value V.sub.C of the inverter 3. The charges Q accumulated in the capacitor C can therefore be given by:

Q=(V.sub.C -A.sub.in) C (1) Then, the switches SW1, Q.sub.3 and Q.sub.4 are turned OFF and the switch SW2 on the V.sub.ref side is turned ON. As the amount of charges accumulated in the capacitor C does not vary, with V.sub.A being the potential of the point A, the following can be derived: Q=(V.sub.A -V.sub.ref) C (2)

From equations (1) and (2), we can attain:

V.sub.A =V.sub.C +(V.sub.ref -A.sub.in) (3)

FIG. 4 illustrates the input-output characteristic of a typical inverter. The point where the linear line V.sub.in =V.sub.out intersects the characteristic curve is the threshold value V.sub.C of the inverter. From this diagram, it is understood that when an input voltage is off V.sub.C, even slightly, this deviation will appear in amplified manner in the output. That is,

V.sub.1 '-V.sub.C =.alpha..sub.1 (V.sub.C -V.sub.1) V.sub.C -V.sub.2 '=.alpha..sub.2 (V.sub.2 -V.sub.C) where .alpha..sub.1 and .alpha..sub.2 are amplification factors of the inverter 3.

From the equation (3), therefore, if A.sub.in is smaller than V.sub.ref, the output V.sub.A1 (= V.sub.out) of the comparator would be: ##EQU2## and if A.sub.in is greater than V.sub.ref, the output V.sub.A2 (= V.sub.out) of the comparator would be: ##EQU3##

The conventional comparators should be concerned with an offset initiated by the resistors in the power sources because of the following reason. As the input of the inverter 3 is at the middle level at the sampling time (at which charges are being accumulated in the capacitor C with SW1, Q.sub.3 and Q.sub.4 all being ON), the P and N type transistors Q.sub.2 and Q.sub.1 of the inverter are both turned ON to thereby permit a through current to flow between the power sources V.sub.DD and V.sub.SS. Given that I.sub.p is the through current at that time and R.sub.S and R.sub.D are a source resistor of the inverter on the side of the reference power source (V.sub.SS) and a source resistor on the side of the supplying power source (V.sub.DD), respectively, the potential on the V.sub.SS side increases by I.sub.p R.sub.S while the potential on the V.sub.DD side falls by I.sub.p R.sub.D. The threshold value V.sub.C at this time can be given by: ##EQU4## where V.sub.TN and V.sub.TP are the threshold voltages of N and P type transistors, respectively, L.sub.N and W.sub.N are the channel length and width of the N type transistor, L.sub.p and W.sub.p are the channel length and width of the P type transistor, .mu..sub.N and .mu..sub.p are the mobilities of electrons and holes, and E.sub.OX and t.sub.OX are the dielectric constant and thickness of a gate oxide film.

When the operation enters a comparing period (unlike in the sampling time, only SW2 being turned ON), the input potential of the inverter varies from V.sub.C, thus causing the through current to become to I.sub.p '. The threshold value V.sub.C ' at this time is ##EQU5## From the equations (5) and (6) it should be understood that V.sub.C and V.sub.C ' have the following relationship: ##EQU6## Therefore, the actual charges Q' accumulated in the capacitor C at the sampling time is

Q'=(V.sub.C +.DELTA.V-A.sub.in) C. From this equation, the potential V.sub.A at the point A at the time a comparison is made will be V.sub.A =V.sub.C +(V.sub.ref -A.sub.in)+.DELTA.V (7) Comparing the equation (3) with the equation (7) shows that an offset of .DELTA.V occurs according to the prior art.

To reduce the offset originated from the resistors of power sources, efforts have been made to make the resistances of these resistors as small as possible. This has resulted in thick power wires, which causes larger chip size. Minimizing the resistances also restricts the location of the comparator.

SUMMARY OF THE INVENTION

Accordingly, it is an object of this invention to reduce or eliminate a variation in threshold value of an inverter originated from the resistors of power sources of a circuit.

The present invention provides a logic circuit comprising first power terminal (V.sub.SS); a second power terminal (V.sub.DD) set at a higher potential than the first power terminal (V.sub.SS); a first FET (Q.sub.1) of a first conductivity having a current path coupled to the first power terminal (V.sub.SS); a second FET (Q.sub.2) of a second conductivity having a current path coupled to the second power terminal (V.sub.DD); and an input terminal commonly coupled to gate terminals of the first and second FETs (Q.sub.1, Q.sub.2), the first FET (Q.sub.1) and the second FET (Q.sub.2) having a relationship expressed approximately by the following equation: ##EQU7## where R.sub.S is a resistance of a resistor element parasitically produced between the first power terminal (V.sub.SS) and the current path of the first FET (Q.sub.1),

R.sub.D is a resistance of a resistor element parasitically produced between the second power terminal

(V.sub.DD) and the current path of the second FET (Q.sub.2),

W.sub.N is a channel width of the first FET (Q.sub.1),

W.sub.p is a channel width of the second FET (Q.sub.2),

L.sub.N is a channel length of the first FET (Q.sub.1),

L.sub.p is a channel length of the second FET (Q.sub.2),

.mu..sub.N is a first carrier mobility of the first FET (Q.sub.1), and

.mu..sub.p is a second carrier mobility of the second FET (Q.sub.2).

The variation in threshold value in an inverter which does not embody this invention is caused by the offset .DELTA.V, and is originated from the term IP(.beta..sub.N R.sub.S -.beta..sub.p R.sub.D) in the aforementioned equation (5) which is a variation in threshold value of the inverter. If the following is satisfied in this term, therefore,

.beta..sub.N R.sub.S =.beta..sub.p R.sub.D (9) the offset .DELTA.V would become zero, and the variation in threshold would be also zero as a consequence.

In other words, this invention is characterized in that, paying attention to the source resistors on the V.sub.DD and V.sub.SS sides to which no consideration has conventionally been given, the resistances of these resistors and the circuit constant of the inverter are made to have the relationship given by the equation (8). In the case of a chopper type comparator, for instance, since the threshold value does not vary, .DELTA.V in the equation (7) is 0 V, thus eliminating a .DELTA.V-originated offset.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram illustrating one embodiment of this invention;

FIG. 2 is a circuit diagram illustrating another embodiment of this invention;

FIG. 3 is a circuit diagram for explaining an example to which this invention is not applied;

FIG. 4 is a diagram illustrating the input-output signal characteristic of an inverter;

FIG. 5 is a diagram illustrating transistors embodying this invention with the same channel width and the same channel length;

FIG. 6 is a diagram illustrating transistors embodying this invention with different channel widths and the same channel length;

FIG. 7 is a diagram illustrating transistors embodying this invention with the same channel width and different channel lengths; and

FIG. 8 is a diagram illustrating transistors embodying this invention with different channel widths and different channel lengths.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

On embodiment of this invention will now be described referring to the accompanying drawings. FIG. 1 illustrates a circuit according to this embodiment in comparison with the one shown in FIG. 3, with only the main part of a chopper type comparator being illustrated. For the purpose of comparison and ease of understanding, the same reference numerals as shown in FIG. 3 are used in FIG. 1 to specify the identical or corresponding elements. R.sub.D and R.sub.S specify, as mentioned earlier, the wiring resistances of power sources V.sub.DD and V.sub.SS, and these resistances are set from the circuit constant of the inverter 3 to satisfy the equation (8). If R.sub.D and R.sub.S are known in advance, the circuit constant of the inverter 3 should be altered to satisfy the equation (8).

In other words, if there is the relationship of the equation (9) satisfied in I.sub.p (.beta..sub.N R.sub.S -.beta..sub.p R.sub.D) in the equation (.sub.5), a variation in threshold value, the threshold values R.sub.S and R.sub.D and the circuit constant of the inverter 3 need only to have the relation of the equation (8), i.e., ##EQU8##

The following is an example of parameters satisfying these equations (5) and (8). The first channel length L.sub.N of the first FET Q.sub.1 is 2.4 .mu.m, the first channel width W.sub.N thereof 6.2 .mu.m, and the first carrier mobility W.sub.N 200 cm.sup.2 /V.sec. With regard to the second FET Q.sub.2, the second channel length L.sub.p is 2.4 .mu.m, the second channel width W.sub.p 14.1 .mu.m, and the second carrier mobility up 85 cm.sup.2 /V.sec.

Of these parameters, the first channel length L.sub.N and the first channel width W.sub.N of the first FET Q.sub.1 should preferably be 1.2 .mu.m to 100 .mu.m, and so should the second channel length L.sub.P and second channel width W.sub.P of the second FET Q.sub.2.

Such simple means can eliminate a variation in threshold value of the inverter 3 to thereby eliminate an offset originated from the source resistors. This can be achieved irrespective of the resistances of the source resistors, which does not therefore restrict the location of the comparator so much. Further, the wires of the power sources need not be made thick, thus preventing the chip size to be undesirably increased.

FIG. 2 illustrates another embodiment of this invention in which in addition to wiring resistors R.sub.A1D and R.sub.A1S (equivalent to R.sub.S and R.sub.D, respectively) of aluminum higher resistors R.sub.D ' and R.sub.S ' are inserted in the circuit. If the values of R.sub.D ' and R.sub.S ' are set to make R.sub.A1S and R.sub.A1D negligible, the circuit constant can be determined only from R.sub.D ' and R.sub.S '.

In other words, given that R.sub.A1D, R.sub.A1S <<R.sub.D ', R.sub.S ', ##EQU9## In this case, the aforementioned parameters need only be set to satisfy ##EQU10## as per the first embodiment.

Different influences will be exerted on fabrication of a semiconductor device depending on which of the parameters, the channel lengths (L.sub.N, L.sub.p) of the two FETs, their channel widths (W.sub.N, W.sub.p) or the resistances (R.sub.S, R.sub.D) of the source electrodes, should be adjusted in realizing the above equation.

FIG. 5 illustrates transistors embodying this invention which have the same channel width and the same channel length; reference numeral 50 denotes a P-type diffusion, 52 an N-type diffusion, and 54 contact holes. If the equality is realized by the resistances R.sub.S, R.sub.D of the source electrodes while making the channel lengths L.sub.N, L.sub.p and the channel widths W.sub.N, W.sub.p fixed as shown in FIG. 5, regular channel lengths and channel widths can be maintained, thus ensuring a uniform shape of the device This produces such a merit that there would be no variation in fabricated semiconductor devices which is inevitably caused by altering the channel lengths L.sub.N, L.sub.p and channel widths W.sub.N, W.sub.p, and an error in characteristic of the devices is not therefore likely to occur. In addition, the circuit area of the semiconductor device will not be increased, making it possible to realize a higher integration of the device. The resistances R.sub.S, R.sub.D of the source electrodes may be adjusted by using a resistor made of polysilicon, etc.

FIG. 6 illustrates transistors embodying this invention which have different channel widths but the same channel length; reference numeral 50 denotes a P-type diffusion, 52 an N-type diffusion, and 54 contact holes. The equality of this invention may be realized by altering the channel widths W.sub.N, W.sub.p while setting the channel lengths L.sub.N, L.sub.p equal to each other, as shown in FIG. 6. Employing the same channel length for L.sub.N, L.sub.p throughout the device ensures alignment of this invention without causing a variation in electric characteristic of the overall device. In addition, designing the pattern of a semiconductor device in this case is easier than the one involved in a case where the channel widths W.sub.N, W.sub.p are altered.

FIG. 7 illustrates transistors embodying this invention which have the same channel width but different channel lengths; reference numeral 50 denotes a P-type diffusion, 52 an N-type diffusion, and 54 contact holes. The equality of this invention may be realized by altering the channel lengths L.sub.N, L.sub.p while setting the channel widths W.sub.N, W.sub.p equal to each other, as shown in FIG. 7.

FIG. 8 illustrates transistors embodying this invention which have different channel widths and different channel lengths; reference numeral 50 denotes a P-type diffusion, 52 an N-type diffusion, and 54 contact holes. The equality of this invention may be realized by altering both the channel widths W.sub.N, W.sub.p and the channel lengths L.sub.N, L.sub.P, as shown in FIG. 8.

Of course, this invention is in no way restricted to the above-described particular embodiments, but may be modified in various manners. For instance, although the foregoing description has been given mainly with reference to a chopper type comparator, this invention can also be applied to an inverter being used as an amplifier.

As described above, according to this invention, a variation in threshold value of an inverter can be eliminated by simple means, so that an offset originated from the resistors of power sources can easily be eliminated. In addition, since the elimination of the offset can be realized irrespective of the values of the source resistors, no restriction will be made on the location of the comparator. Further, the wires of the power sources need not be made particularly thick, thus preventing the chip size from being undesirably increased.

Claims

1. A logic circuit comprising:

a first power terminal;

a second power terminal set at a higher potential than said first power terminal;

a first FET of a first conductivity having a current path coupled to said first power terminal;

a second FET of a second conductivity having a current path coupled to said second power terminal; and

an input terminal commonly coupled to gate terminals of said first and second FETs,

said first FET and said second FET having a relationship expressed approximately by the following equation: ##EQU11## where R.sub.S is a resistance of a resistor element parasitically produced between said first power terminal and said current path of said first FET,

R.sub.D is a resistance of a resistor element parasitically produced between said second power terminal and said current path of said second FET,

W.sub.N is a channel width of said first FET,

W.sub.p is a channel width of said second FET,

L.sub.N is a channel length of said first FET,

L.sub.p is a channel length of said second FET,

.mu..sub.N is a mobility of a first carrier of said first FET, and

.mu..sub.p is a mobility of a second carrier of said second FET.

2. A logic circuit according to claim 1, wherein said first channel length equals said second channel length, and said first channel width equals said second channel width.

3. A logic circuit according to claim 1, wherein said first channel length equals said second channel length.

4. A logic circuit according to claim 1, wherein said first channel width equals said second channel width.

5. A logic circuit according to claim 1, wherein said first channel length differs from said second channel length, and said first channel width differs from said second channel width.

6. A logic circuit according to claim 1, wherein said first channel length of said first FET is in a range from 1.2 .mu.m to 100.0 .mu.m.

7. A logic circuit according to claim 1, wherein said first channel width of said first FET is in a range from 1.2 .mu.m to 100.0 .mu.m.

8. A logic circuit according to claim 1, wherein said second channel length of said second FET is in a range from 1.2 .mu.m to 100.0 .mu.m.

9. A logic circuit according to claim 1, wherein said second channel width of said second FET is in a range from 1.2 .mu.m to 100.0 .mu.m.

10. A logic circuit comprising:

a first power terminal;

a second power terminal set at a higher potential than said first power terminal;

a first FET of a first conductivity having a current path coupled to said first power terminal;

a second FET of a second conductivity having a current path coupled to said second power terminal;

an input terminal commonly coupled to gate terminals of said first and second FETs;

a capacitor having one end commonly coupled to said gate terminals of said first and second FETs;

a first switch having one end coupled to said capacitor and an other end supplied with a signal to be detected; and

a second switch having one end coupled to said capacitor and a other end applied with a reference voltage,

said first FET and said second FET having a relationship expressed approximately by the following equation: ##EQU12## where R.sub.S is a resistor element parasitically produced in said first power terminal,

R.sub.D is a resistance of a resistor element parasitically produced in said second power terminal,

W.sub.N is a channel width of said first FET,

W.sub.p is a channel width of said second FET,

L.sub.N is a channel length of said first FET,

L.sub.p is a channel length of said second FET,

.mu..sub.N is a mobility of a first carrier of said first FET, and

.mu..sub.p is a mobility of a second carrier of said second FET.

11. A logic circuit according to claim 10, wherein said first channel length equals said second channel length, and said first channel width equals said second channel width.

12. A logic circuit according to claim 10, wherein said first channel length equals said second channel length.

13. A logic circuit according to claim 10, wherein said first channel width equals said second channel width.

14. A logic circuit according to claim 10, wherein said first channel length differs from said second channel length, and said first channel width differs from said second channel width.

15. A logic circuit according to claim 10, wherein said first channel length of said first FET is in a range from 1.2 .mu.m to 100.0 .mu.m.

16. A logic circuit according to claim 10, wherein said first channel width of said first FET is in a range from 1.2 .mu.m to 100.0 .mu.m.

17. A logic circuit according to claim 10, wherein said second channel length of said second FET is in a range from 1.2 .mu.m to 100.0 .mu.m.

18. A logic circuit according to claim 10, wherein said second channel width of said second FET is in a range from 1.2 .mu.m to 100.0 .mu.m.

19. A logic circuit comprising:

a first insulating gate field effect transistor (IG-FET) having a first conductivity type;

a second insulating gate field effect transistor (IG-FET) having a second conductivity type;

a first power terminal coupled to a source electrode of said first IG-FET;

a second power terminal coupled to a source electrode of said IG-FET; and

an input terminal being commonly coupled gate electrodes of said first and second IG-FETs;

wherein the following relationship is approximately satisfied: ##EQU13## where L.sub.N denotes a channel length; W.sub.N denotes a channel width of said first IG-FET; L.sub.p denotes a channel length; W.sub.p denotes a channel width of said second IG-FET; R.sub.S denotes a wiring resistance of said first power terminal; R.sub.D denotes a wiring resistance of said second power terminal; .mu..sub.N denotes a mobility of carriers of said first IG-FET; and .mu..sub.P denotes a mobility of carrier of said second IG-FET.

20. A logic circuit according to claim 19, further comprising switch means, coupled to said input terminal of said logic circuit, said switch means being opened and closed according to a sampling time of a comparison input signal and a time of comparing said comparison input signal with a reference voltage to thereby supply a voltage corresponding to a difference between said comparison input signal and said reference voltage to said input terminal of said logic circuit.