Claims
- 1. A method for sorting out, from an incoming sequence of n binary data values, k greatest ones of said data values, comprising machine-executed steps of:
- a) sequentially writing each of said data values, into successive respective ones of n one-word memory locations, as part of a respective data word comprising:
- a first, inhibition bit, and a second, selection bit;
- third bits representing said respective data values, said third bits being less significant, within said data word, than said first inhibition bit, and said second selection bit; and
- fourth bits corresponding to a number representative of a position of said respective data value within said sequence, said fourth bits being less significant than said third bits;
- b) upon inception of said incoming sequence of binary data values, setting said respective first inhibition bits of said n memory locations to a first value:
- c) while writing said third data bits of each said data word, concurrently resetting said first inhibition bits and second selection bits of said corresponding word to a second value;
- d) after arrival of a predetermined number of said words, detecting, after arrival of each further data value until arrival of an n.sup.th data value, a smallest data word stored in said memory locations, and setting said second selection bit of said smallest data word to said first value accordingly; and
- e) sequentially reading, from a time when a signal corresponding to said n.sup.th data value arrives, said data bits from ones of said memory locations, and conditionally processing said data bits of each said data word depending upon whether said respective selection bit thereof has said second value.
- 2. A method according to claim 1, wherein during step e), said data values are read in an order in which said data values have been written during step a).
- 3. A method according to claim 1, wherein said fourth bits are associated with ones of said data values in decreasing order.
- 4. A method according to claim 1, wherein said fourth bits are associated with ones of said data values in increasing order.
- 5. A method according to claim 1, wherein said step d) is begun after arrival of said signal corresponding to a k.sup.th data word.
- 6. A method according to claim 1, wherein said first, inhibition bit is more significant, within said data word, than said second, selection bit.
- 7. A method according to claim 1, wherein n=64.
- 8. A method according to claim 1, wherein said fourth bits remain constant for a given memory location.
- 9. A circuit for identifying k greatest data values in a sequence of n data values sequentially arriving on an input bus as binary logic signals, comprising:
- a memory point matrix of n columns and m rows, each column being assigned to a word corresponding to one of said data values and comprising, in order of increasing row numbers and decreasing bit weights:
- a first inhibition memory point connected to be set by an initialization signal and reset by arrival of a respective one of said data values,
- a second selection memory point connected to an output bus line, and connected to be reset by arrival of a respective one of said data values,
- third memory points connected to lines of a data input bus, and connected and configured to receive and store bits of a respective one of said data value, and
- fourth memory points containing a number representative of a position rank of said data values within said sequence;
- a first circuit for addressing each of said columns according to an input rate of data values, and storing therein said data value present on said lines of said input bus;
- a second circuit, active only after arrival of a predetermined one of said data values, for detecting a smallest word and setting a corresponding one of said second memory points as soon as a next data value has arrived; and
- a third circuit for addressing each of said columns in accordance with said data rate and writing respective bits contained in said second and third memory points on said lines of said data output bus as soon as an n.sup.th data value is written.
- 10. A circuit according to claim 9, wherein said second circuit comprises modules, each being associated to a memory point and each comprising:
- a connection to output Q of an associated one of said memory point,
- an exclusion output X.sub.ij which, if a current row i is a last (m), is connected to a set input of said second selection memory point of current column j,
- an intermediate output,
- an exclusion input connected, either to a respective said exclusion output X.sub.ij of one of said modules of current column j and of preceding row i-j, or else to "0" if said current row is first;
- a detection input, connected to all output of a detection logic circuit which is common to all modules of said current row j and connected to receive as inputs said intermediate outputs of said modules;
- said respective exclusion output X.sub.ij taking values summed up in the following table, where symbol "#" designates 0 or 1 indifferently:
- ______________________________________Z.sub.i X.sub.i-1,j X.sub.ij______________________________________# 1 10 0 01 0 Q______________________________________
- said intermediate output taking a value of 1 if said respective output X.sub.i-1,j and/or said respective output Q is "1".
- 11. A circuit according to claim 10, wherein said detection logic circuit provides a value 0 at output Z.sub.i only when all said intermediate outputs of said modules of said current row j are set to "1".
- 12. A circuit according to claim 10, wherein said fourth memory points have no data input or data output connection.
- 13. A circuit according to claim 10, wherein said detection logic circuit is implemented as wire-AND logic.
- 14. A circuit according to claim 9, wherein circuits for addressing each column are constituted by a shift register.
- 15. A circuit according to claim 9, wherein said second selection memory points are authorized to be set by an active enable signal between arrivals of an (n-k).sup.th datum and said n.sup.th datum.
- 16. A circuit according to claim 9, wherein said fourth memory points have no data input or data output connection.
- 17. A circuit according to claim 9, wherein n=64.
- 18. A method for identifying, in an incoming series of sequences of n digital data values, k largest data values in each said sequence of n values, comprising machine-executed steps of:
- as soon as each new one of said sequences starts, setting said respective inhibition bits of all of n reserved locations to a first value;
- sequentially writing into successive ones of n reserved memory locations, for each of said data values, a respective data word comprising: an inhibition bit, a selection bit, and data bits representing said respective data value;
- while writing each of said data values into respective ones of said memory locations, resetting said first inhibition bits and second selection bits of said respective memory location to said first value;
- upon arrival of each said data value, after arrival of a predetermined number of said data values in said sequence, finding a smallest word stored in said n memory locations and setting said selection bit of said smallest data value to a second value and
- after an n.sup.th data value arrives, sequentially reading stored data words from said memory locations and conditionally outputting each said data value depending upon whether a respective said selection bit has said second value.
- 19. A method according to claim 18, wherein n=64.
- 20. A method according to claim 18, wherein each said memory location also includes one or more fixed priority bits which are less significant than said data bits, said priority bits being distinct for each of said memory locations.
Priority Claims (1)
Number |
Date |
Country |
Kind |
91/02301 |
Feb 1991 |
FRX |
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Parent Case Info
This is a continuation of application Ser. No. 07/838,668, filed Feb. 20, 1992, now abandoned.
US Referenced Citations (1)
Number |
Name |
Date |
Kind |
4317182 |
Takase et al. |
Feb 1982 |
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Foreign Referenced Citations (1)
Number |
Date |
Country |
0273802 |
Jul 1988 |
EPX |
Non-Patent Literature Citations (2)
Entry |
Patent Abstracts of Japan, vol. 015, No. 121 (E-1049) Mar. 25, 1991. |
"A Bit-serial Device for Extracting a Vector Element of a Specified Rank", C. K. Yuen, Digital Processes, vol. 6, No. 2-3, 1980, pp. 207-210. |
Continuations (1)
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Number |
Date |
Country |
Parent |
838668 |
Feb 1992 |
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