Patent Application
20250037639
This application claims priority under 35 USC 119 from Japanese Patent application No. 2023-123355 filed on Jul. 28, 2023, the disclosure of which is incorporated by reference herein.
The present disclosure relates to a circuit and a communication system.
Patent Document 1 (Japanese translation of PCT international application No. 2001-503182) discloses a receiving circuit for receiving data using a differential signal, which is a balanced signal transmitted by an alternating current (AC) coupling method (see FIG. 4 of Patent Document 1).
In the alternating current coupling method, a capacity element that removes a DC signal is placed in the transmission path. For this reason, while the data input to the receiving circuit continues to change, the capacity element is repeatedly charged and discharged, and the potentials of the two signals included in the differential signal, which change in a complementary manner, change to H level or L level. Thus, the receiving circuit may operate normally according to the differential signal.
However, when the input data does not change for a certain period of time, the energy stored in the capacity element continues to be discharged, and the potentials of the two signals may become approximately the same level. Thus, the receiving circuit is unable to detect the potential of the differential signal and may malfunction. For this reason, the conventional technology has room for improvement in terms of realizing stable operation of the receiving circuit.
The disclosure provides a circuit capable of realizing stable operation.
The circuit according to the disclosure is an alternating current coupling circuit, including: a receiving circuit, having a first input terminal for inputting a first signal transmitted via a first capacitive element, and a second input terminal for inputting a second signal transmitted via a second capacitive element and having a potential that changes complementarily to the first signal, and outputting a first logic signal corresponding to a potential of the first signal and a second logic signal corresponding to a potential of the second signal; and a signal supply circuit, supplying a first guarantee signal having a potential corresponding to a value of the first logic signal to the first input terminal as a signal for guaranteeing a potential of the first signal, and supplying a second guarantee signal having a potential that changes complementarily to the first guarantee signal to the second input terminal as a signal for guaranteeing a potential of the second signal.
The communication system according to the disclosure includes a first semiconductor device, having a transmitting circuit for transmitting a first signal and a second signal; and a second semiconductor device having the above-mentioned circuit, wherein the first signal is supplied to the circuit via the first capacitive element, and the second signal is supplied to the circuit via the second capacitive element.
According to the disclosure, a circuit that is capable of achieving stable operation may be provided.
The embodiment is described below with reference to the drawings. In addition, the same or similar symbols are used for the same functions and configurations, and descriptions therefor are omitted as appropriate.
The display panel 10 may be interpreted as an image display device such as an LCD display panel or an organic electro luminescence (EL) panel. The timing controller 11 may control the display timing of an image on the display panel 10 by controlling a plurality of driver ICs 12A and the gate driver 13. The timing controller 11 may generate a clock signal and supply the same to the driver ICs 12A. The timing controller 11 may supply a scan control signal synchronized with the video data to the gate driver 13.
The driver IC 12A may be interpreted as a semiconductor device having a receiving circuit, which is described later. The driver ICs 12A control the lighting state of a plurality of light-emitting elements provided on the display panel 10.
The gate driver 13 may generate a gate signal based on the signal supplied from the timing controller 11 and supply the gate signal to the display panel 10.
The timing controller 11 and the driver ICs 12A may constitute a communication system 200. The communication system 200 may interpret a system that applies mini-LVDS (low voltage differential signaling). Mini-LVDS may be interpreted as an interface standard for connecting a liquid crystal controller and a liquid crystal driver.
Next, a specific configuration of the communication system 200 is described with reference to
The timing controller 11 includes a transmitting circuit 111. The transmitting circuit 111 may be interpreted as a circuit that transmits data using a differential signal 4. The differential signal 4 includes two signals that change in a complementary manner to each other. Specifically, the differential signal 4 includes a first signal 41 transmitted via a first capacitive element 1 provided in the transmission path 3 and a second signal 42 transmitted via a second capacitive element 2 provided in the transmission path 3. The second signal 42 may be interpreted as a signal whose potential changes complementarily to the first signal 41.
The signal output circuit 12 includes a receiving circuit 121 and a signal supply circuit 122.
The receiving circuit 121 may be interpreted as an alternating current coupling data receiving circuit that is supplied with a differential signal 4 transmitted via a capacity element. The alternating current coupling method may be interpreted as a method of removing the direct current component of the input signal and transmitting only the alternating current component to the receiving circuit 121. The receiving circuit 121 has a first input terminal IN1 that inputs the first signal 41 and a second input terminal IN2 that inputs the second signal 42.
The receiving circuit 121 outputs a first logic signal 51 corresponding to the potential of the first signal 41 and a second logic signal 52 corresponding to the potential of the second signal 42. Specifically, the first signal 41 and the second signal 42 are amplified, and the first logic signal 51 and the second logic signal 52 having voltage levels higher than the first signal 41 and the second signal 42 are output.
The first logic signal 51 is transmitted to the display panel 10 shown in
The second logic signal 52 is transmitted to the display panel 10 shown in
The signal supply circuit 122 may be interpreted as a circuit for guaranteeing the potential of the first signal 41 and the potential of the second signal 42. The signal supply circuit 122 includes a first input terminal S1 that inputs the first logic signal 51, a second input terminal S2 that inputs the second logic signal 52, a first output terminal Q1 that outputs a first guarantee signal, and a second output terminal Q2 that outputs a second guarantee signal.
The signal supply circuit 122 may supply a first guarantee signal having a potential corresponding to a value of the first logic signal 51 to the first input terminal IN1 of the receiving circuit 121 via the first output terminal Q1 as a signal for guaranteeing a potential of the first signal 41. Further, the signal supply circuit 122 may supply a second guarantee signal having a potential that changes complementarily to the first guarantee signal to the second input terminal IN2 of the receiving circuit 121 via the second output terminal Q2 as a signal for guaranteeing a potential of the second signal 42.
Next, the specific configuration of the signal output circuit 12 is described with reference to
As shown in
The first signal 41 is input to the first differential amplifier circuit 121a via the first input terminal IN1, and the second signal 42 is input to the first differential amplifier circuit 121a via the second input terminal IN2. The output of the first differential amplifier circuit 121a is input to the second differential amplifier circuit 121b. The second differential amplifier circuit 121b amplifies the input signals and outputs the same as the first logic signal 51 and the second logic signal 52.
When the first guarantee signal 61 of a first potential VH is supplied to the first input terminal IN1 of the receiving circuit 121, the signal supply circuit 122 supply the second guarantee signal 62 of a second potential VL lower than the first potential VH to the second input terminal IN2 of the receiving circuit 121. When the first guarantee signal 61 of the second potential VL is supplied to the first input terminal IN1 of the receiving circuit 121, the signal supply circuit 122 supply the second guarantee signal 62 of the first potential VH to the second input terminal IN2 of the receiving circuit 121. The first potential VH and the second potential VL may be interpreted as a reference voltage with a restricted current supply capability.
Specifically, the signal supply circuit 122 includes a voltage divider circuit 122a and a plurality of switches. The plurality of switches include a first switch 122b1, a second switch 122b2, a third switch 122b3, and a fourth switch 122b4.
The voltage divider circuit 122a may be interpreted as a circuit that generates the first potential VH or the second potential VL by dividing a voltage applied to a resistor provided between two power sources (VDD, VSS). By using the voltage divider circuit 122a, the first potential VH or the second potential VL may be generated with a simple configuration by using a power source common to the two power sources (VDD, VSS) supplied to the receiving circuit 121.
It is noted that the signal supply circuit 122 may include a power source that outputs the first potential VH or the second potential VL, instead of the voltage divider circuit 122a including a resistor.
When a value of the first logic signal 51 is a specific potential, the first switch 122b1 is turned on so as to supply the first guarantee signal 61 of the first potential VH to the first input terminal IN1. Specifically, when the value of the first logic signal 51 applied to the first input terminal S1 is at H level, the first switch 122b1 is turned on so as to supply the first guarantee signal 61 of the first potential VH to the first input terminal IN1 of the receiving circuit 121 via the first output terminal Q1.
When the value of the first logic signal 51 applied to the first input terminal S1 is at L level, the first switch 122b1 is turned off. In this way, the output of the first guarantee signal 61 of the first potential VH is stopped.
When a value of the second logic signal 52 is a specific potential, the second switch 122b2 is turned on so as to supply the second guarantee signal 62 of the first potential VH to the second input terminal IN2. Specifically, when the value of the second logic signal 52 applied to the second input terminal S2 is at H level, the second switch 122b2 is turned on so as to supply the second guarantee signal 62 of the first potential VH to the second input terminal IN2 of the receiving circuit 121 via the second output terminal Q2.
When the value of the second logic signal 52 applied to the second input terminal S2 is at L level, the second switch 122b2 is turned off. In this way, the output of the second guarantee signal 62 of the first potential VH is stopped.
When a value of the second logic signal 52 is a specific potential, the third switch 122b3 is turned on so as to supply the first guarantee signal 61 of the second potential VL to the first input terminal IN1. Specifically, when the value of the second logic signal 52 applied to the second input terminal S2 is at H level, the third switch 122b3 is turned on so as to supply the first guarantee signal 61 of the second potential VL to the first input terminal IN1 of the receiving circuit 121 via the first output terminal Q1.
When the value of the second logic signal 52 applied to the second input terminal S2 is at L level, the third switch 122b3 is turned off. In this way, the output of the second guarantee signal 62 of the second potential VL is stopped.
When a value of the first logic signal 51 is a specific potential, the fourth switch 122b4 is turned on so as to supply the second guarantee signal 62 of the second potential VL to the second input terminal IN2. Specifically, when the value of the first logic signal 51 applied to the first input terminal S1 is at H level, the fourth switch 122b4 is turned on so as to supply the second guarantee signal 62 of the second potential VL to the second input terminal IN2 of the receiving circuit 121 via the second output terminal Q2.
When the value of the first logic signal 51 applied to the first input terminal S1 is at L level, the fourth switch 122b4 is turned off. In this way, the output of the second guarantee signal 62 of the second potential VL is stopped.
Next, the operation of the signal output circuit 12 is described with reference to
State “1” shown in
State “2” shown in
The first signal 41 input to the first input terminal IN1 and the first logic signal 51 output from the first output terminal OUT1 are in phase. The second signal 42 input to the second input terminal IN2 and the second logic signal 52 output from the second output terminal OUT2 are in phase. The first signal 41 and the second signal 42 are in opposite phase.
In
As shown in
When the first signal 41 is at L level and the second signal 42 is at H level from timing t2 to timing t3, the first logic signal 51 is at L level, the second logic signal 52 is at H level, the first switch 122b1 is turned off, and the second switch 122b2 is turned on. In addition, the third switch 122b3 is turned on and the fourth switch 122b4 is turned off. As a result, the second potential VL from the voltage divider circuit 122a is input to the first input terminal IN1 via the first output terminal Q1. Further, the first potential VH from the voltage divider circuit 122a is input to the second input terminal IN2 via the second output terminal Q2.
When the first signal 41 changes to H level and the second signal 42 changes to L level at timing t3, during the period from timing t3 to timing t4, similarly to the period from timing t1 to timing t2, the first potential VH is input to the first input terminal IN1, and the second potential VL is input to the second input terminal IN2.
(In Case the Output Data does not Change for a Certain Period of Time)
In the period from timing t2 to timing t3 in
Thus, the second potential VL is input to the first input terminal IN1 via the first output terminal Q1. Further, the first potential VH is input to the second input terminal IN2 via the second output terminal Q2. Then, the first potential VH and the second potential VL continue to be output until timing t3. Specifically, the potential of the first signal 41 transmitted via the first capacitive element 1 and the potential of the second signal 42 transmitted via the second capacitive element 2 are guaranteed until timing t3. More specifically, since the input data does not change for a certain period of time, the energy stored in the capacity element continues to be discharged, so that even in a situation where the potentials of the first signal 41 and the second signal 42 input to the receiving circuit 121 may decrease, by adding the first potential VH or the second potential VL to these signals, the potentials of the first signal 41 and the second signal 42 input to the receiving circuit 121 may be guaranteed.
As described above, in the alternating current coupling method, a capacity element is provided in a transmission path for the purpose of removing a direct current signal, so that the capacity element is repeatedly charged and discharged while the data input to the receiving circuit 121 continues to change. In this case, the potentials of the two signals included in the differential signal 4 that change complementarily to each other, that is, the first signal 41 and the second signal 42, change to H level or L level within a certain period of time. Thus, the receiving circuit 121 may operate normally according to the differential signal 4.
In contrast, in the case where the data does not change for a certain period of time, the energy stored in the capacity element continues to be discharged, and the potentials of the first signal 41 and the second signal 42 may decrease to approximately the same level during the period from timing t2a to timing t3 in
As shown in
With this configuration, even in a situation where the potentials of the first signal 41 and the second signal 42 may decrease since the data from the transmitting circuit 111 does not change for a certain period of time, the potentials of the first signal 41 and the second signal 42 may be guaranteed by the guarantee signal from the signal supply circuit 122. Thus, the potentials of the first logic signal 51 and the second logic signal 52 of the receiving circuit 121 are guaranteed, so that accurate data transfer may be achieved even when data is not transmitted between the transmitting circuit 111 and the receiving circuit 121 for a certain period of time using the alternating current coupling method.
Furthermore, when LVDS is applied to the communication system 200 of the disclosure, the potentials of the first logic signal 51 and the second logic signal 52 are guaranteed, thereby realizing high-speed serial transfer. By realizing high-speed serial transfer, the number of wires between the transmitting circuit 111 and the receiving circuit 121 may be reduced, and the manufacturing costs of the substrate associated with the wires may be reduced. Since LVDS is a differential current mode interface, it has high resistance to external noise and may also reduce crosstalk noise.
It is noted that regarding the embodiment of the disclosure described above, the following Appendix is further disclosed.
An alternating current coupling circuit, the circuit includes: a receiving circuit, having a first input terminal for inputting a first signal transmitted via a first capacitive element, and a second input terminal for inputting a second signal transmitted via a second capacitive element and having a potential that changes complementarily to the first signal, and outputting a first logic signal corresponding to a potential of the first signal and a second logic signal corresponding to a potential of the second signal; and a signal supply circuit, supplying a first guarantee signal having a potential corresponding to a value of the first logic signal to the first input terminal as a signal for guaranteeing a potential of the first signal, and supplying a second guarantee signal having a potential that changes complementarily to the first guarantee signal to the second input terminal as a signal for guaranteeing a potential of the second signal.
In the circuit according to Appendix 1, the signal supply circuit is configured to supply the second guarantee signal of a second potential lower than a first potential to the second input terminal when the first guarantee signal of the first potential is supplied to the first input terminal and supply the second guarantee signal of the first potential to the second input terminal when the first guarantee signal of the second potential is supplied to the first input terminal.
In the circuit according to Appendix 1 or Appendix 2, the signal supply circuit includes a voltage divider circuit that generates the first potential or the second potential by dividing a voltage applied to a resistor provided between two power sources.
In the circuit according to any one of Appendix 1 to Appendix 3, the signal supply circuit includes: a first switch that is turned on when a value of the first logic signal is a specific potential so as to supply the first guarantee signal of the first potential to the first input terminal; a second switch that is turned on when a value of the second logic signal is a specific potential so as to supply the second guarantee signal of the first potential to the second input terminal; a third switch that is turned on when a value of the second logic signal is a specific potential so as to supply the first guarantee signal of the second potential to the first input terminal; and a fourth switch that is turned on when a value of the first logic signal is a specific potential so as to supply the second guarantee signal of the second potential to the second input terminal.
A semiconductor device includes the circuit according to any one of Appendix 1 to Appendix 4.
A communication system includes: a first semiconductor device, having a transmitting circuit for transmitting the first signal and the second signal according to any one of Appendix 1 to Appendix 5; and a second semiconductor device, having the circuit according to any one of Appendix 1 to Appendix 5, wherein the first signal is supplied to the receiving circuit via the first capacitive element, and the second signal is supplied to the receiving circuit via the second capacitive element.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2023-123355 | Jul 2023 | JP | national |
