Circuit and method for detection of synchronization signal

Abstract

A synchronization detection circuit in which serial data received is collated to a predetermined matching pattern in a synchronization detection window to generate a detection level having a value corresponding to the degree of conformity to the matching pattern and in case a pattern is detected, whose detection level exceeds a preset threshold value, the pattern so detected is indicative of a synchronization signal. During the time before detection of the synchronization signal pattern, the maximum value of past detection level is retained. In case a pattern of the detection level of a value higher than the maximum value, as retained, is detected, the past detection level is updated and the detection of the pattern corresponding to the detection level of the higher value is considered to indicate detection of a provisional synchronization signal. Accordingly, a reset signal for re-synchronization of data take-in timing is output.

Description

BRIEF DESCRIPTIONS OF THE DRAWINGS

FIGS. 1 is a view for illustrating the present invention.

FIG. 2 is a diagram for illustrating the DVD-RAM format.

FIGS. 3 to 7 are diagrams for illustrating the present invention.

FIG. 8 is a block diagram showing the configuration of an example of the present invention.

FIG. 9 is a block diagram showing the configuration of an SY0 detection/decision circuit shown in FIG. 8.

FIG. 10 is a timing chart for illustrating the operation of the example of the present invention.

FIG. 11 is a timing chart for illustrating the resetting operation of the example of the present invention.

FIG. 12 is a schematic view for illustrating the state-of-the-art synchronization detection.

FIG. 13 is a block diagram showing the configuration of a conventional synchronization detection circuit.

FIG. 14 is a timing chart showing the operation of the synchronization circuit of FIG. 13.

FIG. 15 is a diagram for illustrating a synchronization frame of DVD select data.

FIG. 16 is a schematic view showing an error pattern for 14T.

FIG. 17 is a schematic view showing an error pattern for 12-16T.

FIG. 18 is a diagram showing a case where the 14T part of a signal pattern has been deviated by 1T towards back.

FIG. 19 is a diagram showing a case where a part of the signal pattern ahead of the 14T part has been deviated by 1T towards back.

FIGS. 20A and 20B are schematic block diagrams for comparative illustration of the conventional configuration of e.g., Patent Document 1 and the present invention.

Claims

1. A synchronization detection circuit for detecting a synchronization signal from serial data received, comprising: a circuit that collates said serial data with a predetermined matching pattern, in a synchronization detection window, and that generates a detection level which takes on a value corresponding to the degree of conformity between said serial data and said matching pattern; anda circuit that determines a pattern, the detection level of which exceeds a predetermined threshold value, to be a synchronization signal pattern, when such pattern is detected from said serial data.

2. The synchronization detection circuit according to claim 1, further comprising: a circuit that retains a maximum value of a past detection level during the time before detection of a synchronization signal pattern; anda circuit that updates, on detection of a pattern with a detection level thereof being higher than said maximum value, as retained, said past detection level, and based on a premise that the detection of the pattern with said higher detection level can be supposed to indicate detection of a provisional synchronization signal pattern, outputs a signal for re-synchronizing data take-in timing.

3. The synchronization detection circuit according to claim 1, wherein a bit pattern corresponding to at least a synchronization signal at the leading end of a sector is divided into a plural number of regions, as matching patterns, each being of a preset bit length;scores 1 or 0 are afforded in accordance with coincidence or non-coincidence with said matching pattern in each region, respectively; andthe sum of the scores for entirety of said regions of said matching patterns is set as said detection level.

4. The synchronization detection circuit according to claim 1, wherein a bit pattern corresponding to concatenation of a pre-sync pattern provided in a header and a synchronization signal (SY0) pattern at the leading end of a sector is divided into a plural number of regions, as matching patterns, each being of a preset bit length;scores 1 or 0 are afforded in accordance with coincidence or non-coincidence with said matching pattern in each region, respectively; andthe sum of the scores for entirety of said regions of said matching patterns is set as said detection level.

5. The synchronization detection circuit according to claim 1 wherein said synchronization detection window corresponds to a time interval indicating a relatively high probability of detection of a synchronization signal.

6. A recording and/or reproducing apparatus comprising a synchronization detection circuit as set forth in claim 1.

7. A method for synchronization detection comprising the steps of: generating a synchronization compensation signal when a window for a synchronization signal (SY0) at the leading end of a sector is opened;detecting a pattern proximate to the synchronization signal and comparing a pattern detected with a pattern detected in the past;adjusting data take-in timing from said serial data in case the pattern as newly found is determined to be more proximate to the correct synchronization signal; andsetting the synchronization signal, detected by said previous step, as a correct synchronization signal.

8. A method for synchronization detection comprising the steps of: receiving input serial data and a synchronization detection window indicating a region of a high probability of detection of a synchronization signal, as input;collating said input serial data with a predetermined matching pattern, in the synchronization detection window, and generating a detection level which takes on a value corresponding to the degree of conformity between said serial data and said matching pattern; anddetermining a pattern, the detection level of which exceeds a predetermined threshold value, to be a synchronization signal pattern, when such pattern is detected from said serial data.

9. The method according to claim 8, further comprising the steps of: retaining a maximum value of a past detection level during the time before detection of a synchronization signal pattern;updating said past detection level in case a bit pattern with the detection level thereof being higher than said maximum value, as retained, is detected, and based on a premise that the detection of the pattern with said higher detection level can be supposed to indicate detection of a provisional synchronization signal pattern, re-synchronizing data take-in timing.

10. The method according to claim 8, wherein a bit pattern corresponding to at least a synchronization signal (SY0) at the leading end of a sector is divided into a plurality of regions, as matching patterns, each being of a preset bit length;scores 1 or 0 are afforded in accordance with coincidence or non-coincidence with a matching pattern in each region, respectively; andthe sum of the scores for entirety of said regions of said matching patterns is set as said detection level.

11. The method according to claim 8, wherein a bit pattern corresponding to concatenation of a pre-sync pattern provided in a header and a synchronization signal (SY0) pattern at the leading end of a sector is divided into a plural number of regions, as matching patterns, each being of a preset bit length;scores 1 or 0 are afforded in accordance with coincidence or non-coincidence with a matching pattern in each region, respectively; andthe sum of the scores for entirety of said regions of said matching patterns is set as said detection level.