Circuit and method for powering up an integrated circuit and an integrated circuit utilizing same

Description

FIELD OF THE INVENTION

The present invention generally relates to the field of integrated circuits. More specifically, the present invention relates to a circuit and a method of facilitating the power-up of an integrated circuit having multiple circuit blocks and/or segments, such as analog and digital logic circuit blocks and/or segments.

BACKGROUND

Since the development and fabrication of the first integrated circuit (“C”), also know as a “microchip,” back in the early 1970, integrated circuits have become essential components in also every device, product and system produced by the human race. As the number of applications for integrated circuits has increased (ranging form computing and control systems, analog and digital signal conditioning and processing, and data storage), so has their complexity. Because of their complexity, modern day integrated circuits, such as the non-volatile memory (“NVM”) integrated circuit shown in FIG. 1, may include tens of millions of transistors organized into tens or hundreds of related and interconnect circuits and/or circuit blocks.

The NVM circuit shown in FIG. 1 includes an array of NVM cells, an analog circuit block, a digital logical circuit block, and a power-up circuit block. The analog circuit block may include charge pumps and sense amplifiers needed to program/erase and read the NVM array. The digital logic circuit block may include a controller adapted, among other things, to: (1) coordinate the flow of data between an external interface and the NVM array, (2) multiplexers for accessing specific rows and columns of the NVM array, and (3) control logic to coordinate the operation and monitor various analog circuits, such as charge pumps and sense amplifiers, in the analog circuit block. Many circuits and/or circuit blocks within an IC, such as exemplified by the NVM circuit shown in FIG. 1, require different supply voltage levels to operate properly. Thus, a power-up circuit segment may monitor the supply voltage being applied to an IC and may provide an enable/reset signal to one or more of the circuits or circuit blocks when the supply voltage reaches a respective circuit's or circuit block's required voltage level. The power-up circuit may also provide an accurate reference voltage to be used by enabling circuitry associated with each of the circuits or circuit blocks

Turning now to FIG. 2, there is shown a power-up circuit segment 200 according to the prior art. According to the exemplary prior art circuit of FIG. 2, during power-up, while VDD beings ramping upward, a power reset circuit block 210 provides an enable signal to a comparator 220 once the power reset circuit block 210 determines that VDD has reached a sufficiently high voltage level for the comparator 220 to be reliably operative. The comparator 220 may receive as an input on a first terminal some fraction of VDD, where the fraction is set by a voltage divider 240. On a second terminal, the comparator 220 may receive a reference voltage, where the reference voltage may be set according to the threshold voltage (e.g. 0.4V) of a transistor 230. According to the power-up circuit of FIG. 2, once VDD reaches some multiple (defined by the voltage divider) of the threshold voltage of transistor 230, the comparator may output a bandgap enable signal, which signal is intended to activate a bandgap reference circuit 250. The output of the bandgap reference may be used as an accurate reference voltage for determining when other circuits or circuit blocks may be enabled.

Because a bandgap circuit 250, such as the one shown in FIG. 2, requires a certain supply voltage level (e.g. 1.4 volts) to operate properly, the voltage divider 240 and the transistor 230 threshold voltage may be selected such that the comparator may enable the bandgap circuit 250 once VDD reaches that certain supply voltage level (e.g. 1.4 volts). However, due to the fact that a transistor's 230 threshold voltage may fluctuate up or down based on a number of parameters, including fabrication process deviations and operating temperature, the voltage level at which the comparator 220 may enable a bandgap reference circuit 250 may deviate by several hundred millivolt, up or down. This deviation may cause the bandgap reference operate improperly and may cause other circuits or circuit blocks to be enabled when VDD is below their respective nominal operating voltages.

There is a need in the field of IC design for a power-up circuit and method to provide a relatively accurate reference voltage and/or to facilitate circuit/circuit-block enabling signals.

SUMMARY

The present invention is a circuit and method for providing a reference voltage and/or one or more circuit/circuit-block enabling signals for an IC. According to some embodiments of the present invention, the voltage level VDD of an IC's power supply line may transition from a floating or close-to-zero voltage to an operating voltage level (e.g. 1.8 Volts) when an external power source is applied through connectors to the supply line. As the voltage level on the power supply line ramps upward towards or above a nominal operating voltage, a first threshold voltage detector circuit segment may be activated and may begin to generate a bandgap reset signal once the voltage level of the power supply reaches a first threshold voltage level. The bandgap reset signal may trigger the power-up and operation of a bandgap reference circuit segment, and according to further embodiments of the present invention, a second threshold voltage detector circuit segment, which second threshold voltage detector circuit segment may be matched with the first voltage detector circuit, may generate a voltage reset signal indicating that the bandgap reference source is powering-up.

According to some embodiments of the present invention, once the IC power supply line reaches a second threshold voltage level, the first threshold voltage detector circuit segment may disable the bandgap-reset signal. When the power supply line voltage level reaches a third threshold voltage level, which third threshold voltage level may be correlated to the output voltage level of the bandgap circuit output, the second threshold voltage detector circuit segment may either disable or otherwise modulate the voltage reset signal so as to indicate that the bandgap reference circuit is operating and providing a substantially stable reference voltage (e.g. 1.2 Volts).

The second threshold voltage level may be nearly or substantially equal to the output voltage of the bandgap reference (e.g. 1.2 Volts). According to some embodiments of the present invention, the third threshold voltage level may either be substantially equal to the second threshold voltage level or may be equal to the bandgap reference voltage output (e.g. 1.2 Volts) plus some voltage margin (e.g. 0.3 Volts).

According to further embodiments of the present invention, if the voltage level on the IC power supply line falls below the third threshold voltage level, the second threshold voltage detector circuit segment may modulate the voltage reset signal to indicate that the output of the bandgap reference circuit may be below its defined output voltage level, and the first threshold voltage detector circuit segment may again produce a bandgap reset signal.

According to some embodiments of the present invention, the voltage reset signal generated by the second voltage threshold detector circuit segment may enable the first threshold voltage detector circuit segment to generate a bandgap reset signal.

BRIEF DESCRIPTION OF THE DRAWINGS

The subject matter regarded as the invention is particularly pointed out and distinctly claimed in the concluding portion of the specification. The invention, however, both as to organization and method of operation, together with objects, features and advantages thereof, may best be understood by reference to the following non limiting detailed description when read with the accompanied drawings in which:

FIG. 1 shows a block diagram representing a general arrangement of circuit blocks on a non-volatile memory (“NVM”) integrated circuit, including an: (1) NVM array, (2) analog circuit block, and (3) digital logic circuit block, and (4) a power-up circuit segment;

FIG. 2 shows a general circuit level diagram of an exemplary power-up circuit segment according to the prior art;

FIG. 3 shows a circuit level diagram of an exemplary voltage threshold detection circuit segment according to some embodiments of the present invention, including two sets of current mirrors in series with each other, where one branch of the current mirrors is connected to an inverter;

FIG. 4 shows a circuit level diagram of an exemplary voltage threshold detection and voltage reference source supply circuit according to some embodiments of the present invention, where the circuit includes two interconnected threshold voltage detection circuit segments and a bandgap reference circuit segment;

FIG. 5 shows a flow diagram including the steps of a method by which a power-up circuit according to some embodiments of the present invention may operate;

FIG. 6 shows a set of correlated voltage vs. time graphs indicating exemplary relationships between the various voltage levels at various points on a power-up circuit according to some embodiments of the present invention.

It will be appreciated that for simplicity and clarity of these non-limiting illustrations, elements shown in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals may be repeated among the figures to indicate corresponding or analogous elements.

DETAILED DESCRIPTION OF THE INVENTION

In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be understood by those skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the present invention.

Turning now to FIG. 3, there is shown a circuit level diagram of an exemplary voltage threshold detection circuit segment according to some embodiments of the present invention, including three analog branched, two of which are current mirrors in series with each other, where one branch of the current mirrors is connected to an inverter. The first analog branch may be defined by elements R1 and N2; the second by elements P5, N5 and N3; and the third branch may be defined by elements P6, P2 and N4.

According to some embodiments of the present invention, transistors P5 and P6, at the top of the second and third current mirrors branches, may not be identical in size (i.e. channel width/length), but rather P6 may be designed to be larger than P5. The ratio between P5 and P6 may be for example 1.2 or any other ratio which may be determined optimal for a specific: (1) purpose, (2) set of voltages and/or (3) a specific fabrication technology.

The asymmetry between the three branches may results in each of the three branches beginning to conduct current when VDD reaches each of three different voltage levels. During operation of the circuit of FIG. 3, the first analog branch of the circuit may be the first to begin conducting, for example when VDD reaches or exceeds a minimum conducting voltage VDD_min_—1, which minimum conducting voltage may be defined by the formula VDD_min_—1=Vtn_lv+Vdsat (first branch, R1,N2), where, Vtn_lv is the threshold voltage of low voltage NMOS, Vtp_hv is the threshold voltage of high voltage PMOS and Vdsat is the drain-source saturation voltage.

For typical parameter values such as: Vtn_lv=0.4v, Vtp_hv=0.7v and Vdsat=0.05v, VDD_min_—1 would equal about 0.45v. According to some embodiments of the present invention, the minimum conducting VDD voltages levels for the second branch (VDD_min_—2) and the third branch (VDD_min_—3) to begin conducting may be defined by the formulas:

- When V_ref=0:
  
  VDD_min_—2=Vtp_—hv+2*Vdsat; (second branch, P5,N5,N3)
  VDD_min_—3=Vtp_—P2+Vdsat_—P6+Vdsat_—N4 (third branch, P6,P2,N4)
- When V_ref>0:
  
  VDD_min_—2=Vtp_—hv+2*Vdsat (second branch, P5,N5,N3)
  VDD_min_—3=V_—ref+(Vtp_—P₂+Vdsat_—P2+Vdsat_—P6+Vdsat_—N4)

Thus, for the typical parameter values listed above and when V_ref is equal to 0: VDD_min_—2 may equal 0.8v, and VDD_min_—3 may equal 0.8v.

The operation of the circuit in FIG. 3, and more specifically the interrelation of the voltage level at various nodes of the circuit, may be described in view of the interrelated voltage graphs shown in FIG. 6. While VDD is in the range of 0v<VDD<VDD_min_—1 (e.g. the circuit is being powered up) currents I1, I2, I3 may be close to zero and the output voltage of the inverter (V_reset) may not be well defined. Once VDD exceeds the threshold voltage of transistor N2 (e.g. 0.4v) (i.e. VDD=VDD_min_—1@ Time=T1), current may begin to flow through N2 and this current flow may be mirrored in the second and third branches, through N3 and N4, respectively. Current flow through N4 combined with a closed P6 may cause the voltage at V_sense to be pulled close to ground, resulting in the output of the inverter whose input is connected to V_sense to generate a V_reset voltage associated with logical “1.” It should be understood by one of ordinary skill in the electrical arts that the selection of which logical state (i.e. 0 or 1) output by the inverter should be correlated with which V_reset voltage level may be arbitrary. According to the example of FIG's. 3 and 6, a close to 0 voltage level may be considered a logical “0,” while a close to VDD voltage level may be considered a logical “1.” Thus, when V_sense is pulled close to zero, the voltage level associated with V_reset may be close to VDD.

Until VDD reaches VDD_min_—2 (e.g. VDD=0.8v@T=T2), the second branch may stay out of saturation and V_sense may continue to be pulled down to near ground by NMOS N4, and thus V_reset may remain associated with logical “1” at a voltage level close to VDD. However, once VDD reaches and/or exceeds VDD_min_—2 (e.g. VDD>0.8v@T>T2), transistors P5 may begin to conduct and current I2 in the second branch may begin flow. Since P6, which is part of a current mirror with P5, is larger than P5, when P5 starts conducting, P6 may begin to conduct at least as much current as P5, and according to some embodiments of the present invention, current may flow through P5 and P6 according to the size ration of P5:P6. Once P6 begins to conduct, V_sense may be pulled up to near VDD and the output of the inverter may change to logical “0,” close to 0 volts.

Thus, according to embodiments of the present invention, when V_ref=0v, V_reset=‘1’ may be well defined for VDD range. VDD_min_—1 (0.4v)<VDD<VDD_min_—2 (0.8v). According to embodiments of the present invention where V_ref>0, V_reset=‘1’ may be well defined for VDD range VDD_min_—1 (0.4v)<VDD<V_ref+(Vtp_P2+Vdsat_P2+Vdsat_P6). Thus, V_ref's voltage level may be used to adjust the VDD voltage range at which V_reset=‘1.’

According to some embodiments of the present invention, the voltage threshold detection circuit may include an NMOS transistor N5 that may be used for compensation of corner dependence between NMOS and PMOS transistors. Transistors P3 and P4 may be used to add hysteresys to the voltage threshold detection circuit segment.

Turning now to FIG. 4, there is shown a circuit level diagram of an exemplary voltage threshold detection and voltage reference source supply circuit according to some embodiments of the present invention, where the circuit includes two interconnected threshold voltage detection circuit segments and a bandgap reference circuit segment. The exemplary voltage threshold detection and voltage reference source supply circuit may be described in view of FIG. 5, where FIG. 5 shows a flow diagram including the steps of a method by which a power-up circuit according to some embodiments of the present invention may operate, and in view of FIG. 6, which shows a set of correlated voltage vs. time graphs indicating exemplary relationships between the various voltage levels at various points on a power-up circuit according to some embodiments of the present invention.

The second voltage threshold detection circuit segment of FIG. 4 is substantially identical to the voltage threshold detection circuit segment described above in connection with FIG. 3. The first voltage threshold detection circuit segment of FIG. 4 is also substantially similar to the one describer in connection with FIG. 3, with the following exceptions. (1) it has two analog branches instead of three; (2) the gate of P9 (corresponding to P2 in FIG. 3) is grounded rather than being connected to a V_ref node, as shown in FIG. 3 (i.e. V_ref for the first threshold voltage detection circuit segment is effectively ground or 0 volts); (3) the two branches of the first voltage threshold detection circuit segment include transistors N6 and N7 whose gates are connected to each other and to the output of the inverter of the second threshold voltage detection circuit segment; and (4) instead of having an inverter, as described in connection with FIG. 3, the first threshold voltage detection circuit segment includes an “AND” logical unit, where a first of the logic unit's two inputs is connect to the output of the inverter of the second threshold detection circuit segment and the second logic unit input is inverted and connected to the V_sense2 node of the first threshold voltage detection circuit segment.

Thus, once VDD reaches a first threshold voltage (i.e. time T1 in FIG. 6), generally defined as the voltage at which the first analog branch of the second threshold voltage detection circuit segment begins to conduct, partly for the reasons stated above in connection with FIG. 3: (1) V_reset on the second threshold voltage detection circuit segment goes “high,” and in-turn turns on transistors N6 and N7, and provides an enable signal to a first input of the first threshold voltage detection circuit segment's “AND” logic unit; (2) transistor N8 and N9, which are connected in a current mirroring configuration with gates connected to N2, begin to conduct and to pull node V_sense2 to ground; (3) the second input to the “AND” logic unit goes “low”, (4) but since the second input of the “AND” logic unit is inverted, the output of the “AND” logic unit goes “high”. The output of the “AND” logic unit going “high” may be referred to as a bandgap reset signal (FIG. 5: Step 1000). According to the exemplary embodiment shown in FIG. 4, once the output of the “AND” logic unit goes “high”, the output of the “AND” logic unit may cause transistor N5 to conduct, thereby activating and/or resetting the bandgap reference source.

According to some embodiments of the present invention, V_reset signal may be used to indicate to associated circuits that a bandgap reference is being initiated, while the bandgap reference signal may be used to start initiating a bandgap reference. It should be understood by anyone of ordinary skill in the art that both the V_reset signal and the bandgap reference signal may be used to other purposes including signaling associated circuit segments to begin powering up.

The exemplary bandgap reference source shown in FIG. 4 may be referred to as a Vbe reference, and its operation may be understood using the Ebers-Moll diode equation:

- Where, diode (D2)>diode (D1) (for example, D2=24×D1) and P7=P8=P9. In static state. Vd1=Vd2 is possible in two cases for diodes D1 and D2: Vd1=Vd2 when Id=0 or Id=I1
- The voltage level VDD of an IC's power supply line may transition from a floating or close-to-zero voltage, when currents in diodes D1 and D2 are close to zero and floating voltage Vd1 can be equal to floating voltage Vd2. This stable state occurs in this kind of a circuit when comparator A2 raises ‘pbias_ref’ net in order to keep zero current in diodes D1 and D2.
- Therefore, it is necessary to force down the “Pbias_ref’ net until VDD voltage level rises high enough for the functionality of comparator A2.
- When the ‘Pbias_ref’ net is forced to the ground, transistors P7 and P8 are completely opened and currents through diodes D1 and D2 may produce differential voltage for comparator (A2).
- When the supply voltage reaches a second threshold voltage level (which is enough for the functionality of comparator A2), Bg_reset signal closes NMOS N5 (Unit 103) and releases voltage reference circuit (Unit 100). If VDD voltage level is still lower than the needed voltage level for the normal operation of this circuit, voltages Vd1 and Vd2 may not be equal due to low currents in diodes D1 and D2. Comparator (A2) begins to lower the “Pbias_ref’ net in order to increase the currents in diodes D1 and D2.
- Therefore, while VDD is below the required voltage level, transistors P7, P8 and P9 stay completely opened and the reference output voltage follows the VDD supplier.
- When the VDD supply reaches the required voltage level, comparator A2 increases the ‘Pbias_ref’ net voltage in order to maintain a constant current in diodes D1 and D2 and a respectively constant output reference voltage V_bg.

It should be understood by one of ordinary skill in the art that any bandgap reference source, known today or to be devised in the future may be applicable to the present invention. The exemplary bandgap reference source shown as unit FIG. 4 may be replaced by any functionally equivalent source.

The output of the bandgap reference source may be connected to the bandgap reference follower, which bandgap reference follower may act as an output stage operating as a current buffer to mitigate current flow from the bandgap reference source. The bandgap reference follower may include an operation amplifier where one of the amplifiers inputs is the output of the bandgap reference source and the second input is direct in a direct feedback loop from the operational amplifier's output. The output of the operational amplifier may lead to ground through transistors P1 and N1, and the gate of P1 may be connected to its own drain and to the V_ref node of the second threshold voltage detection circuit segment. Because, according to the exemplary embodiment of FIG. 4, the output of the operational amplifier is connected to the V_ref node through transistor P1, which transistor P1 introduces a voltage drop, through the selection of P1, V_ref may be adjusted to be lower than the output voltage of the bandgap reference source A sample and hold circuit may sample a voltage level to be used as the applied voltage for the V_ref node in the second threshold voltage detection circuit segment.

Thus, once VDD reaches a second threshold voltage level (e.g. VDD is near or equal to the bandgap reference source output voltage), point T2 in FIG. 6, transistors P5, P6, P10 and P11 may turn on. P11 may pull up node V_sense2 to VDD, and node V_sense2 being pulled to VDD may cause the output of the “AND” logic unit in the first threshold voltage detection circuit segment to go “low”, thereby shutting off the bandgap reset signal (FIG. 5: Step 2000).

Although when VDD reaches a second threshold voltage transistor P6 may conduct, while P2 is still shut off, node V_sense1 may not by pulled up to VDD. Depending upon the voltage level V_ref applied to P2, it may be required that VDD reach a third threshold voltage, a voltage level equal to the Second Threshold Voltage+Margin (See FIG. 6), before P2 begins to conduct. According to some embodiments of the present invention, the voltage level VDD should reach (FIG. 6: T=T3) before P2 may begin conducting may be defined by the above listed formulas relating to FIG. 3. According to some embodiments of the present invention, the Margin voltage may be substantially zero. According to further embodiments of the present invention, if V_ref is a non-negligible value, the Margin voltage may be several hundred millivolts and the third threshold voltage may not be substantially equal to the second threshold voltage

Once VDD reaches the third threshold voltage, whether or not the third threshold voltage is substantially equal to the second threshold voltage, transistor P2 may turn on and V sense1 may be pulled up to VDD, thereby causing the output of the inverter to go “low”. The output of the inverter going low may be perceived as the shutting off or modulation of a V_reset signal according to some embodiments of the present invention (FIG. 5: Step 3000). The shutting off or modulation of the V_reset signal may indicate to associated circuits that the Bandgap reference is operational and outputting a stable reference voltage

According to some embodiments of the present invention, should VDD begin to drop below the third threshold level (e.g. a voltage sufficient for the bandgap reference to operate+Margin voltage), as shown in FIG. 6 at T+T6, the V_reset signal may modulate to indicate that the output of the bandgap reference is not totally reliable (FIG. 5: step 4000). Should the VDD drop below the second threshold voltage, the bandgap-reset signal may be activated.

While certain features of the invention have been illustrated and described herein, many modifications, substitutions, changes, and equivalents will now occur to those of ordinary skill in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit of the invention.

Claims

1. A method of providing a reference voltage to an integrated circuit (“IC”) comprising: i generating a bandgap reset signal and a voltage reset signal once a supply voltage of the IC reaches a first threshold voltage level; ii disabling the bandgap reset signal once the supply voltage reaches a second threshold voltage level, which second threshold voltage level is sufficient for an associated bandgap reference circuit segment to produce a substantially stable reference voltage; and iii modulating the voltage-reset signal once the supply voltage reaches a third threshold voltage so as to indicate that the bandgap reference circuit segment is operational.
2. The method according to claim 1, wherein the third threshold voltage is greater than the second threshold voltage by some voltage margin value.
3. The method according to claim 2, wherein the voltage margin value is selected such that once the supply voltage reaches the third threshold value the bandgap reference circuit segment has substantially established a steady state output.
4. The method according to claim 1, wherein the third threshold voltage is substantially equal to the second threshold voltage.
5. The method according to claim 1, wherein as part of generating a voltage reset signal an input node of a logic device is pulled to down to ground.
6. The method according to claim 5, wherein as part of modulating the voltage reset signal, the input node of the logic device is pulled up to the supply voltage level.
7. The method according to claim 1, wherein as part of generating a bandgap reset signal an input node of a logic device is pulled to down to ground.
8. The method according to claim 7, wherein as part of disabling the bandgap reset signal the input node of the logic device is pulled up to the supply voltage.
9. A circuit for providing a reference voltage to an integrated circuit (“IC”) comprising: i a first voltage threshold detection circuit segment adapted to generate a bandgap reset signal once a supply voltage of the IC reaches a first threshold voltage level and to disable the bandgap reset signal once the supply voltage reaches a second threshold voltage level, which second threshold voltage level is sufficient for an associated bandgap reference circuit segment to produce a substantially stable reference voltage, and ii a second voltage threshold detection circuit segment adapted to generate a voltage reset signal once the supply voltage of the IC reaches the first threshold voltage level and to modulate the voltage reset signal once the supply voltage reaches a third threshold voltage level so to indicate that the bandgap reference is operational.
10. The circuit according to claim 9, wherein said first voltage threshold detection circuit segment comprises two or transistor mirrors and a logic device.
11. The circuit according to claim 9, wherein said second voltage threshold detection circuit segment comprises two or transistor mirrors and a logic device.
12. The circuit according to claim 9, further comprising a bangap reference follower circuit segment.
13. The circuit according to claim 12, wherein said bandgap reference follower includes a voltage offset element adapted to introduce a voltage margin between the first and second threshold voltages.
14. An integrate circuit comprising: i non-volatile memory circuitry; ii a first voltage threshold detection circuit segment adapted to generate a bandgap reset signal once a supply voltage of the IC reaches a first threshold voltage level and to disable the bandgap reset signal once the supply voltage reaches a second threshold voltage level, which second threshold voltage level is sufficient for an associated bandgap reference circuit segment to produce a substantially stable reference voltage, iii a second voltage threshold detection circuit segment adapted to generate a voltage reset signal once the supply voltage of the IC reaches the first threshold voltage level and to modulate the voltage reset signal once the supply voltage reaches a third threshold voltage level so to indicate that the bandgap reference is operational; and iv wherein said non-volatile memory circuitry utilizes an output signal from the bandgap reference circuit segment.
15. The circuit according to claim 14, wherein said first voltage threshold detection circuit segment comprises two or transistor mirrors and a logic device.
16. The circuit according to claim 14, wherein said second voltage threshold detection circuit segment comprises two or transistor mirrors and a logic device.
17. The circuit according to claim 14, further comprising a bangap reference follower circuit segment.
18. The circuit according to claim 17, wherein said bandgap reference follower includes a voltage offset element adapted to introduce a voltage margin between the first and second threshold voltages.

Circuit and method for powering up an integrated circuit and an integrated circuit utilizing same

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CPC

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