Patent Application
20070152646
The present invention relates generally to voltage regulators, and more particularly, to controlling the timing of voltages supplied by a voltage regulator.
Voltage regulators are essential to the operation of most electronic devices. They convert a source voltage into a regulated DC voltage that is required to meet the devices' operating needs. An electronic device may need more than one voltage regulator, with each one providing a regulated DC voltage for a different component of the device. There are many types of voltage regulators available today, with switching voltage regulators being amongst the most popular.
It is often required to control the power-up and power-down timing of voltage regulators, especially when they are used in complex electronic devices, such as computers, portable communication devices, and integrated circuits (“ICs”), including microprocessors, application-specific integrated circuits (“ASICs”), and field-programmable gate arrays (“FPGAs”). These devices typically have multiple interconnected components, each with its own power needs. For example, many electronic devices supply power to different components in a predetermined time sequence when the electronic device is turned on. When initially powering-up the device, it is desirable to sequentially power up each component and wait until the power to one component stabilizes before supplying power to another component. Doing so may avoid latch-up and potentially damaging power spikes in the electronic devices.
Examples of prior-art circuits that control the power-up and power-down timing of voltage regulators include those disclosed in U.S. Pat. Nos. 4,151,425, 6,429,706, 6,462,438, and 6,691,239. These prior-art circuits, commonly referred to as “voltage sequencing circuits” as they sequence the timing of voltages supplied to loads, are typically external to voltage regulators and may require several resistors, capacitors, and other discrete components to control. Such circuits are complex and may require a significant amount of silicon die area to be implemented.
There is therefore a need to provide a simple circuit for controlling the timing of voltages supplied to loads with a voltage regulator.
In view of the foregoing, the present invention provides a circuit for use with a voltage regulator, the voltage regulator including a first input adapted to receive a source voltage, a second input adapted to receive an enable voltage and an output for producing a regulated output voltage from the source voltage, the circuit comprising a reference input adapted to receive a reference voltage, a comparator coupled to the second input for generating an output based on a comparison of the enable voltage at the second input with the reference voltage at the reference input and a delay enable circuit coupled to the comparator for receiving the output from the comparator and delaying the regulated output voltage based on such output.
In one embodiment, the circuit may be used to provide a delay that is set by the combination of the enable voltage and the reference voltage, with the enable voltage provided by a voltage divider externally coupled to the second input. In another embodiment, the circuit may be used to provide a delay that is set by a capacitor externally coupled to the second input and charged by a current source internal to the voltage regulator.
The accompanying drawings, which are somewhat schematic in some instances and are incorporated in and form a part of this specification, illustrate several embodiments of the invention and, together with the description, serve to explain the principles of the invention.
Generally, in accordance with exemplary embodiments of the present invention, a circuit and a method are provided for controlling the timing of voltages supplied to loads with a voltage regulator. As stated herein, a voltage regulator generally refers to a circuit used to convert a source voltage into a regulated output voltage. The source voltage coupled to the voltage regulator may be a fluctuating voltage, e.g., such as that provided by a power supply connected to a wall socket, or at a given amplitude, e.g., 5 Volts. A linear voltage regulator, as used herein, generally refers to a voltage regulator designed with one or more transistors operating in their linear region. A switching voltage regulator, as used herein, generally refers to a voltage regulator designed with one or more switching elements and one or more energy storage and transfer elements between the source voltage and an output load.
In an exemplary embodiment of the present invention, a voltage regulator may have an enable input pin to receive an enable voltage for indicating whether to enable or disable the voltage regulator. In accordance with the present invention, the enable voltage can be used to generate time delays for delaying the regulated output voltage generated by the voltage regulator.
An exemplary schematic diagram of a voltage regulator in accordance with the present invention is provided in
Switching element 120 may be of any suitable type, such as, for example, a metal-oxide semiconductor field-effect transistor (“MOSFET”), a field-effect transistor (“FET”), and a bipolar junction transistor (“BJT”), among others. Energy storage/transfer element 125 may include, for example, an inductor, a capacitor, and a transformer, or any combination thereof. Control circuit 130 may include circuitry to enable or disable the switching regulator based on the enable voltage EN at input 110 and circuitry to control the ON and OFF times of switching element 120. Such circuitry may include, for example, pulse width modulation (“PWM”), pulse frequency modulation (“PFM”) control circuitry, or linear control circuitry used with low dropout voltage regulators.
In accordance with the present invention, switching voltage regulator 100 also includes means for delaying the regulated output voltage based on the enable voltage. The means for delaying the regulated output voltage may include delay circuit 135 coupled between input 110 and output 115, which provides time delays for controlling the timing of regulated output voltage Vout at output 115. In one exemplary embodiment, delay circuit 135 may generate up to four different time delays depending on four different ranges for the enable voltage EN applied to enable input 110. In another exemplary embodiment, delay circuit 135 may generate a time delay according to the time it takes to charge a capacitor coupled to enable input 110.
It is appreciated that switching element 120, energy storage and transfer element 125, and control circuit 130 may form voltage regulator 140 coupled to delay circuit 135. It is also appreciated that delay circuit 135 may be internal to a switching voltage regulator, such as shown internal to switching voltage regulator 100 or external to a switching voltage regulator, such as shown external to voltage regulator 140. Further, it is appreciated that delay circuit 135 may be used with other types of voltage regulators, including linear voltage regulators, without deviating from the principles and embodiments of the present invention.
An exemplary schematic diagram of one embodiment of delay circuit 135 for use with a voltage regulator in accordance with the present invention is illustrated in
Comparators 215, 220, 225, and 230 compare the enable voltage EN at input 110 with reference voltages V1-V4, respectively. Reference voltages V1-V4 have a range ranging from a minimum reference voltage and a maximum reference voltage. When the enable voltage EN falls between the minimum reference voltage and the maximum reference voltage at a given comparator, a time delay is generated by a delay element coupled to the comparator, such as delay element 235 coupled to the output of comparator 215, delay element 240 coupled to the output of comparator 220, delay element 245 coupled to the output of comparator 225, and delay element 250 coupled to the output of comparator 230.
For example, when the enable voltage EN is within the range of V1, delay element 235 will generate a delay for delaying the regulated output voltage Vout at output 115 by that delay. And when the enable voltage EN is within the range of V2, delay element 240 will generate a delay for delaying the regulated output voltage Vout at output 115 by that delay. Delay selector 255 may be used to select the time delay generated by a given delay element, i.e., delay elements 235, 240, 245, and 250, to apply to the regulated output voltage Vout at output 115. Table 1 below shows exemplary values of enable voltage EN at input 110 and respective reference voltages V1-V4 to generate time delays D1-D4 that are applied to regulated output voltage Vout at output 115.
As seen in Table 1, the reference voltages V1-V4 have a range ranging from a minimum reference voltage and a maximum reference voltage. For example, when enable voltage EN at input 110 has a value, for example, within the range 0.8 Volts +/−0.2 Volts of reference voltage V1, a time delay D1 of 5 milliseconds is generated. That is, regulated output voltage Vout at output 115 will be delayed by 5 milliseconds. As understood by one of ordinary skill in the art, enable voltage EN at input 110 and reference voltages V1-V4 may have different values than those shown in Table 1 to generate time delays D1-D4, which may also take on different values than those shown in Table 1. The values shown in Table 1 are shown for illustration purposes only, and other values may be used without deviating from the principles and embodiments of the present invention.
It is appreciated that voltage regulator 140 shown in
An exemplary schematic diagram of three voltage regulators coupled to a single source voltage to generate three regulated output voltages at three given time delays in accordance with the exemplary embodiment of delay circuit 200 shown in
In accordance with the principles and embodiments of the present invention, voltage regulators 300, 305 and 310 generate regulated output voltages Vout
For example, a voltage divider formed by resistors 315 and 320 is used to generate an enable voltage EN that, when input at voltage regulator 300 at input 365, is used by delay circuit 120 internal to voltage regulator 300 to delay the regulated output voltage Vout
It is appreciated that resistor pairs 315 and 320, 325 and 330, and 335 and 340 may take on any value in accordance with delay specifications of voltage regulators 300, 305 and 310 for producing different time delays. For example, resistor pair 315 and 320 may take on a value within a range of a reference voltage V1 shown in Table 1 for generating regulated output voltage Vout
In accordance with the present invention, regulated output voltages Vout
A schematic diagram of another embodiment of delay circuit 135 for use with a voltage regulator in accordance with the present invention is illustrated in
Current source 415 becomes active and starts charging external capacitor 430 when source voltage Vin crosses the programmable undervoltage lockout (“UVLO”) threshold specified for voltage regulator 140. UVLO circuit 410, coupled between input 105 and current source 415, is provided to compare the source voltage Vin with the UVLO threshold, which may be, for example, on the order of 2.5-3.5 Volts.
Upon Vin crossing the UVLO threshold, current source 415 starts charging capacitor 430 up to a reference voltage that is a fraction of Vin, for example, Vin/M, with M an integer, such as M=2, 3, 4, etc. Once capacitor 430 is charged up to reference voltage Vin/M, comparator 420 activates delay enable circuit 425 to generate regulated output voltage 115 with a time delay corresponding to the time it takes to charge capacitor 430 to the reference voltage Vin/M. In this embodiment, delay enable circuit 425 may be, for example, an enable or turn-on cell within switching voltage regulator 100.
For example, for Vin=3.3 Volts and with capacitor 430 being a one microfarad capacitor, a current source of two microamperes may take approximately 412 milliseconds to charge up to a Vin/4 reference voltage of 0.82 Volts before triggering delay enable circuit 425 to allow voltage regulator 400 to output regulated output voltage Vout at output 115. By using a 0.1 microfarad capacitor, the time delay may be reduced to 41.2 mS.
It is appreciated that with this embodiment the time delay generated is set by external capacitor 430. Different time delays may be generated by choosing different values for external capacitor 430.
A schematic diagram of three voltage regulators coupled to a single source voltage to generate three regulated output voltages at three given time delays in accordance with the exemplary embodiment of delay circuit 135 shown in
In accordance with the principles and embodiments of the present invention, voltage regulators 500, 505, and 510 generate regulated output voltages Vout
External capacitor 515, for example, is used to generate an enable voltage EN that, when input at voltage regulator 500 at input 520, generates a delay for delaying the regulated output voltage Vout
It is appreciated that external capacitors 515, 530, and 545 may take on any value for producing different time delays. For example, regulated output voltages Vout
Advantageously, a designer of an electronic device containing several components may, for example, use voltage regulators 500, 505 and 510 to provide different voltages at different times for each component at power-up. The designer may do so by choosing external capacitors that can be charged up to the fraction of the source voltage input at the comparator, such as Vin/M input at comparator 420, by the current source internal to the voltage regulators, such as current source 415.
Another advantage is that delay circuit 135 (
The foregoing descriptions of specific embodiments and best mode of the present invention have been presented for purposes of illustration and description only. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Specific features of the invention are shown in some drawings and not in others, for purposes of convenience only, and any feature may be combined with other features in accordance with the invention. Steps of the described processes may be reordered or combined, and other steps may be included. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. Further variations of the invention will be apparent to one skilled in the art in light of this disclosure and such variations are intended to fall within the scope of the appended claims and their equivalents.
