Patent Application
20050052912
The present invention relates to the field of computer systems. Specifically, embodiments of the present invention relate to a circuit and system for addressing multiple computer memory modules on the same bus while maintaining proper timing.
Resistors are used to avoid problematic reflections and to properly terminate the address signal. A series resistor 120 between the driver 125 and the memory modules 110 serves to dampen reflected signals coming back from the memory modules 110. The parallel resistor 130 coupled to the terminating voltage 140 serves to properly terminate the signal and typically has an impedance to match that of the transmission line 150.
Such a conventional system functions well when the number of memory modules 110 is limited to no more than four memory modules 110. However, the need for ever more memory has led to a desire to place more than four memory modules together in a fashion such that they can all be addresses by a single driver.
Unfortunately, if more than four modules are daisy chained in the configuration of
One conventional technique to increase the number of memory modules in the overall system is to add an additional driver to the system such that a few more memory modules can be addressed within the timing budget. However, this solution is undesirable because the additional driver requires additional space, which is limited in many computer systems.
Thus, one problem with conventional methods of addressing memory in a computer system is that timing skew limits how many memory modules can be addressed using a single driver. Another problem with conventional techniques is that too much space is required by the number of drivers that are required to address the desired number of memory modules.
The present invention pertains to a circuit and system for a heavily loaded memory module address bus. In one embodiment, the circuit comprises a transmission line having a dampening impedance between a driver and a branch point of the transmission line. The circuit also has a termination impedance having one end coupled to the transmission line between the dampening impedance and the branch point. The transmission line has branches from the branch point. Each branch couples to at least one memory module interface.
The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention:
In the following detailed description of embodiments of the present invention, a circuit and system for addressing multiple computer memory modules on the same bus while maintaining proper timing, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, embodiments of the present invention may be practiced without these specific details or by using alternative elements or methods. In other instances well known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the present invention.
Embodiments of the present invention reduce skew when addressing multiple computer memory modules on the same bus while maintaining proper timing, as compared to conventional solutions. Embodiments of the present invention use a single driver to address more than four memory modules. Embodiments of the present invention allow termination resistors to be placed relatively far from the memory modules being addressed. Thus, embodiments of the present invention provide more freedom in selecting the location of termination resistors.
The circuit 200 has a transmission line 320 that is coupled at one end to a driver 305 and coupled to interfaces 330 that are able to receive memory modules 340. The transmission line 320 is unidirectional in embodiments of the present invention. The transmission line 320 has a branch point 315 from which two branches 320c, 320d of the transmission line extend. A first branch 320c extends from the branch point 315 to memory module connector 340a. A second branch 320d extends from the branch point 315 to memory module connector 340i. The first branch 320c electrically connects to memory module connectors 340a, 340b, 340c, and 340d. The second branch 320d electrically connects to memory module connectors 340e, 340f, 340g, and 340h. Thus, each branch 320c and 320d is used to address four memory modules, such that a single driver 305 is used to address eight memory modules 340. Thus, the number of memory modules 340 that can be addressed by a single driver 305 is doubled over the conventional circuit of
Still referring to
Referring briefly to
However, embodiments of the present invention are configured such that reflections between the parallel termination resistor 360 and the memory modules 340 do not cause significant signal integrity problems. For example, the memory modules 340 are located very close to each other relative to the size of the wavelength of a typical signal.
The transmission line 320 branches at branch point to achieve a symmetrical configuration in the various branches of the data line 320, in embodiments in accordance with the present invention. Thus, not only is skew reduced when addressing the memory modules, but the symmetry reduces the complexity in analyzing the system during design and test phases.
In the conventional circuit of
Moreover, in embodiments of the present invention, the configuration of the series dampening impedance 350 and the parallel termination impedance 360 provides flexibility in controlling the magnitude of the signal on the transmission line 320 not available in the conventional circuit of
For clarity,
There may be more or fewer memory module connectors 330 than shown in
Moreover, the dampening and termination impedances can be located on the side of the memory module connectors rather than on the end of the memory modules. For example, referring to the conventional circuit of
In
In embodiments of the present invention, the waveform that is transmitted on the transmission line 320 is a square wave that is used as a data signal. That is, the rising or falling edges of the waveform are not used for clocking purposes. Therefore, the rising and falling edges of the waveform are not critical. However, the top and bottom of the waveform are significant for the data value to be registered properly. Even if there is some deformity in the edges of the waveform, the data value will still be interpreted properly if the tops and bottoms of the waveform do not experience significant distortion. For example, the data value will still be interpreted properly if the tops and bottoms of the waveform are within specification for the memory modules 340 in the circuit 300. The present invention provides for such a waveform in which the tops and bottoms of the waveform have a distortion that is small enough so as to not cause improper values to be registered.
The dampening and termination impedances 350, 360 are electrically coupled by a line through the via 545 in the PC board 510. Placing the dampening and termination impedances 350, 360 on opposite sides of the PC board 510 may allow for a more compact PC board 510 than if both impedances 350, 360 are placed on the same side of the PC board 510, although it is not required that the impedances be located on opposite sides of the PC board 510.
The system 500 includes a transmission line 320 that couples the controller 515 with the memory module connectors 340. A portion of the transmission line 320a is coupled between the controller 515 and the dampening impedance 350. The dampening impedance 350 may also be referred to as a series impedance. Another portion of the transmission line 550b is coupled between the dampening impedance 350 and the memory module connectors 340. This portion of the transmission line 550b run partway through the via 545. A first end of the termination impedance 360 is electrically coupled to the transmission line 550 by termination impedance line 555. A second end of the termination impedance 360 is electrically connected to a termination voltage terminal 570.
The second portion of the transmission line 550 couples to a branch point 315 of the transmission line 320, which branches into two separate parts 320c and 320d. Each branch 320c, 320d of the transmission line couples to four memory module connectors 340, in this embodiment. However, the present invention is not limited to a branch being connected to four memory module connectors. Moreover, the present invention is not limited to only two branches. The embodiment of
While the present invention has been described in particular embodiments, it should be appreciated that the present invention should not be construed as limited by such embodiments, but rather construed according to the below claims.
