Patent Application
20240275267
Power modules are used in a large variety of applications including inverters, DC-DC converters, motor drives, power supplies, uninterruptable power supplies (UPS), and the like. Some of these power modules are constructed with power transistors such as Insulated Gate Bipolar Transistors (IGBTs) or Metal-Oxide-Semiconducting Field-Effect Transistors (MOSFETs), configured as phase-shifted full-bridge (PSFB) peak current mode control (PCMC) DC-DC power converters. For higher voltage outputs, such as 54V outputs, active clamping (ACL) circuits may be used in the output stage of the PSFB PCMC DC-DC power module to ensure safe operation of the output stage transistors while maintaining high efficiency. However, many implementations of this active clamping circuit adversely affect the peak current flowing in the PSFB module.
In an implementation, an electronic system for controlling a power converter having an active clamping circuit includes a current sensor configured to sense current through a primary side of a transformer within the power converter, and a comparator sub-system.
The comparator sub-system is configured to receive a transformer current signal from the current sensor and generate a trip signal based on a difference between the transformer current signal and a reference signal. The electronic system also includes a pulse width modulator configured to generate a gate input signal for the active clamping circuit based at least in part on the trip signal.
In another implementation, a microcontroller unit for controlling a power converter having an active clamping circuit includes a comparator sub-system configured to receive a transformer current signal from a current sensor and generate a trip signal based on a difference between the transformer current signal and a reference signal.
The microcontroller also includes a pulse width modulator configured to generate a gate input signal for the active clamping circuit based at least in part on the trip signal.
In a further embodiment, a method for using a microcontroller unit to control a power converter having an active clamping circuit includes receiving a transformer current signal from a current sensor.
The method also includes generating a trip signal based on a difference between the transformer current signal and a reference signal, and generating a gate input signal for the active clamping circuit based at least in part on the trip signal.
Many aspects of the disclosure can be better understood with reference to the following drawings. While several implementations are described in connection with these drawings, the disclosure is not limited to the implementations disclosed herein. On the contrary, the intent is to cover all alternatives, modifications, and equivalents.
The following descriptions of various example embodiments and implementations of an electronic system for controlling a PSFB PCMC power converter with active clamping illustrate systems and methods for protecting primary transistors within power converters. In these various examples, a pulse width modulator is configured to provide a gate input to an active clamping circuit within a power converter. The active clamping circuit limits the voltage across the secondary bridge within the phase-shifted full-bridge power converter, but distorts the peak current within the transformer. In some examples, a microcontroller unit is configured to control the primary transistors within the power converter along with the active clamping circuit.
By varying the pulse width of the signal controlling the active clamping circuit, the electronic system minimizes effects of the active clamping circuit on the output current of the power converter, providing a technical effect and technical advantage over current solutions. The electronic system controls the active clamping circuit such that it turns on only during an early part of the cycle, providing effective clamping when it is needed the most. Active clamping is turned off during a latter part of the cycle, eliminating distortion in the peak current within the transformer, and helping to retain the linear ramp wave shape towards the latter part of the waveform for effective peak current mode control. Active clamping provides higher efficiency compared to passive clamping.
The electronic system senses the current of the power converter on the primary side of the transformer, and by comparing this current to a reference current, provides the ability to continuously adjust control of the active clamping circuit, allowing for high efficiency clamping and effective peak current mode control under varying load conditions. By sensing current on the primary side of the transformer, the active clamping circuit is controlled to provide protection of transistors on the primary side of the power converter while maintaining high efficiency active clamping at the output.
The primary side full-bridge rectifier includes primary transistors Q1101, Q2102, Q3103, and Q4104. In this example embodiment, these primary transistors are MOSFETs, however other embodiments may use other types of transistors, such as IGBTs, and the like. The gate of transistor Q1101 is driven by signal PWM1A 111; the gate of transistor Q2102 is driven by signal PWM1B 112; the gate of transistor Q3103 is driven by signal PWM2A 113; and the gate of transistor Q4104 is driven by signal PWM2B 114. The primary side rectifier is powered by Vin 120 and is grounded at GND_P 122. Node 141 is labeled as voltage V1, and node 142 is labeled as voltage V2. The primary side also includes inductor Lr 132.
The secondary side full-bridge rectifier includes primary transistors Q5105, Q6106, Q7107, and Q8108. In this example embodiment, these primary transistors are MOSFETs, however other embodiments may use other types of transistors, such as IGBTs, and the like. The gate of transistor Q5105 is driven by signal PWM3A 115; the gate of transistor Q6106 is driven by signal PWM3B 116; the gate of transistor Q7107 is driven by signal PWM4A 117; and the gate of transistor Q8108 is driven by signal PWM4B 118. The secondary side rectifier produces output voltage Vout 126 across resistive load RL 130 and capacitive load Co 128, and is grounded at GND_S 124. Node 143 is labeled as voltage V3, and node 144 is labeled as voltage V4. The secondary side also includes inductor Lo 138.
The secondary side also includes active clamping circuit 140. In this example embodiment, active clamping circuit 140 includes capacitor C1136 in series with transistor Q9109 across the output of the secondary side full-bridge rectifier. The gate of transistor Q9109 is controlled by signal PWM5A 119 in order to provide active clamping of the output in order to ensure safe operation of the output stage transistors while maintaining high efficiency. By controlling signal PWM5A 119, the circuits and systems described below minimize effects of the active clamping circuit on the output current of the power converter.
Control signals PWM1A 111, PWM1B 112, PWM2A 113, PWM2B 114, PWM3A 115, PWM3B 116, PWM4A 117, PWM4B 118, and PWM5A 119 are produced by pulse width modulators PWM1151, PWM2152, PWM3153, PWM4154, and PWM5155 within control circuit 150.
Pulse width modulator modules PWM1151, PWM2152, PWM3153, and PWM4154 are configured to generate signals controlling the primary transistors 101-108 of the phase-shifted full-bridge power converter 100. Pulse width modulator module PWM1151 is configured to generate signals PWM1A 111 and PWM1B 112. Pulse width modulator module PWM2152 is configured to generate signals PWM2A 113 and PWM2B 114. Pulse width modulator module PWM3153 is configured to generate signals PWM3A 115 and PWM3B 116. Pulse width modulator module PWM4154 is configured to generate signals PWM4A 117 and PWM4B 118. Pulse width modulator module PWM5155 is configured to generate signal PWM5A 119, which controls active clamping circuit 140.
PWM5A 204 is generated by the MCU for the purpose of controlling the ACL MOSFET Q9109. The active clamping MOSFET Q9109 is off between the time intervals T1 211 to T2 212 and between T3 213 and T4 214 when the PWM5A 204 signal is low. The active clamping MOSFET Q9109 is on immediately before T1 211, between the time intervals T2 212 to T3 213, and immediately after T4 214 when the PWM5A 204 signal is high. Larger active clamping duty cycles result in higher RMS currents within the transformer windings.
The voltage across the primary side of transformer T1124 (VT1 206), being an alternating current (AC) signal, is positive high immediately before T1 211 and immediately after T4 214 and negative high between times T2 212 and T3 213. This is due to the action of the four primary MOSFETs Q1-Q4101-104 in order to transfer power from the primary side of transformer T1124 to the secondary side of transformer T1124.
VT1 206 is zero between times T1 211 to T2 212 and between times T3 213 and T4 214, so no power is transferred from the primary side to the secondary side of transformer T1124 during these two intervals of time. VT1 206 is high immediately before T1 211, between times T2 212 to T3 213, and immediately after T4 214 so power is transferred from the primary side to the secondary side of transformer T1124 during these two intervals of time.
During the time intervals when power is transferred from the primary side to the secondary side of transformer T1124 the active clamping MOSFET Q9109 remains on and clamps any voltage spike across the primary side and the secondary side of transformer T1124. This clamping action limits the voltage across the four secondary MOSFETs Q5-Q8105-108, and helps provide the needed protection for the secondary MOSFETs Q5-Q8105-108.
During the power transfer time intervals (immediately before T1 211, between T2 212 to T3 213, and immediately after T4 214) the current through the primary side of transformer T1134 (IT1 202) gradually builds up, indicating power transfer from the primary side to the secondary side of transformer T1124. The current through the primary side of transformer T1134 (IT1 202) drops to zero between times T1 211 to T2 212 and between times T3 213 and T4 214 indicating that no power is transferred to the secondary side of transformer T1124.
In this example, the interval between times T1 211 and T2 212 and between times T3 213 and T4 214 when the active clamping MOSFET Q9109 is off, is 0.3 uS during each cycle of the output of power converter 100.
PWM5A 304 is generated by the MCU for the purpose of controlling the ACL MOSFET Q9109. The active clamping MOSFET Q9109 is off between the time intervals T1 311 to T2 312 and between T3 313 and T4 314 when the PWM5A 304 signal is low. The active clamping MOSFET Q9109 is on immediately before T1 311, between the time intervals T2 312 to T3 313, and immediately after T4 314 when the PWM5A 304 signal is high. Larger active clamping duty cycles result in higher RMS currents within the transformer windings.
In this example, the interval between times T1 311 and T2 312 and between times T3 313 and T4 314 when the active clamping MOSFET Q9109 is off, is 0.5 uS during each cycle of the output of power converter 100, thus the circuit of
By controlling the duty cycle of signal PWM5A 204 and 304, the circuits and systems described below minimize effects of the active clamping circuit on the RMS currents within the transformer windings of power converter 100.
In this example, the primary side full-bridge rectifier 450 includes primary transistors Q1101, Q2102, Q3103, and Q4104. The gate of transistor Q1101 is driven by signal PWM1A 111; the gate of transistor Q2102 is driven by signal PWM1B 112; the gate of transistor Q3103 is driven by signal PWM2A 113; and the gate of transistor Q4104 is driven by signal PWM2B 114. The primary side rectifier is powered by Vin 120 and is grounded at GND_P 122. The primary side also includes inductor Lr 132.
In this example, current sensor 452 is configured to sense the current through the primary side of transformer T1135. Signal conditioning circuitry 460 is configured to generate a transformer current signal 402 based on the current 401 through the primary side of the transformer T1135 within the power converter 100.
In this example embodiment, microcontroller unit 410 is configured to generate a plurality of signals used to control both the primary transistors 101-108 and the active clamping circuit 140 of the phase-shifted full-bridge power converter 100 of
Pulse width modulator modules PWM1431, PWM2432, PWM3433, and PWM4434 are configured to generate signals controlling the primary transistors 101-108 of the phase-shifted full-bridge power converter 100 of
Comparator sub-system 440 includes digital-to-analog converter (DAC) 444, ramp input 442, comparator 446 and filter and digital logic module 448. Comparator sub-system 440 receives transformer current signal 402 based on the current 401 through the primary side of the transformer T1135 within the power converter 100. Comparator 446 compares the transformer current signal 402 to a reference signal 403 generated by DAC 444. Ramp input 442 is configured to provide digital slope compensation to DAC 444.
Comparator 446 generates comparator output signal 404 based on a difference between transformer current signal 402 and reference signal 403. Filter and digital logic module 448 receives comparator output signal 404 from comparator 446 and generates the trip signal 405 based on the comparator output signal 404. The trip signal 405 is provided to the pulse width modulator modules 431-435 and processing circuitry 420. Processing circuitry 420 is configured to control pulse width modulator module PWM5435 to produce signal PWM5A 119 having a pulse width based at least in part on the trip signal 405 in order to control active clamping circuit 140 in a manner to clamp the output voltage of power converter 100 while ensuring safe operation of the output stage transistors, and while minimizing the effects of the active clamping circuit 140 on the output current of power converter 100.
In this example embodiment, microcontroller unit 410 comprises comparator sub-system 440, processing circuitry 420, pulse width modulator modules PWM1431, PWM2432, PWM3433, PWM4434, and PWM5435, and internal storage system 500. Pulse width modulator modules PWM1431, PWM2432, PWM3433, and PWM4434 are configured to generate signals controlling the primary transistors 101-108 of the phase-shifted full-bridge power converter 100 of
Comparator sub-system 440 is configured to generate and provide trip signal 504 to processing circuitry 420 and the pulse width modulator modules 431-435 as described above with respect to
Processing circuitry 420 comprises electronic circuitry configured to direct microcontroller unit 410 to control a power converter 100 having an active clamping circuit 140 as described above. Processing circuitry 420 may comprise microprocessors and other circuitry that retrieves and executes software 510. Examples of processing circuitry 420 include general purpose central processing units, application specific processors, and logic devices, as well as any other type of processing device, combinations, or variations thereof. Processing circuitry 420 can be implemented within a single processing device but can also be distributed across multiple processing devices or sub-systems that cooperate in executing program instructions.
Internal storage system 500 can comprise any non-transitory computer readable storage media capable of storing software 510 that is executable by processing circuitry 420. Internal storage system 500 can also include various data structures 520 which comprise one or more registers, databases, tables, lists, or other data structures. Storage system 500 can include volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information, such as computer readable instructions, data structures, program modules, or other data.
Storage system 500 can be implemented as a single storage device but can also be implemented across multiple storage devices or sub-systems co-located or distributed relative to each other. Storage system 500 can comprise additional elements, such as a controller, capable of communicating with processing circuitry 420. Examples of storage media include random access memory, read only memory, magnetic disks, optical disks, flash memory, virtual memory and non-virtual memory, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and that can be accessed by an instruction execution system, as well as any combination or variation thereof.
Software 510 can be implemented in program instructions and among other functions can, when executed by microcontroller unit 410 in general or processing circuitry 420 in particular, direct microcontroller unit 410, or processing circuitry 420, to operate as described herein to control a power converter 100 having an active clamping circuit 140. Software 510 can include additional processes, programs, or components, such as operating system software, database software, or application software. Software 510 can also comprise firmware or some other form of machine-readable processing instructions executable by elements of processing circuitry 420.
In at least one example implementation, the program instructions include various modules configured to direct processing circuitry 420 to control pulse width modulator modules PWM1431, PWM2432, PWM3433, and PWM4434 to generate signals controlling the primary transistors 101-108 of the phase-shifted full-bridge power converter 100 of
In general, software 510 can, when loaded into processing circuitry 420 and executed, transform processing circuitry 420 overall from a general-purpose computing system into a special-purpose computing system customized to operate as described herein for a microcontroller unit 410 configured to control a power converter 100 including an active clamping circuit 140, among other operations. Encoding software 510 on internal storage system 500 can transform the physical structure of internal storage system 500. The specific transformation of the physical structure can depend on various factors in different implementations of this description. Examples of such factors can include, but are not limited to the technology used to implement the storage media of internal storage system 500 and whether the computer-storage media are characterized as primary or secondary storage.
For example, if the computer-storage media are implemented as semiconductor-based memory, software 510 can transform the physical state of the semiconductor memory when the program is encoded therein. For example, software 510 can transform the state of transistors, capacitors, or other discrete circuit elements constituting the semiconductor memory. A similar transformation can occur with respect to magnetic or optical media. Other transformations of physical media are possible without departing from the scope of the present description, with the foregoing examples provided only to facilitate this discussion.
In this example method, microcontroller unit 410 receives a transformer current signal 402 from a current sensor 452, (operation 600). Comparator sub-system 440 generates a trip signal 405 based on a difference between the transformer current signal 402 and a reference signal 403, (operation 602).
Microcontroller unit 410 then generates a gate input signal PWM5A 119 for the active clamping circuit 140 based at least in part on the trip signal 405, (operation 604).
Immediately before time T0 710, the signal PWM1A 111 is de-asserted, causing transistor Q1101 to be in an off (e.g., cutoff) state, and the signal PWM1B 112 is asserted, causing transistor Q2102 to be in an on (e.g., saturated) state. Similarly, the signal PWM2A 113 is de-asserted, causing transistor Q3103 to be in an off state, and the signal PWM2B 114 is asserted, causing transistor Q4104 to be in the on state. This time immediately before T0 110 may be considered a guardband time when, to prevent current flow through, the inductor Lr 132 and the transformer T1134 are only connected to ground.
Immediately before time T0 710, signal PWM5A 119 is de-asserted, causing transistor Q9109 to be in the off state.
At time T0 710, the signal PWM1A 111 transitions to being asserted, causing transistor Q1101 to transition to the on state, and the signal PWM1B 112 transitions to being de-asserted, causing transistor Q2102 to transition to the off state. The signal PWM2A 113 remains de-asserted, and the signal PWM2B 114 remains asserted.
The signal PWM3A 115 remains asserted, causing transistor Q5105 to be in the on state, and the signal PWM3B 116 transitions to being de-asserted, causing transistor Q6106 to transition to the off state. The signal PWM4A 117 transitions to being de-asserted, causing transistor Q7107 to transition to the off state, and the signal PWM4B 118 remains asserted, causing transistor Q8108 to be in the on state.
The signal PWM5A 119 remains de-asserted, causing transistor Q9109 to be in the off state.
As a result, the voltage between nodes V1141 and V2142 (illustrated as V12 721) rises to or near Vin while the voltage between nodes V3143 and V4144 (illustrated as V34 722) remains at or near zero. Hence, current through inductor Lr 132 (illustrated as iT1 720) begins to rise and change direction. As the voltage V34 722 is still zero between T0 710 and T1 711, it may not be desirable to turn on Q9109 (controlled by PWM5A) to avoid the ACL capacitor 136 energy being discharged to the secondary winding.
At time T1 711, the current iT1 720 has reached its peak, and voltages V12 721 and V34 722 and the output voltage Vout 723 have also reached their peak. The control circuit 150 waits for a selectable delay before transitioning the power converter 100 to the next state at T2 712.
At time T2 712, the signal PWM5A 119 is asserted, causing transistor Q9109 to transition to the on state, thus enabling the active clamping. This active clamping time between times T2 712 and T3 713 may be relatively short, and in some examples, the control circuit 150 specifies an active clamping time of approximately 700 ns in a 100 kHz power converter 100.
At time T3 713, the signal PWM5A 119 is de-asserted, causing transistor Q9109 to transition to the off state, thus ending the active clamping time.
At time T4 714, the signal PWM1A 111 remains asserted, causing transistor Q1101 to remain in the on state, and the signal PWM1B 112 remains de-asserted, causing transistor Q2102 to remain in the off state. The signal PWM2A 113 remains de-asserted, causing transistor Q3103 to remain in the off state, and the signal PWM2B 114 transitions to being de-asserted, causing transistor Q4104 to transition to the off state.
The signal PWM3A 115 remains asserted, causing transistor Q5105 to be in the on state, and the signal PWM3B 116 remains de-asserted, causing transistor Q6106 to be in the off state. The signal PWM4A 117 remains de-asserted, causing transistor Q7107 to be in the off state, and the signal PWM4B 118 remains asserted, causing transistor Q8108 to be in the on state.
The signal PWM5A 119 remains de-asserted, causing transistor Q9109 to be in the off state.
As a result, voltages V12 721 and V34 722 begin to fall to zero.
At time T5 715, the signal PWM1A 111 transitions to being de-asserted, causing transistor Q1101 to transition to the off state, and the signal PWM1B 112 transitions to being asserted, causing transistor Q2102 to transition to the on state. The signal PWM2A 113 transitions from being de-asserted to being asserted between time T4 714 and T5 715, and is asserted at time T5 715, causing transistor Q3103 to be in the on state. The signal PWM2B 114 remains de-asserted, causing transistor Q4104 to be in the off state.
The signal PWM3A 115 transitions from being asserted to being de-asserted at time T5 715 or shortly thereafter, causing transistor Q5105 to be in the off state. The signal PWM3B 116 transitions from being de-asserted to being asserted between time T4 714 and T5 715, and is asserted at time T5 715, causing transistor Q6106 to be in the on state. The signal PWM4A 117 also transitions from being de-asserted to being asserted between time T4 714 and T5 715, and is asserted at time T5 715, causing transistor Q7107 to be in the on state. The signal PWM4B 118 transitions from being asserted to being de-asserted at time T5 715 or shortly thereafter, causing transistor Q8108 to be in the off state.
The signal PWM5A 119 remains de-asserted, causing transistor Q9109 to be in the off state.
As a result, the voltage V12 721 rises to or near negative Vin while the voltage V34 722 remains at or near zero. Hence, current iT1 720 begins to fall and change direction.
At time T6 716, the current iT1 720 has reached its peak, and voltages V12 721 and V34 722 have also reached their peak, albeit in an opposite polarity from the peaks at time T1 711. The output voltage Vout 723 has also reached a peak. The control circuit 150 waits for a selectable delay before transitioning the power converter 100 to the next state at T7 717. This delay may be the same or different from the delay between times T1 711 and T2 712.
At time T7 717, the signal PWM5A 119 is asserted, causing transistor Q9109 to transition to the on state, thus enabling the active clamping. This active clamping time between times T7 717 and T8 718 may be the same or different from the active clamping time between times T2 712 and T3 713.
At time T8 718, the signal PWM5A 119 is de-asserted, causing transistor Q9109 to transition to the off state, thus ending the active clamping time.
At time T9 719, the signal PWM1A 111 remains de-asserted, causing transistor Q1101 to remain in the off state, and the signal PWM1B 112 remains asserted, causing transistor Q2102 to remain in the on state. The signal PWM2A 113 transitions to being de-asserted, causing transistor Q3103 to transition to the off state, and the signal PWM2B 114 remains de-asserted, causing transistor Q4104 to be in the off state.
The signal PWM3A 115 remains de-asserted, causing transistor Q5105 to be in the off state, and the signal PWM3B 116 remains asserted, causing transistor Q6106 to be in the on state. The signal PWM4A 117 remains asserted, causing transistor Q7107 to be in the on state, and the signal PWM4B 118 remains de-asserted, causing transistor Q8108 to be in the off state.
The signal PWM5A 119 remains de-asserted, causing transistor Q9109 to be in the off state.
The cycle repeats, and accordingly, the state and behavior of the power converter 100 at time T10 720 may be substantially similar to the state at time T0 710.
The included descriptions and figures depict specific embodiments to teach those skilled in the art how to make and use the best mode. For the purpose of teaching inventive principles, some conventional aspects have been simplified or omitted. Those skilled in the art will appreciate variations from these embodiments that fall within the scope of the invention. Those skilled in the art will also appreciate that the features described above may be combined in various ways to form multiple embodiments. As a result, the invention is not limited to the specific embodiments described above, but only by the claims and their equivalents.
