Circuit, apparatus and method for capturing a representation of a waveform from a clock-data recovery (CDR) unit

Abstract

A circuit, apparatus and method obtains system margin at the receive circuit using phase shifted data sampling clocks while allowing the CDR to remain synchronized with the incoming data stream in embodiments of the present invention. In a first embodiment of the present invention, logic is provided in a CDR unit of a serial receiving circuit by disengaging or freezing the CDR loop during a waveform capture mode. In a second embodiment of the present invention, an additional clock phase adjuster and sampling stage is used to generate offset clock signals independent of CDR tracking clocks. In a third embodiment of the present invention, edge clocks alone are used for CDR tracking of half rate serial data while data clocks are used for capturing a waveform. In a fourth embodiment of the present invention, a predetermined pattern having a single transition is used for CDR tracking. In a fifth embodiment of the present invention, a predetermined pattern is used for capturing a waveform in a first period of time and data for synchronization is used for CDR tracking during a second period of time. In a sixth embodiment of the present invention, a circuit includes multiple serial links to receive different sets of serial data where the master link is coupled to an active CDR for tracking. Other slave links also receive serial data and can be used for capturing representation of waveforms while CDR tracking information is derived from one master link.

Description

FIELD OF THE INVENTION

[0003] The present invention relates to communication systems, and in particular, serial link systems.

BACKGROUND OF INVENTION

[0004] A serial data system consists of a transmit circuit for transmitting data bits on a serial link to a receive circuit. Most receive circuits include a Clock-Data Recovery (“CDR”) circuit to synchronize the receive sampling clock with the incoming serial data. A CDR actively looks for transitions in the incoming serial data stream and phase aligns sampling clock edges with respect to the incoming data transitions to provide maximum setup-hold timing margins.

[0005] An objective of a receive circuit in a serial link system is to capture the incoming data stream without any errors. In a synchronous system, the incoming data can be broken up into discrete bits with respect to time (see ‘din’ in FIG. 2) with each bit contained within the same period (i.e. bit time). To receive the data in an accurate manner, it is desirable to sample each data bit in the center of each bit's respective bit time. These sample points can be represented as rising and falling edges from a periodic waveform or clock signal (see ‘dClk’ in FIG. 2). Assuming that this data sampling clock has the same (or close to the same) transition or bit time as the data (i.e. frequency), a circuit is needed to time or phase shift the edges of the sampling clocks to the center of the data's bit time since this relationship between data and sampling clock edges is unknown. Hence the need for a CDR unit which recovers the sampling clock from the incoming data transitions to place the rising and falling edges of a clock signal in the middle of a bit time. By placing the edges of a clock signal in the middle of a bit time, the maximum amount of timing margin (or setup/hold margin) is developed for each bit and a CDR is considered ‘phase locked’ to the incoming data.

[0006] At the same time, the receive circuit may also have a circuit to provide a Built-in-Self-Test (“BIST”) as described in the above-referenced patent application. A BIST circuit may sample the serial data in order to obtain representations of incoming signals or waveforms for system margining purposes. The timing requirements, however, of the sampling clock edges for obtaining waveforms by a BIST circuit conflict with the timing requirements to synchronize the clock edges with the incoming serial data.

[0007] To perform a system margining test as described in the related patent application, it may be necessary to phase shift the sampling clock edges with respect to the received data stream. However, as the sampling clock is shifted off the ‘phase locked’ position, the CDR loop will not get the proper phase information from the data samples leading to erroneous tracking information for the receive circuit.

[0008] Therefore, it is desirable to provide a circuit, an apparatus and a method that can synchronize the sampling clock edges with the incoming serial data while at the same time capture representations of waveforms of the incoming serial data. In particular, it is desirable to provide methods with different circuits and setups to allow a CDR to track relative to the incoming data stream; while at the same time allow system margining to take place in the receive circuit

SUMMARY OF INVENTION

[0009] Embodiments of the present invention enable obtaining system margin at the receive circuit using phase shifted data sampling clock signals while allowing the CDR to remain synchronized with the incoming data stream. In a first embodiment of the present invention, logic is provided in a CDR unit of a serial receiving circuit by disengaging or freezing the CDR loop during a waveform capture mode. In a second embodiment of the present invention, an additional clock phase adjuster and sampling stage is used to generate offset clock signals independent of CDR sampling clocks. In a third embodiment of the present invention, edge clocks alone are used for CDR tracking of half rate serial data while data clocks are used for capturing a waveform. In a fourth embodiment of the present invention, a predetermined pattern having a single transition is used for CDR tracking. In a fifth embodiment of the present invention, a predetermined pattern is used for capturing a waveform in a first period of time and data for synchronization is used for CDR tracking during a second period of time. In a sixth embodiment of the present invention, a circuit includes multiple serial links to receive different sets of serial data where the master link is coupled to an active CDR for tracking. Other slave links also receive serial data and can be used for capturing representation of waveforms while CDR tracking information is derived from one master link.

[0010] In a first embodiment of the present invention, logic is provided in a phase adjustment circuit of the CDR unit of a serial receiving circuit for disengaging or freezing the CDR loop during system margining. In this embodiment, the loop will not track the incoming data transitions allowing system margining to occur by phase shifting the data clock signals in response to a Hold signal. Alternatively, the incoming data stream could be offset while the data clocks are held fixed.

[0011] In a second embodiment of the present invention, an additional phase adjuster and sampling stage is used to generate offset clock signals independent of CDR tracking clocks. In this embodiment of the present invention, the main CDR loop remains unchanged, so the loop continues to track the incoming serial data while system margining clocks that are phase shifted off the main CDR tracking clocks are controlled by the additional phase adjuster and data sampling stage.

[0012] In a third embodiment of the present invention, edge clocks alone are used for CDR tracking of half rate serial data while data clocks are used for capturing system margining information. In this embodiment of the present invention, an additional waveform select logic stage is provided after a sampler stage to switch from the normal full rate mode of operation for CDR tracking. The CDR is still tracking the half-rate data by using only the edge clock while the data clock can be shifted for system margining purposes.

[0013] In a fourth embodiment of the present invention, a predetermined sequence of serial data having a single transition is used for CDR tracking. During system margining, a specific periodic pattern is often transmitted in order to observe the system response to a periodic stimulus. The predetermined sequence having one transition is substituted into the CDR phase detect path in place of the incoming periodic pattern to phase track during this mode of operation. Knowing that the incoming pattern is periodic makes this embodiment possible because an apparatus can maintain CDR phase lock to the single transition within the pattern while system margining occurs for the entire data pattern.

[0014] In a fifth embodiment of the present invention, a predetermined data pattern is used for capturing a margining waveform in a first period of time and data for synchronization is used for CDR tracking during a second period of time. This embodiment simply switches between tracking and margining modes for different parts of the pattern.

[0015] In a sixth embodiment of the present invention, a circuit may include multiple serial links to receive different sets of serial data where the master link is coupled to an active CDR for tracking. Other slave links also receive serial data and can be used for capturing representations of waveforms while CDR tracking information is derived from the first master link. In this embodiment, an apparatus comprises a ‘master’ transmit circuit that is coupled to a ‘master’ receive circuit and transmits serial data. The ‘master’ receive circuit generates the phase adjustment signal in response to the serial data that performs the active CDR tracking. A ‘slave’ transmit circuit is coupled to a respective receive ‘slave’ circuit across a serial link and transmits serial data. The ‘slave’ receive circuit is coupled to the ‘master’ receive circuit in a way such that the ‘slave’ receive circuit obtains CDR tracking information from the ‘master’ receive circuit while independently obtaining a representation of a waveform in response to the receive circuit's independent clock signal.

[0016] These embodiments of the present invention, as well as other aspects and advantages, are described in more detail in conjunction with the figures, the detailed description, and the claims that follow.

BRIEF DESCRIPTION OF THE DRAWINGS

[0017] FIG. 1 is a block diagram illustrating a communication system in accordance with an embodiment of the present invention.

[0018] FIG. 2 is a diagram illustrating signals that may be used in accordance with an embodiment of the present invention.

[0019] FIG. 3 is a block diagram illustrating a CDR loop with the Hold signal in accordance with an embodiment of the present invention.

[0020] FIG. 4 is a block diagram illustrating an additional sampler and phase adjuster stage in accordance with an embodiment of the present invention.

[0021] FIG. 5 is a block diagram illustrating the use of edge clock signals for CDR tracking and data clocks for obtaining a representation of waveform in accordance with an embodiment of the present invention.

[0022] FIG. 6 is a diagram illustrating half-rate serial data and edge sampling clock signals in accordance with an embodiment of the present invention.

[0023] FIG. 7 is a diagram illustrating a use of a waveform pattern in different periods of time to collect CDR tracking information and waveform representations in accordance with an embodiment of the present invention.

[0024] FIG. 8 is a block diagram illustrating multiple serial links in a ‘master’/‘slave’ CDR tracking configuration in accordance with an embodiment of the present invention.

[0025] FIG. 9 is a flow chart of a method in accordance with an embodiment of the present invention.

DETAILED DESCRIPTION

[0026] FIG. 1 illustrates a communication system 10 according to an embodiment of the present invention. In an embodiment of the present invention, communication system 10 includes a transmit circuit 20 and a receive circuit 30 coupled by medium 11. In an embodiment of the present invention, transmit circuit 20, and in particular serializer circuit 21, generates serial data 25 on medium 11 to receive circuit 30. Transmit circuit 20 also includes waveform generation logic 22 for generating waveform data (a.k.a. “escope” data) or predetermined waveforms as described in United States patent application entitled “Method and Apparatus for Evaluating and Calibrating a Signal System” cited above and incorporated by reference herein in an embodiment of the present invention.

[0027] Receive circuit 30 includes a Clock Data Recovery unit (“CDR”) 35 that actively looks for transitions in the incoming data stream and phase aligns the sampling clock edges with respect to the incoming data to provide optimal setup/hold margin times. CDR 35 includes Data Collection circuit 36 having data/edge samplers 34 and phase detector 33, as well as Clock Phase Adjustment circuit 32. CDR 35 samples the serial data with data/edge samplers 34. Phase detector 33 then uses the sampled data and edge information to provide early and late phase information about the incoming data relative to the sampling clock signals. Clock Phase Adjustment circuit 32 generates the sampling clock signals that complete the CDR loop in response to phase information from phase detector 33. Embodiments of present invention, including embodiments of CDR 35, are illustrated in FIGS. 3-7 and described below.

[0028] In an embodiment of the present invention, medium 11 is a wire or set of wires for transporting signals, such as waveforms. In an embodiment of the present invention, medium 11 is a bidirectional data bus that may carry data information, control information or both. In an alternate embodiment of the present invention, medium 11 is a unidirectional bus. In still a further embodiment of the present invention, medium 11 includes a wireless or photonics connection.

[0029] FIG. 2 illustrates serial data and sampling clock signals 50 in accordance with an embodiment of the present invention. Serial data ‘din’ represents the alternating transitions of serial data that may be transported on medium 11 illustrated in FIG. 1. Data cell 51 represents a period of time in serial data ‘din’ in which a data value may have a high value 52 or low value 53. Edge clock ‘eClk’ is used to determine the boundary of data cell 51 or the transition from high to low or from low to high of both the rising (even) and falling (odd) edges. For example, the rising edge e1 and falling edge e2 of edge clock signal ‘eClk’ are used to define data cell 51. The data clock signal ‘dClk’ is 90° offset in phase from edge clock ‘eClk’ and is used to determine the value of a data cell. For example, the data clock ‘dClk’ rising edge d1 (even) and falling edge d2 (odd) are used to determine the time at which the value of serial data ‘din’ is sampled. In particular, the time at which to sample serial data ‘din’ in order to determine the value of data cell 51. Data cell 51 may have a binary one value corresponding to high value 52 or a binary zero value corresponding to low value 53. Likewise, data clock ‘dClk’ falling edge d2 is used to determine the sampling time associated with data cell 54.

[0030] A CDR is typically responsible for generating edge clock ‘eClk’ and data clocks ‘dClk’ (both rising and falling transitions used to sample even/odd data) in order to obtain data of serial data ‘din’. A CDR is responsible for adjusting or phase shifting edge clock ‘eClk’ and data clock ‘dClk’ in order to align transitions of edge clock ‘eClk’ with the boundaries of data cells within serial data ‘din’ and align transitions of data clock ‘dClk’ with the center of the corresponding data cells. These adjusted clock edges are used to time the sampling of serial data ‘din’. This synchronization of the data and edge clocks to the incoming serial data ‘din’ is often carried out by a type of Delay Lock Loop (“DLL”) called the CDR loop. However, the clock signals used for synchronization do not allow for sampling a waveform that may be used for evaluating system performance or diagnostics. In order to evaluate system performance, it is desirable to have the ability to sweep sampling clock relative to the received data pattern. However, with the CDR loop still engaged, the loop will attempt to compensate for the data clock ‘dClk’ disturbance off its ideal 900 phase shifted position and give false phase alignment information out of the phase detector to the sampling clocks relative to the incoming data. This is a problem being addressed by embodiments of the present invention.

[0031] An embodiment of a CDR 35 is shown as CDR 90 in FIG. 3. CDR 90 includes data/edge samplers 100 for receiving serial data, ‘din’, responsive to data and edge sampling clock signals ‘dClk’ and ‘eClk’, on lines 131 and 130, respectively. Receive data 150 is collected and sent to an end user or other circuit in an embodiment of the present invention. Collected data information and edge information is then provided to a phase detector 102, on lines 121 and 120, respectively. Phase detector 102 measures the phase difference between the sampling clock signals and incoming serial data, and outputs phase information on line 124. Phase control logic 103 then decodes the phase difference information and provides phase adjust signals, in particular a data phase adjust signal and an edge phase adjust signal on lines 125 and 126, respectively. In an embodiment of the present invention, receive circuit 30 includes a quadrature clock that is locked to a reference (typically done with a PLL) in order to provide a PLL clock signal and quadrature PLL clock signal. A data clock phase adjuster 107 shifts the phase of data sampling clock, ‘dClk’, in response to the data phase adjust signal and a PLL clock signal on line 138. Likewise, edge clock phase adjuster 108 shifts the phase of the edge clock, ‘eClk’, in response to the edge phase adjust signal and a quadrature PLL clock signal on line 139. Data and edge sampling clock signals, ‘dClk’ and ‘eClk’, for both data and edge then are fed back to data/edge samplers 100 to complete a CDR 90 loop.

[0032] FIG. 3 also illustrates a CDR 90 that both synchronizes the sampling clock signals to the serial data ‘din’ and can also capture a representation of a waveform in the serial data ‘din’ by asserting the ‘Hold’ signal on line 140 in an embodiment of the present invention. Generally, asserting a ‘Hold’ signal to phase control logic 103 during a waveform capture mode disengages the CDR loop and enables an asserted ‘Offset_En’ signal on line 150 to allow the phase sweep of the data clock signal ‘dClk’ to sample the serial data ‘din’ at different points in time. Phase control logic 103 ignores the phase alignment information signals on line 124 from phase detector 102 that are based on offset phase shifted data clock signal ‘dClk’ into data/edge samplers 100.

[0033] Serial data ‘din’ is provided to data/edge samplers 100 as illustrated in FIG. 3. In an embodiment of the present invention, edge samples or values are obtained from an edge sampling circuit (i.e. data/edge samplers 100) in response to the rising and falling edges of edge clock signal ‘eClk’ on line 130 illustrated in FIG. 3. Likewise, data samples or values of a data cell are obtained from a data sampling circuit (i.e. data/edge samplers 100) in response to the rising and falling edges of data clock signal ‘dClk’ on line 131 illustrated in FIG. 3. Edge clock signal ‘eClk’ and data clock signal ‘dClk’ are input to data/edge samplers 100 from clock phase adjuster 108 and 107, respectively. Data information and edge information are transferred to phase detector 102 via lines 121 and 120, respectively. Phase detector 102 determines, based on a plurality of data and edge values, whether the edge clock signal is early or late and should be shifted or aligned up or down with respect to serial data ‘din’; for example, whether edge clock e1 should be shifted left or right to align with the beginning of data cell 51 illustrated in FIG. 2. If the transitions of the captured serial data indicate an early transition, an up signal is generated on line 124. If the transitions indicate a late transition, a down signal is generated on line 124.

[0034] Phase control logic 103 generates control signals for capturing a representation of a waveform from serial data ‘din’, and in particular sweeping data clock ‘dclk’ across a period of a waveform. Phase control logic ignores the phase information signal on line 124 in response to an assertion of a ‘Hold’ signal on line 140 and ‘Offset_En’ signal on line 150 provides control of ‘dClk’ offset to an external source.

[0035] The ‘Hold’ CDR embodiment described above provides several advantages over the other embodiments provide herein. First, the ‘Hold’ CDR embodiment requires less additional hardware compared to the other embodiments. Phase control logic 103 includes the necessary logic to respond to an assertion of a ‘Hold’ and ‘Offset_En’ signal, but there is no additional data path for the waveform data. Nevertheless, timing errors may be introduced during a capturing of a waveform because a CDR loop is disengaged and cannot track and eliminate errors due to variations in temperature and voltage that can skew clock edges with respect to serial data.

[0036] The components illustrated in FIG. 4 are similar to the components illustrated in FIG. 3. However, FIG. 4 illustrates an additional sampler and phase adjuster or waveform path 444 for providing representations of waveforms and CDR path 455 for synchronizing incoming serial data.

[0037] Serial data ‘din’ is input to data/edge samplers 400. Data clock signal dClk and edge clock signal eClk are input to data/edge samplers 400 on lines 431 and 430, respectively. Data information and edge information is passed to phase detector 402 on lines 421 and 420, respectively.

[0038] Phase information is generated on line 424 to phase control logic 403 and offset phase control logic 404. Phase control logic 403 is coupled to phase adjusters 407 and 408 via lines 425 and 426. Edge clock signal ‘eClk’ is output on line 430 from edge phase adjuster 408; while, data clock signal ‘dClk’ is output from data phase adjuster 407. A PLL clock signal is provided to phase adjuster 407 on line 438. A quadrature PLL clock signal is provided to phase adjuster 408 on line 439.

[0039] An independent waveform data path 444 is used to obtain a representation of a waveform by the offsetting clock signals generated by offset phase control logic 404. Serial data ‘din’ is input to data/edge samplers 410. Offset data clock signal ‘dClk’ is input to data/edge samplers 410 on line 432. Offset data clock phase adjuster 409 generates offset data clock signal ‘dClk’ in response to an offset data adjust signal on line 425 and a PLL clock signal on line 470. Waveform information that would be used for system margining purposes is output as receive data 450.

[0040] Offset data adjust signal on line 425 is enabled by ‘Offset In’ signal asserted on line 441. Offset phase control logic 404 functions similar to phase control logic 103 described in the previous embodiment. But in this embodiment, the offset control logic will use tracking information from the CDR loop path before injecting offset into waveform path 444.

[0041] The additional waveform and CDR path embodiment described above provides several advantages over the other embodiments provided herein. First, a CDR path is independent of a waveform data path so a CDR loop can continue to track incoming serial data ‘din’ as waveform data clock, ‘dClk’; sweeps a period of a waveform. However, this embodiment requires additional hardware stages to implement: data/edge samplers 410, offset data clock phase adjuster 409, and offset phase control logic 404.

[0042] FIG. 5 illustrates using edge clock signal ‘eClk’ for CDR tracking while using data clock signal ‘dClk’ for obtaining a representation of a waveform in an embodiment of the present invention. Edge clock signal ‘eClk’ is used in tracking CDR loop 580 and requires receiving ‘din’ at half the typical rate in an embodiment of the present invention. In a waveform capture mode, information from the data clock signals is ignored because data clock signals ‘dClk’ are offset from a bit sync position and are used for sweeping across a waveform. Edge clocks are used to obtain psuedo (half-rate) data information for CDR tracking.

[0043] FIG. 6 illustrates a half rate serial data ‘din’ and the use of full-rate edge clocks. In particular, even edge clock signals ‘eclke’ are used for obtaining edge information and odd edge clock signals ‘eclko’ are used for obtaining psuedo (half-rate) data information.

[0044] Returning to FIG. 5, half-rate ‘din’ is input to data/edge samplers 500. Edge clock signal ‘eClk’ is also input on line 530. Likewise, data clock signal ‘dClk’ is input on line 531. Edge information is output on line 520 and data information is output on line 521.

[0045] CDR data and edge information feeds a waveform select logic 501 that is coupled to data/edge samplers 500. Waveform select logic 503 passes edge information responsive to an assertion of a waveform enable signal on line 560 and ignores data information. Phase detector 502 is coupled to waveform select logic 501 via line 520 and operates similarly to phase detector 402 described above. Phase control logic 503 is coupled to phase detector 502 via line 524 and receives phase information. Phase control logic 503 operates similarly to phase control logic 103 illustrated in FIG. 3. Phase control logic 503 is coupled to data and edge phase adjusters 507 and 508, respectively.

[0046] Edge clock phase adjuster 508 is coupled to phase control logic 503 via line 526. Data clock phase adjuster 507 is coupled to phase control logic 503 via line 525. Edge clock phase adjuster 508 outputs edge clock signal ‘eClk’ on lines 530 responsive to an edge phase adjust signal on line 526 and a quadrature PLL clock signal on line 539. Likewise, data clock phase adjuster 507 outputs data clock signal ‘dClk’ on line 531 responsive to a data phase adjust signal on line 525 and a PLL clock signal on line 538.

[0047] In an embodiment of the present invention, a predetermined bit pattern is transmitted repeatedly during a waveform capture mode. For example, an N-bit pattern is transmitted in serial data ‘din’ to data/edge samplers 500 shown in FIG. 5. By selecting a predetermined bit pattern with at least a single transition, the CDR loop locks to the one transition within the pattern when capturing a representation of a waveform during a waveform capture mode. Waveform select logic 503 selects a predetermined N-bit pattern every M number of cycles for CDR tracking in an embodiment of the present invention. Edge information obtained by using edge clock signal ‘eClk’ is still used for CDR tracking during a waveform capture mode. During the other non-used cycles of operation, a no transition data pattern would be used which essentially discontinues phase adjustment signal from phase detector 502. Since the data information is not used for CDR tracking with the assertion of waveform enable signal on line 560, the data receive path is free to collect ‘escope’ waveform data by sweeping the data clock signal ‘dClk’ across the repeating N-bit data pattern.

[0048] The use of a predetermined bit pattern described above offers several advantages over other embodiments of the present invention. First, minimal hardware change is needed when adding waveform select logic 501. Second, since it is known that a predetermined data pattern is transmitted during a waveform capture mode, the CDR can track this pattern by looking for only one transition. However, this embodiment of the present invention updates sampling clock signals at a slower rate compared to other embodiments of the present invention. Phase detect transition updates every N-bits instead of every real transition in normal modes of operation.

[0049] FIG. 7 illustrates the use of a predetermined waveform bit pattern to perform waveform data sweeps at a first period of time and then CDR data tracking for synchronization at a second period of time according to an embodiment of the present invention. In this embodiment, a switch is provided in waveform select logic 503 of FIG. 5. The switch toggles between CDR tracking and obtaining a representation of a waveform in response to a waveform enable signal on line 560. Serial data ‘din’ includes N-bits of CDR data during a first period of time followed by N-bits of waveform data during a second period of time as illustrated in FIG. 7. There is an invalid region between CDR tracking data and waveform data. Obtaining a representation of a waveform and CDR tracking would be alternated in a continuous manner.

[0050] FIG. 8 illustrates a multiple links embodiment of the present invention. Circuit 81 is coupled by multiple links to circuit 82 on a semiconductor substrate 80 in an embodiment of the present invention. In particular, transmit circuits 88, 89, and 90 are coupled to receive circuits 91, 92 and 93 via links or medium 83, 84 and 85, respectfully. Transmit circuit 88, link 83 and receive circuit 91 serve as a ‘master’ link that performs CDR tracking. Receive circuit 91 generates the synchronous clocking signal to receive circuits 92 and 93 via interconnect 87. Accordingly, slave receive circuits 92 and 93 can obtain representations of waveforms by sweeping the clock signal obtained from receive circuit 91 across a period of a received signal.

[0051] The master/slave embodiment offers the advantage of a relatively simple implementation compared to the other embodiments. However, variations across semiconductor substrate 80 cause differences in optimum sampling for the different links.

[0052] FIG. 9 illustrates a method 900 according to an embodiment of the present invention. In alternate embodiments of the present invention, steps illustrated in FIG. 9 are carried out by hardware, software or a combination thereof. In alternate embodiments, the steps illustrated in FIG. 9 are carried out by the components illustrated in FIGS. 3-8. As one of ordinary skill in the art would appreciate, other steps that are not shown may be included in various embodiments of the present invention.

[0053] Method 900 begins at step 901 where serial data is received. Serial data is then sampled as illustrated by step 902. In an embodiment of the present invention, data/edge samplers 100, as illustrated in FIG. 3, may sample serial data. A sampling clock signal is then adjusted for sampling the incoming serial data in step 903. Steps 902 and 903 are repeated in order to synchronize or phase lock to the incoming serial data. In an embodiment of the present invention, an edge clock signal is adjusted and used for sampling serial data at half rate. In alternate embodiments, other clock signals are used for synchronization. A determination is made whether to capture a representation of a waveform of the incoming serial. If a representation of a waveform does not need to be captured, method 900 exits; otherwise an offset signal is adjusted in response to the serial data as illustrated by step 905. Step 906 then illustrates sampling serial data to obtain a representation of a waveform in response to the phase adjusted clock signal. Steps 905 and 906 are then repeated until a representation of a waveform is obtained.

[0054] The foregoing description of the preferred embodiments of the present invention has been provided for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations will be apparent to practitioners skilled in the art. The embodiments were chosen and described in order to best explain the principles of the invention and its practical applications, thereby enabling others skilled in the art to understand the invention for various embodiments and with the various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the following claims and their equivalents.

Claims

1) A receiving circuit, comprising: a sampler to receive serial data responsive to a data clock signal and an edge clock signal; and, a clock circuit, coupled to the sampler, to generate the data clock signal and the edge clock signal responsive to the serial data, wherein the clock circuit includes logic to increment the data clock in order to capture a sampled signal of the serial data.

2) The receiving circuit of claim 1, wherein the clock circuit further comprises: a phase detector to generate phase information responsive to the serial data; and a phase control logic, coupled to the phase detector, to generate a data adjust signal and an edge adjust signal.

3) The receiving circuit of claim 1, wherein the receiving circuit is included in a Clock Data Recovery (“CDR”) unit.

4) The receiving circuit of claim 2, wherein the clock circuit further comprises: a first phase adjuster, coupled to the phase control logic, to generate the data clock signal responsive to the data adjust signal; and, a second phase adjuster, coupled to the phase control logic, to generate the edge clock signal responsive to the edge adjust signal.

5) A receiving circuit, comprising: a first sampler to receive serial data responsive to a data clock signal and an edge clock signal; a second sampler to receive the serial data responsive to an offset data clock signal; and, a clock circuit, coupled to the first and second sampler, to generate: 1) the data clock signal, 2) the edge clock signal, and 3) the offset data clock signal responsive to the serial data.

6) The receiving circuit of claim 5, wherein the receiving circuit is included in a Clock Data Recovery (“CDR”) unit.

7) The receiving circuit of claim 5, wherein the clock circuit further comprises: a phase detector to generate phase information responsive to the serial data; a phase control logic, coupled to the phase detector, to generate a data adjust signal and an edge adjust signal; and, an offset phase control logic, coupled to the phase detector and the second sampler, to increment the offset data clock signal.

8) The receiving circuit of claim 7, wherein the clock circuit further comprises: a first phase adjuster, coupled to the phase control logic, to generate the data clock signal responsive to the data adjust signal; and, a second phase adjuster, coupled to the phase control logic, to generate the edge clock signal responsive to the edge adjust signal.

9) A receiving circuit, comprising: a sampler to receive a half-rate serial data responsive to an edge clock signal; and, a clock circuit, coupled to the sampler, to generate the edge clock signal and a data clock signal responsive to the serial data, wherein the clock circuit includes logic to increment the data clock signal in order to capture a sampled signal of the serial data.

10) The receiving circuit of claim 9, wherein the receiving circuit is included in a Clock Data Recovery (“CDR”) unit.

11) The receiving circuit of claim 10, wherein the clock circuit further comprises: a waveform select logic to pass the serial data responsive to an enable signal; a phase detector, coupled to the waveform select logic, to generate phase information responsive to the serial data; and, a phase control circuit, coupled to the phase detector, to generate a data adjust signal and an edge adjust signal responsive to the phase information.

12) The receiving circuit of claim 11, wherein the clock circuit further comprises: a first phase adjuster, coupled to the phase control circuit, to generate the data clock signal responsive to the data adjust signal; and, a second phase adjuster, coupled to the phase control circuit, to generate the edge clock signal responsive to the edge adjust signal.

13) A receiving circuit, comprising: a first sampler to receive serial data responsive to a data clock signal and edge clock signal, wherein the serial data includes a repeating pattern having a single transition in a predetermined bit pattern; and, a clock circuit, coupled to the first sampler, to generate the data clock signal and the edge clock signal responsive to the serial data and the predetermined bit pattern.

14) The receiving circuit of claim 13, wherein the receiving circuit is included in a Clock Data Recovery (“CDR”) unit.

15) The receiving circuit of claim 13, wherein the clock circuit further comprises: a waveform select logic to pass the predetermined bit pattern responsive to an enable signal; a phase detector, coupled to the waveform select logic, to generate phase information responsive to the serial data; and, a phase control logic, coupled to the phase detector, to generate a data adjust signal and an edge adjust signal responsive to the phase information.

16) The receiving circuit of claim 15, wherein the clock circuit further comprises: a first phase adjuster, coupled to the phase control logic, to generate the data clock signal responsive to the data adjust signal; and, a second phase adjuster, coupled to the phase control logic, to generate the edge clock signal responsive to the edge adjust signal.

17) The receiving circuit of claim 13, wherein the repeating pattern includes an N-bit pattern having a single transition and the predetermined pattern repeats every M cycles.

18) A receiving circuit, comprising: a first sampler to receive serial data responsive to a data clock signal and an edge clock signal, wherein the serial data includes a repeating pattern for obtaining a representation of a waveform during a first period of time and data for synchronization during a second period of time; and, a clock circuit, coupled to the first sampler, to generate the data clock signal and the edge clock signal responsive to the serial data.

19) The receiving circuit of claim 18, wherein the receiving circuit is included in a Clock Data Recovery (“CDR”) unit.

20) The receiving circuit of claim 19, wherein the clock circuit further comprises: a waveform select logic to pass the data responsive to an enable signal; a phase detector, coupled to the waveform select logic, to generate phase information responsive to the serial data; and, a phase control logic, coupled to the phase detector, to generate a data adjust signal and an edge adjust signal responsive to the phase information.

21) The receiving circuit of claim 19, wherein the clock circuit further comprises: a first phase adjuster, coupled to the phase control logic, to generate the data clock signal responsive to the data adjust signal; and, a second phase adjuster, coupled to the phase control logic, to generate the edge clock signal responsive to the edge adjust signal.

22) An apparatus, comprising: a first transmit circuit to transmit serial data, including CDR data; a first receive circuit, coupled to the transmit circuit, to generate a clock signal responsive to the CDR data; a second transmit circuit to transmitting serial data, including a waveform; and, a second receive circuit, coupled to the second transmit circuit and the first receive circuit, to obtain a representation of the waveform in response to the clock signal.

23) An apparatus, comprising: a transmit circuit to generate serial data; a receiving circuit, coupled to the transmit circuit, including: a sampler to receive serial data responsive to a data clock signal and an edge clock signal; a phase detector, coupled to the sampler, to generate phase information responsive to the serial data; and, a clock circuit, coupled to the phase detector, to generate the data clock signal and the edge clock signal responsive to the phase information, wherein the clock circuit includes logic for incrementing the data clock signal in order to capture a representation of a waveform in the serial data.

24) A method, comprising the steps of: receiving serial data; synchronizing the serial data; and, sampling the serial data to obtain a representation of a waveform.

25) The method of claim 24, wherein the sampling step includes: incrementing a phase of a data clock signal used for sampling during the period of the waveform; and, the synchronizing step includes adjusting an edge clock signal responsive to the serial data.

26) The method of claim 24, wherein the synchronizing step includes: sampling the serial data; adjusting the clock signal responsive to the serial data; and, adjusting the clock signal to an offset signal responsive to the serial data.

27) The method of claim 24, wherein the serial data is received at half rate and the synchronizing step includes sampling the serial data with an edge clock signal.

28) The method of claim 24, wherein the serial data includes a predetermined bit pattern having a single transition and the synchronizing step includes sampling the serial data during the predetermined pattern with an edge clock signal.

29) The method of claim 24, wherein the serial data includes a predetermined bit pattern during a first period of time and a bit pattern for synchronizing during a second period of time and the synchronizing step includes sampling the serial data during the first period to obtain a representation of a waveform and sampling the serial data during the second period of time with an edge clock signal and a data clock signal.

30) A method, comprising the steps of: receiving serial data at a first input; synchronizing the serial data in order to obtain an edge clock and a data clock; and, sampling the serial data at a second input to obtain a representation of a waveform responsive to the edge clock.