The present invention relates to a circuit arrangement, comprising
The present invention further relates to a corresponding method for controlling and/or for preventing injection current according to the preamble of claim 6.
Transistor means, such as analog switches, mu[ltiple]x[ers] and/or demu[ltiple]x[ers], are used in a variety of applications, such as in A[nalog]/D[igital] converters, in bus interfaces (as used in the telecom industry), in data acquisition systems, in level shifters, in personal computers, etc.
Conventionally, the operating voltage on I[nput]/O[utput] terminals, in particular of analog data, of the transistor means is limited to rail values wherein these rail values can vary from ground level gnd to supply voltage Vcc. However, in many applications, like automotive applications, signals with an amplitude lower than ground level gnd or higher than supply voltage Vcc frequently occur on terminals of the transistor means during disabled state or disabled mode. Such occurrence can be due to transient behavior of the circuit arrangement, to different power supplies of different parts of this circuit arrangement or to any unwanted voltage spikes etc.
The net result of this behavior is the current being sourced or sinked from the transistor means terminal being connected to this faulty line, i.e. being connected to the conductive channel provided with at least one overvoltage signal or with at least one undervoltage signal.
For analog operation, it is desirable to have minimal disturbance on the terminal of the transistor means which is not connected to the faulty line. However, in conventional analog designs, this overvoltage signal or undervoltage signal or this injection of undesired current can leak to the other side of the transistor means via two mechanisms:
Consequently, signal lines or conductive channels are restricted to the power supply Vcc of the circuit arrangement, in particular of the analog switch or of the analog multiplexer and/or of the analog demultiplexer. Another way of handling such phenomena is that a system in which the circuit arrangement is used should have a power supply range equal to the voltage range of the analog signal and/or of the digital signal to be transmitted.
This causes serious hindrance in those applications where the available power supply voltage is less than the peak value of the analog signal and/or of the digital signal. In such cases, a conventional analog switch or a conventional analog multiplexer or a conventional analog demultiplexer requires a supply voltage Vcc higher than the supply voltage of subsystems to handle high voltage analog signals.
In the following, the basic introduction for the design of the transistor means, namely of a complementary metal-oxide semiconductor (CMOS), in particular of an analog switch or of an analog multiplexer or of an analog demultiplexer, is discussed.
In
In this scenario, the voltages on the conductive channel comprising an input line 12 and an output line 14 are in the voltage range from zero (=ground level gnd) to supply voltage Vcc.
Analog MOS switches, in particular analog CMOS switches, are used to transmit analog or digital signals across the input line 12 of the CMOS switch 20 and across the output line 14 of the CMOS switch 20 with minimal distortion, when enabled. An ideal switch acts as an open switch in the disabled state and as a short switch in the enabled state. However, in conventional MOS transistors, in particular in conventional CMOS switches, several problems occur.
An analog transistor means, in particular an analog MOS transistor, such as an analog CMOS switch, blocks signals in the disabled state of the transistor means and transmits signals in the enabled state of the transistor means. However, the transistor means can block and transmit only signals in the power supply range, i.e. in the voltage range between zero (=ground level gnd) and supply voltage Vcc.
As explained above, due to various disturbances in a system, the conductive channels, in particular the switch lines, are subject to unpredictable currents and/or to unpredictable overvoltages and/or to unpredictable undervoltages, in particular in the disabled state operation of the transistor means.
For normal operation of the overall system, the transistor means must block these unwanted signals so as to have minimal disturbance in the overall system. Otherwise, these disturbances can cause an undesired behavior in the system due to unwanted leakages between conductive channels, in particular between the switch lines.
In this context, there are mainly two mechanisms for this undesired behavior:
These two mechanisms can cause problems for overvoltage signals, i.e. for signals higher than the supply voltage Vcc of the circuit arrangement. The same mechanisms hold for undervoltage signals, i.e. for signals lower than ground level gnd as well:
In
In the disabled state operation of the switch, the PMOS is disabled by providing at least one signal equal to the supply voltage Vcc on the gate MPg of the PMOS. So, if there is an unwanted current at the drain of the PMOS or at the source of the PMOS, the voltage on the drain of the PMOS or on the source of the PMOS tends to rise above the supply voltage Vcc. This causes a current path CP from the drain side to the source side or vice versa due to the PMOS being partially turned-on being or fully turned-on.
The CMOS effect, i.e.
In
Circuits for preventing the parasitic bipolar effect in analog switches or in analog multiplexers or in analog demultiplexers are respectively described
The circuits described in these prior art documents only take care of the parasitic bipolar effect; the MOS effect is not dealt with in these prior art documents. Therefore, these analog switches and multiplexers/demultiplexers can work only if it is ensured that the MOS will not become active, which is possible only when a very effective sink is used, for example when low threshold diodes are used, which is a very costly process, or when the size of the additional circuitry is enormously increased.
Another solution can be to use T-switch construction to block excessive currents. However, the use of a T-switch like construction leads to the disadvantages that
With respect to the MOS effect, prior art document GB 2 319 128 A discloses a CMOS transmission gate multiplexer with improved off-isolation; a transmission cell for transmitting a signal from an input to an output in response to a control signal is provided.
Moreover, in prior art document U.S. Pat. No. 6,567,024 B1 an analog switch is disclosed comprising means for restraining injection current. This conventional analog switch comprises a pair of transfer gates with a pair of transistors whose conduction is enabled and disabled by control signals. The back gate, the source and the drain of one of these transistors are coupled to input and output ends.
However, the parasitic bipolar effect is dealt with neither in prior art document GB 2 319 128 A nor in prior art document U.S. Pat. No. 6,567,024 B1.
Starting from the disadvantages and shortcomings as described above and taking the prior art as discussed into account, an object of the present invention is to further develop a circuit arrangement of the kind as described in the technical field as well as a method of the kind as described in the technical field in such way that minimal disturbance due to unwanted current signals and/or due to unwanted voltage signals on the conductive channel is ensured, in particular that the MOS effect as well as the bipolar effect are prevented in the circuit arrangement; such unwanted signals can be
The object of the present invention is achieved by a circuit arrangement comprising the features of claim 1 as well as by a method comprising the features of claim 6. Advantageous embodiments and expedient improvements of the present invention are disclosed in the respective dependent claims.
The present invention is based on the idea of providing a circuit arrangement, in particular a M[etal-]O[xide]S[emiconductor] analog switch or a MOS analog multiplexer and/or a MOS analog demultiplexer, the circuit arrangement having at least one injection current effect control, wherein said injection current effect control is in particular based
Thus, the present invention proposes a circuit arrangement, in particular an analog switch scheme, which can handle the unwanted signal, in particular
The transistor means can be implemented as at least one metal-oxide semiconductor (MOS), in particularly as at least one complementary metal-oxide semiconductor (CMOS), for example as at least one complementary high-density metal-oxide semiconductor (CHMOS) and/or as at least one bipolar complementary metal-oxide semiconductor (BiCMOS).
Thus, according to a preferred embodiment of the present invention the transistor means comprises at least one p-type transistor unit, in particular at least one p-channel metal-oxide semiconductor (PMOS) or p-type metal-oxide semiconductor field effect transistor (PMOSFET), starting to conduct in case of at least one negative voltage being placed on its gate electrode.
Moreover, the transistor means advantageously comprises at least one n-type transistor unit, in particular at least one n-channel metal-oxide semiconductor (NMOS) or n-type metal-oxide semiconductor field effect transistor (NMOSFET), starting to conduct in case of at least one positive voltage being placed on its gate electrode.
Preventing the transistor means from starting to conduct due to being provided with at least one unwanted signal in its disabled state can for example be implemented
The enabling and disabling of the transistor means, in particular of the PMOS and/or of the NMOS, can be performed by means of at least one enable signal and/or by means of at least one disable signal.
According to a preferred embodiment of the present invention, the unwanted signal handling capability, in particular the overvoltage handling capability and the undervoltage handling capability, is achieved by providing the state control circuit, in particular by providing
For preventing MOS channel formation, the signal level circuit is preferably designed for controlling the signal level of at least one electrode of the transistor means, in particular
Moreover, for preventing the unwanted signal from being transmitted to at least one power supply, the state control circuit advantageously comprises at least one backflow-prevention circuit.
For achieving the unwanted signal handling capability according to a preferred embodiment of the present invention, the current control circuit is designed for ensuring at least one current sinking capability on the first part, such as on at least one analog input line, of the conductive channel, and/or on the second part, such as on at least one analog output line, of the conductive channel, to kill the leakage due to the parasitic bipolar effect.
For this reason, the current control circuit advantageously comprises
Thus, the current control circuit is advantageously designed as at least one built-in current-source/current-sink capability, which allows overvoltage and undervoltage, for example in excess of supply rail, on each side of the transistor means without disturbing the other side of the transistor means in the disabled state.
Moreover, for protecting the transistor means against at least one parasitic bipolar effect, in particular for preventing the transistor means from signal leakage due to said parasitic bipolar effect, the circuit arrangement preferably comprises at least one bipolar control circuit.
For preventing at least one current from being injected into at least one backgate of the transistor means, in particular from being injected into at least one parasitic bipolar transistor being formed by at least one source-drain-backgate of the transistor means, for example by at least one emitter-collector-base of the transistor means, the bipolar control circuit advantageously comprises at least one backflow-prevention circuit.
For controlling, in particular for dynamically controlling, the voltage level of the backgate of the transistor means, in particular for rising and/or for lowering the voltage level of said backgate of the transistor means, in dependence on the voltage level of the first pin and/or of the second pin and/or of the power supply, the bipolar control circuit preferably comprises at least one backgate control circuit.
Independently thereof or in combination therewith the circuit arrangement is preferably fully static, which makes it usable in advanced low power applications.
According to a preferred embodiment of the present invention the circuit arrangement is implemented as a low voltage analog switch structure, preferably being in compliance with conventional industrial switches, for example with the 4066 switch (cf. http://www.standardics.philips.com/products/hc/pdf/74hc_hct4066.pdf).
Moreover, the circuit arrangement according to the present invention can be implemented as at least one analog multiplexer (Mux) and/or as at least one analog demultiplier (DeMux).
According to a preferred embodiment of the present invention the circuit arrangement comprises the injection-current effect control as described above and is implemented for example in an N-well with 0.35 micrometer complementary metal-oxide semiconductor (CMOS) process with operating voltage of about 1.65 Volt to about 3.6 Volt. However, the present invention can also be used in P-well processes or in BiCMOS processes.
The circuit arrangement according to the present invention is advantageously used for applications such as automotive, where voltages in excess of normal supply voltages are common.
In the enabled state, the circuit arrangement, in particular the transistor means, can transfer the analog and/or digital signal in the range of ground level (vanishing voltage) to supply voltage across its conductive channel.
In the disabled state, the circuit arrangement, in particular the transistor means, blocks the transmitting of the analog and/or digital signal across its conductive channel.
The present invention leads to the advantage that current-injection effect control can be realized.
Moreover, the problem or disadvantage of rail-to-rail voltage limitations of a conventional CMOS switch can be overcome in a static way by the present invention.
Further benefits of a preferred embodiment of the present invention are:
The circuit arrangement according to the present invention is preferably qualified in accordance with the stress test qualification AEC-Q100 (Q1) for integrated circuits of A[utomotive]E[lectronics]C[ouncil].
A first level analysis indicates that a preferred embodiment of the circuit arrangement according to the present invention is four times smaller in terms of area than conventional circuit arrangements comprising a circuit for preventing the parasitic bipolar effect. Thus, the circuit arrangement according to the present invention can be produced at cheaper cost.
Finally, the present invention relates to the use of at least one circuit arrangement as described above and/or of the method as described above
In this context the circuit arrangement can be implemented as at least one switching device, in particular as at least one analog switch, and/or as at least one multiplexing device (Mux) and/or as at least one demultiplexing device (DeMux), for example as at least one analog multiplexer and/or as at least one analog demultiplexer.
As already discussed above, there are several options to embody as well as to improve the teaching of the present invention in an advantageous manner. To this aim, reference is made to the claims respectively dependent on claim 1 and on claim 6; further improvements, features and advantages of the present invention are explained below in more detail with reference to three preferred embodiments by way of example and to the accompanying drawings where
The same reference numerals are used for corresponding parts in
In order to avoid unnecessary repetitions, the following description regarding the embodiments, characteristics and advantages of the present invention relates (unless stated otherwise)
In
This analogue switch comprises a switching unit being designed as transistor means 20, namely as a metal-oxide semiconductor (MOS), in particular as a complementary metal-oxide semiconductor (CMOS).
Said CMOS 20 comprises
The CMOS 20, in particular the transistors of the CMOS 20, i.e. the PMOS transistor MP and the NMOS transistor MN, are switchable between the enabled state or enabled mode and the disabled state or disabled mode by being provided with enable signals EN. Preferably, only one of the PMOS transistor(s) MP and/or of the NMOS transistor(s) MN is enabled or switched on at any time.
In the enabled state or enabled mode, the CMOS 20, in particular the enabled transistor unit of the CMOS 20, for example the enabled PMOS or the enabled NMOS, can pass analog and/or digital signals in the range of its power supply Vcc across a first part 12 of a conductive channel, namely from an input line, to a second part 14 of the conductive channel, namely to an output line.
In the disabled state or disabled mode, the CMOS 20, in particular the disabled transistor unit of the CMOS 20, for example the disabled PMOS or the disabled NMOS, blocks the analog and/or digital signals from being transmitted from the input line 12 to the output line 14, to which aim the CMOS 20 is arranged between said input line 12 and said output line 14.
However, it has to be taken into account that in many applications, like for instance in automotive applications, the analogue switch 100 can be subjected to one or more unwanted signals, such as excessive current and/or excessive voltage, especially in the disabled state of the CMOS 20 or in the so-called off-state of the CMOS 20.
In contrast to conventional switches, the CMOS 20 of the present invention is capable of blocking such unwanted signal from being transmitted from the disturbed side of the CMOS 20, i.e. from the first part 12 or the second part 14 of the conductive channel being provided with the unwanted signal, to the undisturbed side of the CMOS 20, i.e. to the other part 14 or 12 of the conductive channel.
To ensure minimal disturbance due to the unwanted signal on the conductive channel 12, 14, the MOS effect, in particular the CMOS effect, and the bipolar effect are prevented in the circuit arrangement 100 in the disabled state of the CMOS 20, in particular in the disabled state of the PMOS and/or in the disabled state of the NMOS.
Therefor, the analogue switch 100 comprises three main circuit blocks as shown in
In
The dualovervoltage block 30 is designed for preventing the CMOS effect, namely for preventing leakage due to conductive channel formation between a first pin [-->reference numeral pin1], said first pin being assigned to the input line 12 of the conductive channel, and a second pin [-->reference numeral pin2], said second pin being assigned to the output line 14 of the conductive channel, in the disabled state or disabled mode of the CMOS 20, in particular in the disabled state or disabled mode of the PMOS and/or of the NMOS.
In
For preventing the PMOS of the switching unit 20 from starting to conduct in the disabled state or disabled mode, after detecting the overvoltage signal the signal level of at least one electrode of the PMOS is controlled, more particularly the signal level of at least one gate electrode [-->reference numeral gatep] of the PMOS is raised.
Thus, at least one inverter [-->reference numeral Inv_0 in
Said high voltage signal for preventing the PMOS [-->reference numeral MP0 in
The state control circuit or dualovervoltage block 30 comprises
When the overvoltage signal occurs on any of the lines 12, 14 of the conductive channel, the signal level circuit or Max-finder circuit block 34 Is activated and raises the signal level at the gate [-->reference numeral gatep in
The backflow-prevention circuit 32 prevents the flow of current from the first pin or second pin [-->reference numeral pin1 or reference numeral pin2] and/or from the conductive channel line 12, 14 being provided with the overvoltage to the power supply Vcc of the transistor means 20, wherein said backflow is prevented via the further PMOS transistor [-->reference numeral MP4 in
In this way, the gate electrode [-->reference numeral gatep] of the PMOS of the switching unit 20 is dynamically raised to the maximum voltage level, and no conductive channel is formed between the input line 12 and the output line 14. Thus, the leakage from one side of the switching unit 20 to the other side of the switching unit 20, due to CMOS effect, is prevented.
In
The state control circuit or dualovervoltage circuit 30 depicted in
For protecting the switching unit 20 from the parasitic bipolar effect the voltage level of a backgate [-->reference numeral bg in
More particularly, to prevent the parasitic bipolar effect, the current injected into the base-emitter (drain-backgate) junction of this bipolar transistor is to be avoided. This is achieved by raising the backgate voltage of the PMOS-switch to the maximum of the first pin [-->reference numeral pin1], of the second pin [-->reference numeral pin2], and of the supply voltage [-->reference numeral Vcc].
In this way, there is no forward bias across the base-emitter region of the bipolar, and consequently there is no leakage between the emitter and the collector of the parasitic bipolar (drain and source of the MOS).
Moreover, as depicted in
In
This current control circuit 52, 54 is designed for preventing that one or more unwanted current peaks are transmitted from the input line 12 of the conductive channel to the output line 14 of the conductive channel.
This current control circuit 52, 54 comprises
Thus, a source-sink block 52, 54 is attached to each side of the switching unit 20.
As stated above with reference to
In contrast thereto, the current control circuit 52, 54 is designed for preventing the conductive channel 12, 14 from disturbance due to unwanted current spikes being provided by a current source or by means of a high impedance source.
To prevent these current spikes from building very high voltage on the conductive channel 12, 14 and to prevent circuits connected to the conductive channel 12, 14 from breakdown under such stress, the current control circuit 52, 54 sources or sinks the current corresponding to these spikes from the conductive channel 12, 14.
For preventing the transmission of the unwanted current peak(s), the current control circuit 52, 54 senses the unwanted current peak(s) by means of at least one sensor means, in particular by means of at least one sensing transistor unit, for example by means of at least one further PMOS [-->reference numeral MP1 in
The size of this sensing transistor unit [-->reference numeral MP1 in
Moreover, for preventing the transmission of the unwanted current peak, the current control circuit 52, 54 provides at least one low impedance path for the current peak to the power supply Vcc and/or to the grounding gnd.
More particularly, the current control circuit 52, 54 dynamically senses the overvoltage and/or the undesired current signal on the conductive channel 12, 14 and offers the low impedance path for this current to the power supply Vcc and/or to the grounding gnd of the analog switch 100 via the PMOS transistor unit [-->reference numeral MP0 in
In this way, the current control circuit 52, 54 maintains the voltage of the lines 1214 of the conductive channel within tolerable limits.
In an undesired current mode, the overvoltage protection circuit blocks, i.e.
Thereby, the dualovervoltage block 30 as well as the BG_logic block 40 reduce the requirement on the size of the sensing transistor unit [-->reference numeral MP1 in
The working of the current control circuit 52, 54 can be understood as follows: The sensing transistor unit [-->reference numeral MP1 in
This conduction of the sensing transistor unit [-->reference numeral MP1 in
The voltage signal V1 is fed to the gate of one or more NMOS transistor units [-->reference numeral MN1 in
The NMOS transistor [-->reference numeral MN1 in
The first embodiment of the circuit arrangement in the form of the analogue switch 100 according to the present invention as depicted in
An advantageous operating range for the first embodiment of the analogue switch 100 (cf.
In
In the disabled state or disabled mode, the current is forced into one side of a switching unit 20′, in particular of an overvoltage switch, and the effect of this current is measured on the other side of the overvoltage switch 20′.
In the simulation setup as depicted in
The current forced into the first pin [-->reference numeral pin1] was varied from zero to three Milliampere. As depicted in
With reference to
In
The simulation set up for the overvoltage protection is shown in
The voltage on line Y is varied from about 3.2 Volt to about four Volt, and the current going into the first pin [-->reference numeral pin1] as well as the current coming out of the second pin [-->reference numeral pin2] is measured under different process conditions, namely slow, typical and fast, as well as under different temperature conditions.
In
It can be taken from
The maximum disturbance on line Z can be observed by measuring the current coming out of the second pin [-->reference numeral pin2] through the external resistance Rext of four Kiloohm.
The current deriving from a resistor R_1 being assigned to the second sink-source circuit 54′ is designated with reference numeral I(R_1) in
The current out of the second pin [-->reference numeral pin2] can be seen to be in the range between about ten Nanoampere and about twenty Nanoampere. The current into the first pin [-->reference numeral pin1] can be seen to increase as voltage on line Y increases. The current into the first pin [-->reference numeral pin1] gets saturated depending on the current sinking capabilities of the source-sink circuit block 52′, 54′.
With reference to
The simulation results of the circuit arrangement 100′ (cf.
According to a preferred embodiment, the circuit arrangement 100, 100′, 100″, in particular the state control circuit 30, the bipolar control circuit 40, and the current control circuit 52, 54 can be completely static and can conduct current only when required. In this way, normal operation of the circuit arrangement 100, 100′, 100″, in particular of the analogue switch, is still maintained and the circuit arrangement 100, 100′, 100″ remains completely static.
Because of its static design, the circuit arrangement 100, 100′, 100″ can be used in low power applications. Also, it is designed using a general CMOS process; thus, the circuit arrangement 100, 100′, 100″ can be easily produced at very low price.
The circuit arrangement 100, 100′, 100″ according to the present invention leads to the advantage of eliminating the need for external resistance or diode network to keep the analog signal range within the range of the supply voltage Vcc. This feature is especially useful in automotive applications.
In conclusion, a preferred embodiment of the present invention can be implemented as a schematic of a compensated switch for allowing signals on the input line 12 of the conductive channel and on the output line 14 of the conductive channel (cf.
The main advantages of this design are as follows:
Spice simulations under various process conditions as well as under various temperature conditions prove the concept. Simulation results are shown for overvoltage conditions (line voltage higher than supply voltage Vcc) but the analysis can easily be derived for for undervoltage signals (line voltage lower than ground potential gnd).
Number | Date | Country | Kind |
---|---|---|---|
06110635.7 | Mar 2006 | EP | regional |
PCT/IB2007/050468 | Feb 2007 | IB | international |
Filing Document | Filing Date | Country | Kind | 371c Date |
---|---|---|---|---|
PCT/IB07/50468 | 2/13/2007 | WO | 00 | 9/3/2008 |