Patent Grant
9693068
The present invention relates principally to the technical field of optical and/or electrical, in particular serialised, signal links; more particularly, the present invention relates to a circuit arrangement and to a method for coding and/or decoding a data stream, in particular of up to 24-bit-wide R[ed]G[reen]B[lue] video signals.
Displays in mobile phones, in notebooks or in portable game consoles, are controlled among others by a parallel data bus, which receives the information via the colour bits and the necessary synchronisation bits. If this data is transmitted in parallel, this parallel data transmission requires a broad flat ribbon cable or a relatively large amount of space on a printed circuit board, thereby preventing such devices from being minituarised any further.
There exist method for serialising this parallel data and then deserialise it, but only a few of these conventional methods are suitable for a D[irect]C[urrent]-balanced data transmission.
Methods which guarantee such a DC-balanced data transmission, have a big surplus of serial bits to be additionally transmitted due to the coding and decoding method used. For if this data is serialised and deserialised, a large amount of additional bits is either additionally transmitted due to the conventionally used coding and decoding methods, or more than one differential line is required for transmitting the data and the associated clock signal, whereby the aim of minitiarising such devices is again thwarted.
In order to receive a DC-balanced signal coding and decoding methods with different bit widths are employed. The most well known coding/deconding method is 8b/10b coding/decoding (8b=eight bit, 10b=ten bit). In most cases such 8b/10b coding/decoding comprises
The basis used for such 5b/6b blocks and 3b/4b blocks is usually the instructions and the table of Albert X. Widmer (IBM Research Division). As regards the asppropriate technological background of the present invention reference can be made to the prior art publication U.S. Pat. No. 6,911,921 B2.
Starting from the above-explained disadvantages and inadequacies as well as taking the outlined prior art into account the object of the present invention is to further develop a circuit arrangement of the above-mentioned type and a method of the above-mentioned type in such way that an efficient DC-balanced coding and/or decoding is possible, in particular with the lowest possible overheads.
This object is achieved by a circuit arrangement according to the invention with the herein described features and by a method according to the invention with the herein described features, in particular by the coding and/or decoding, for example of 24 Bit-R[ed]G[reen]B[lue] video signals, using 27 Bit/32 Bit coding/decoding, by means of which it is possible to code and/or to decode the data to be transmitted in such way that only very few additional bits are incurred for a DC-balanced serial optical and/or electrical data connection or transmission; data overheads incurred are therefore very small.
Advantageous embodiments and expedient further developments of the present invention are described above and below.
This object is achieved by a circuit arrangement provided for coding and/or decoding a data stream, in particular of up to 24-bit-wide R[ed]G[reen]B[lue] video signals, comprising
This object is further achieved by an embodiment of the circuit arrangement according to the invention,
This object is further achieved by an embodiment of the circuit arrangement according to the invention,
This object is further achieved by an embodiment of the circuit arrangement according to the invention, wherein the disparity information D_in, when passing each of the 5b/6b coder blocks and when passing the 2b/2b coder block, remains unchanged (D_out=D_in) or is inverted (D_in=0→D_out=1 or D_in=1→D_out=0) depending on the D[irect]C[urrent]-balancing of the data signal going out from the respective 5b/6b coder block and from the 2b/2b coder block.
This object is further achieved by an embodiment of the circuit arrangement according to the invention,
This object is further achieved by an embodiment of the circuit arrangement according to the invention, wherein the disparity information D_in when passing each of the 6b/5b decoder blocks and when passing the 2b/2b decoder block remains unchanged (D_out=D_in) or is inverted (D_in=0→D_out=1 order D_in=1→D_out=0) depending on the D[irect]C[urrent]-balancing of the data signal arriving in the respective 6b/5b decoder block and in the 2b/2b decoder block.
This object is further achieved by an embodiment of the circuit arrangement according to the invention, wherein of four possible input signals 00, 01, 10, 11, three input signals can be used, in particular as a DC-balanced signal, for the data input of the 2b/2b coder block or of the 2b/2b decoder block utilising the disparity information D_in, D_out.
This object is further achieved by an embodiment of the circuit arrangement according to the invention, wherein the data input of the 2b/2b coder block or the 2b/2b decoder block can be acted upon by
This object is further achieved by an embodiment of the circuit arrangement according to the invention,
This object is achieved by a method for coding and/or decoding a data stream, in particular of up to 24-bit-wide R[ed]G[reen]B[lue] videosignals, said method comprising:
This object is further achieved by an embodiment of the method according to the invention,
This object is further achieved by an embodiment of the method according to the invention, wherein of four possible input signals 00, 01, 10, 11, three input signals are used, in particular as a DC-balanced signal, for the data input of the 2b/2b coder block or of the 2b/2b decoder block utilising the disparity information D_in, D_out.
This object is further achieved by an embodiment of the method according to the invention, wherein the data input of the 2b/2b coder block or the 2b/2b decoder block is acted upon
This object is further achieved by an embodiment of the method according to the invention,
This object is further achieved by a use of the circuit arrangement and/or of the method according to the invention for the serialised optical and/or electrical signal transmission between at least one up to 24-bit-wide digital R[ed]G[reen]B[lue] data source, in particular at least one, for example high-resolution camera and/or a camera acting as an image source, or at least one application processor, and at least one up to 24-bit-wide digital R[ed]G[reen]B[lue] data sink, in particular at least one application processor or at least one, for example high-resolution display or monitor and/or a display or monitor acting for example as an image sink.
By means of the present invention it is possible, on the one hand, to produce a 32 bit long data word which is suitable for DC-balanced serial data transmission, and on the other, to decode a 32 Bit long data word into an error-free 27 Bit wide data word.
According to the invention this is accomplished using
The data stream generated by means of 5b/6b-coding has an overhead of twenty percent relative to the original data stream, which, however, is progress in comparison to the also commonly used 4b/5b coding insofar as with 4b/5b coding the gross data rate relative to the net or usable data rate (so-called pay load) is raised by 25 percent due to the data overhead.
The 2b/2b coder block and 2b/2b decoder block also used according to the invention ensure under usage of the disparity information that of four possible input information (i.e. 00, 01, 10, 11) three can be used for generating a DC-balanced signal.
This usage of three out of four possible input signals is conveniently possible, if the D[ata]E[nable] signal and the H[orizontal]S[ynchronisation] signal are connected to the two data inputs, wherein reference may be made to the methodology according to VESA-Standard; see http://www.vesa.org/
The present invention provides a possibility to reduce the number of coded bits to be transmitted and which have been serialised by means of at least one multiplexing downstream of this coding, without reducing the transmitted usable data quantity; this again results in the required gross data transmission rate being reduced, which in turn results in a reduced power consumption of a serial data transmission.
As an example the present invention can be used in bundled or serialised optical and/or electrical signal transmission between at least one up to 24-bit-wide digital R[ed]G[reen]B[lue] data source, in particular at least one, for example, high-resolution camera acting for example as an image source, or at least one application processor, and at least one up to 24-bit-wide digital R[ed]G[reen]B[lue] data sink, in particular at least one application processor or at least one, for example high-resolution display or monitor acting for example as an image sink.
In principle it is possible, to realise and to operate the signal link
As already discussed above, there are various possibilities for embodying and further developing the teaching of the present invention in an advantageous manner. For this purpose, on the one hand reference is made to the explanations above and to the dependent claims, and on the other hand further embodiments, features and advantages of the present invention are explained in greater detail below, inter alia by way of the exemplary embodiments illustrated by
It is shown in:
Like or similar embodiments, elements or features are provided with identical reference numerals in
By means of the circuit arrangement 100 shown in
To this end the circuit arrangement 100 comprises
By means of the coder 10 it is possible to generate a data stream comprising a sequence of a random amount of 32-bit-long data words, which is suitable for a DC balanced serialised data transmission between the coder 10 and the decoder 60. Serialisation is realised by means a 32-to-1 multiplexer 40 (so-called Mux), which is arranged downstream of the coder 10 and ensures that the data stream can be output in a serial sequence.
To effect the coding each of the five 5b/6b coder blocks 20 can pick up five-bit-wide digital signals at its data input 22 and convert them into six bit wide signals which are output by the respective data output 24 (the reference numerals 22, 24 in
Further each of the 5b/6b coder blocks 20 comprises a disparity input 26 for the incoming disparity information D_in and a disparity output 28 for the outgoing disparity information D_out because—in addition to the data—also the disparity is processed (the reference numerals 26, 28 in
For this 5b/6b conversion, as an example, the coding table shown in
Of the 32 5-bit input words A B C D E to be transmitted a part is converted into 6-bit output symbols a b c d e i, which contain an identical number of zeros and ones, i.e. respectively three zeros and three ones and consequently are denoted as balanced or D[irect]C[urrent] balanced or D[irect]C[urrent] neutral, and can thus be transmitted as DC-neutral. As such, as an example according to the coding table in
The remaining part of the 32 5-bit input words A B C D E to be transmitted is converted into 6-bit output symbols, which do not contain an identical number of zeros and ones, but
Therefore, as an example according to the coding table in
A 2b/2b coder block 30 is connected in parallel to the five 5b/6b coder blocks 20, which also comprises a data input 32 and a data output 34. Further, the 2b/2b coder block 30 comprises a disparity input 36 for the incoming disparity information D_in and a disparity output 38 for the outgoing disparity information D_out because—in addition to the data—also the disparity is processed.
This 2b/2b conversion may be for example accomplished using the coding table shown in
As such, in
Of the four 2-bit input words A B, a part is converted into 2-bit output symbols a b, which contain an identical number of zeros and ones, i.e. respectively one zero and one, and consequently are denoted as balanced or D[irect]C[urrent]-balanced or D[irect]C[urrent]-neutral, i.e. can be DC-neutrally transmitted. As such, according to the exemplary coding table in
Of the remaining part of the 2-bit input words A B, according to the coding table in
As such, according to the coding table in
The fourth (=in the embodiment of
The restriction to three out of the four possible input signals 0 0, 0 1, 1 0, 1 1 at the input of the 2b/2b coder block 30 is advantageously possible in particular when the D[ata]E[nable] signal and the H[orizontal]S[ynchronisation] signal are connected to the two data inputs 32 and data outputs 34, for these two signals can be communicated without temporal coincidence.
The decision,
For this purpose, during the transmission of sequential unbalanced output symbols, respectively one symbol from the one group (=with a surplus of two zeros, i.e. with two zeros and four ones in the case of an unbalanced 6-bit output symbol a b c d e i or with two zeros and no ones in the case of an unbalanced 2-bit output symbol a b) followed by a symbol from the other group (=with a surplus of two ones, i.e. with two zeros and four ones in the case of an unbalanced 6-bit output symbol a b c d e i or with no zeros and two ones in the case of an unbalanced 2-bit output symbol a b) is alternately transmitted. In this way, when averaged over time, a balanced bit sequence consisting of zeros and ones and therefore a DC-free transmission occurs.
Each of the 5b/6b coder blocks 20 as well as the 2b/2b coder block 30 of the coder 10 is notified via the respective disparity input 26 or 36 by way of the incoming disparity information D_in, whether the output symbol a b, if it is not DC-balanced, shall comprise
In such a case of outputting a not DC-balanced output symbol the state of the disparity information configured as a binary signal (=0 or 1) is inverted, i.e.
Thereby it is determined which disparity the following or next unbalanced outputted symbol shall comprise, wherein the disparity information,
Therefore, if an unbalanced output symbol has negative parity, i.e. two zeros more than ones, i.e.
If, on the other hand, an unbalanced output symbol has positive parity, i.e. two ones more than zeros, i.e.
If finally the output symbol has neutral disparity, i.e. the output symbol is DC-balanced, the so disparity information coming from the previous output symbol is forwarded unchanged to the next coding block 20 or 30, which depending on whether its output symbol is balanced or unbalanced, leaves the state of the disparity information again unchanged or inverts it.
The choice, whether the primary output word or the alternate output word is output in the exemplary coding tables of
Using this approach it is ensured that DC-freedom is achieved across a sufficiently large quantity of output symbols.
Any number of balanced output symbols can be present between two unbalanced output symbols, for example no symbol, one symbol, several or many balanced output symbols between two unbalanced output symbols.
The construction and the function of the decoder 60 are essentially mirror images of the above described construction and function of the coder 10:
By means of the decoder 60 decoding of the DC-balanced data stream provided by the coder 10 can be realised in a 27-bit-wide error-free data stream.
After the data stream coming from the coder 10 and serialised by means of the multiplexer 40 is again deserialised initially by means of a 1-to-32 demultiplexer 50 (so-called demux) upstream of the decoder 60 into a width of 32 Bit, each of the five 6b/5b decoder blocks 70 can pick up 6-bit-wide digital signals through its data input 72 for decoding and convert them into a 5-bit-wide digital word, which is output via the respective data output 74 (in
Further, each of the five 6b/5b decoder blocks 70 comprises a disparity input 76 for the incoming disparity information D_in and a disparity output 78 for the outgoing disparity information D_out because—in addition to the data—also the disparity is processed (in
A 2b/2b decoder block 80 is connected in parallel to the five 6b/5b decoder blocks 70, which also comprises a data input 82 and a data output 84. Further the 2b/2b decoder block 80 comprises a disparity input 86 for the incoming disparity information D_in and a disparity output 88 for the outgoing disparity information D_out because—in addition to the data—also the disparity is processed.
As regards the decoding side (shown in the right half of
While this invention has been described as having a preferred design, it is understood that it is capable of further modifications, and uses and/or adaptations of the invention and following in general the principle of the invention and including such departures from the present disclosure as come within the known or customary practice in the art to which the invention pertains, and as may be applied to the central features hereinbefore set forth, and fall within the scope of the invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10 2011 052 766 | Aug 2011 | DE | national |
This application is a continuation of international (WO) patent application no. PCT/DE2012/200056, filed 16 Aug. 2012, which claims the priority of German (DE) patent application no. 10 2011 052 766.4, filed 16 Aug. 2011, the contents of each being hereby incorporated herein by reference.
| Number | Name | Date | Kind |
|---|---|---|---|
| 4665517 | Widmer | May 1987 | A |
| 4759018 | Buchner | Jul 1988 | A |
| 5245339 | Cideciyan | Sep 1993 | A |
| 5387911 | Gleichert | Feb 1995 | A |
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| 7292161 | Widmer | Nov 2007 | B2 |
| 7359437 | Hwang | Apr 2008 | B2 |
| 20030048851 | Hwang | Mar 2003 | A1 |
| 20040083419 | Chiba | Apr 2004 | A1 |
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| Entry |
|---|
| International Search Report; PCT/DE2012/200056; Mar. 4, 2013. |
| Number | Date | Country | |
|---|---|---|---|
| 20150049820 A1 | Feb 2015 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/DE2012/200056 | Aug 2012 | US |
| Child | 14181471 | US |
