Claims
- 1. In a circuit arrangement for causing acceptance or rejection of processing requests for an information-processing sequential logic system of a telecommunications switching system, which logic system has a limited call-handling capability with respect to its information-processing capacity, in which a traffic measuring device identifies the information-processing traffic load of the information-processing sequential logic system caused by processing requests, in which a rejection device serves for defense against such overloads is provided in which a critical limit value can be set based on the measuring of the identified information-processing traffic load, and in which different urgency degrees of different types of processing requests have different urgency values individually assigned thereto, the improvement comprising:
- means for comparing the individual urgency values to the critical limit value and producing an acceptance character when the urgency value is greater than the critical limit value, or for producing a rejection character if the urgency value is less than the critical limit and if addition of a residual acceptance value in a type associated residual acceptance value storage means produces an overflow; and
- means for accepting or rejecting the processing requests in response to the acceptance and rejection characters for processing by the sequential logic system so that processing requests having above-average urgency are taken into consideration with a certain priority over processing requests having below-average urgency with respect to their processing in the sequential logic system,
- said type associated residual acceptance value storage means storing said residual values representing a percentage of each type of each request to be rejected, and accumulating said residual values for each type of request in respective counter storage areas to reject the request when the counter storage area overflows and accept the request when there is no overflow.
- 2. The circuit arrangement of claim 1, wherein:
- said comparison means includes means for assigning an acceptance character when the urgency value is equal to or greater than the critical limit and assigning a rejection character when the urgency value is smaller than the critical limit value and said overflow results.
- 3. The circuit arrangement of claim 1, wherein:
- said comparison means comprises means for assigning an acceptance character to a processing request when the urgency value is greater than the critical limit and assigning a rejection character to the processing requests when the urgency value is equal to or less than the critical limit value and said overflow results.
Priority Claims (1)
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3529171 |
Aug 1985 |
DEX |
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Parent Case Info
This is a continuation of application Ser. No. 894,763, filed Aug. 8, 1986, now abandoned.
US Referenced Citations (8)
Foreign Referenced Citations (5)
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0104637 |
Apr 1984 |
EPX |
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Oct 1984 |
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56-90692 |
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Non-Patent Literature Citations (3)
Entry |
"Performance of a Monitor For a Real-Time Control System" Erna S. Hoover and Barry J. Eckhart, AFIPS Conference Proceedings, vol. 29, 1966, pp. 23-35. |
IBM Technical Disclosure Bulletin, vol. 25, No. 1 Jun., 1982, pp. 431-432. |
Telcom Report, vol. 4 (1981), Special Issue "EWSD"Digital Switching System. |
Continuations (1)
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894763 |
Aug 1986 |
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