Claims
- 1. A circuit arrangement for compensating for changes in pulse duration in a binary signal which are the consequence of parasitic reactances in a multi-stage signal path, comprising an input inverter (I1) having an input coupled to the output of said signal path and an output, a circuit (NA) comprising a copy of the multi-stage signal path having the same parasitic reactances as said multi-stage signal path and having an input coupled to the output of said input inverter (I1) and an output, and an output inverter (I1) having an input coupled to the output of said circuit (NA) and an output for providing a compensated signal.
- 2. A circuit arrangement as claimed in claim 1, characterized in that the signal path, its copy (NA), as well as the input and output inverters (I1, I1), are integrated on a single chip.
- 3. A circuit arrangement as claimed in claim 2, characterized in that the coupling between the input inverter (I1) and input of the circuit (NA) comprises a connection of the single chip, which is coupled to a reference potential via a capacitor (K1).
- 4. A circuit arrangement as claimed in claim 2 or 3, characterized in that the single chip comprises a switching network and in that one circuit (NA) is provided for each output of the switching network.
Priority Claims (1)
Number |
Date |
Country |
Kind |
3938459 |
Nov 1989 |
DEX |
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Parent Case Info
This is a continuation of application Ser. No. 07/614,334, filed Nov. 15, 1990 now abandoned.
US Referenced Citations (11)
Non-Patent Literature Citations (1)
Entry |
Steinbuch and Rupprecht: Nachirichtentechnik, Springer-Verlag Berlin/Heidelberg/New York, (1967), pp. 113-118. |
Continuations (1)
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Number |
Date |
Country |
Parent |
614334 |
Nov 1990 |
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