BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 shows a circuit arrangement with two semiconductor switches according to the prior art, each of which is connected to its own overvoltage protection circuit.
FIG. 2 shows a circuit arrangement with at least two semiconductor switches, having a central overvoltage protection arrangement for the semiconductor switches.
FIG. 3 shows a first exemplary embodiment of a voltage limiting unit of the overvoltage protection arrangement.
FIG. 4 shows a second exemplary embodiment of a voltage limiting unit of the overvoltage protection arrangement.
FIG. 5 shows a second exemplary embodiment of a circuit arrangement having a central overvoltage protection arrangement.
FIG. 6 shows a third exemplary embodiment of a circuit arrangement having a central overvoltage protection arrangement.
FIG. 7 shows a circuit arrangement with at least two semiconductor switches and a coupling circuit for electrically coupling the control terminals of at least two semiconductor switches.
FIG. 8 shows a circuit arrangement with at least two semi conductor switches, a coupling circuit and a central overvoltage protection arrangement.
DETAILED DESCRIPTION
In the figures, unless otherwise stated, the same reference numbers designate the same circuit components and signals with the same meaning.
FIG. 2 shows a first embodiment of a circuit arrangement according to the invention, having two semiconductor switches T1, Tn, each of which has a control terminal 11, 1n, a first load terminal 21, 2n and a second load terminal 31, 3n. The semiconductor switches T1, Tn in the example are realized as n-channel-MOSFETs, whose drain terminals form the first load terminals 21, 2n, whose source terminals form the second load terminals 31, 3n and whose gate terminals form the control terminals 11, 1n. The semiconductor switches T1, Tn in the example are connected as low-side switches.
To each of the control terminals 11, 1n of these semiconductor switches T1, Tn driver circuits DRV1, DRVn are connected, which serve to convert actuating signals IN1, INn, by which the semiconductor switches T1, Tn are to be made conducting or blocking, to suitable levels for actuating these semiconductor switches T1, Tn.
The two semiconductor switches T1, Tn can be actuated separately from each other via the actuating signals IN1, INn and thereby serve to actuate different loads, not shown in greater detail in FIG. 2, independently of each other. These loads are to be connected in series with the load paths of the semiconductor switches T1, Tn with these series circuits are to be connected between terminals for a power supply potential and a reference potential.
The two semiconductor switches T1, Tn and their driver circuits DRV1, DRVn are integrated in a manner not depicted in greater detail, preferably jointly in a semiconductor body or a semiconductor chip.
A common (i.e. shared) overvoltage protection circuit 60 is provided to protect the two semiconductor switches T1, Tn against overvoltage on their load sections. This overvoltage protection circuit 60 comprises a voltage limiting unit 70 with a first and a second terminal 71, 72, the first terminal 71 being connected to a central circuit node 80 and the second terminal 72 being connected to a terminal for a reference potential GND. This reference potential GND can be, in particular, the reference potential to which all voltages are referred in an application circuit in which the depicted circuit arrangement is employed. This reference potential GND can be, in particular, the ground potential.
The first terminal 71 of the voltage limiting unit is coupled via the central circuit node 80 to the first load terminals 21, 2n of the semiconductor switches T1, Tn. Between each of the first load terminals 21, 2n and the central circuit node 80 there is connected a current sensor 41, 4n. Each of these current sensors 41, 4n actuates a current source 51, 5n, which is connected to the control terminal 11, 1n of the respective semiconductor switch T1, Tn. These current sources 51, 5n in the example shown are connected between the first load terminals 21, 2n and the control terminals 11, 1n of the semiconductor switches T1, Tn and are thus energized by the potential at the first load terminals 21, 2n.
In a manner not shown in greater detail, it is also possible to connect the terminals 51, 5n of the current sources away from the control terminals 11, 1n to a different power supply potential than the load potentials of the first semiconductor switches 21, 2n, which must be chosen such that it is sufficient to actuate the semiconductor switches in conduction.
In the context of the present invention, “current source” describes a circuit arrangement that is controlled by one of the current sensors and furnishes a current to the control terminal of the respective semiconductor switch. This current source can also be realized, in a manner not specifically illustrated, as a switch that is controlled by the respective current sensor and whose load path is connected between a terminal for a power supply potential and the control terminal of the respective semiconductor switch.
Optionally, rectifiers D1, Dn are connected between the first load terminals 21, 2n and the current sensors 41, 4n. These rectifiers D1, Dn are realized in the example of FIG. 2 as diodes and during operating states where the semiconductor switches T1, Tn are actuated into conduction via the driver circuits DRV1, DRVn they prevent the charge of the gate electrodes of the MOSFETs T1, Tn from flowing away across their load section and they prevent a current from flowing away from the central circuit node 80 across the load paths of the semiconductor switches T1, Tn.
The functioning of the circuit arrangement depicted in FIG. 2 will now be explained by means of the first semiconductor switch T1 and its actuation circuit, which comprises the current sensor 41 and the current source 51. For this, let it first be assumed that the semiconductor switch T1 is actuated into blocking via the actuation signal IN1 and the driver circuit DRV1. If, during this process, the load potential at the first load terminal 21—for example, due to an inductive load connected to it—increases to a value that corresponds to the threshold voltage of the voltage limiting unit 70 plus the forward voltage of the diode D1, a current I41 will flow from the first load terminal 21 across the diode D1, the current sensor 41, and the voltage limiting unit 70 to reference potential GND. The current sensor 41 detects this current flow and actuates the current source 51, so that the latter delivers a current I51 to the control terminal 11 of the semiconductor switch T1. The semiconductor switch T1 is thereby biased into conduction so as to counteract any further rise in the load potential or, in case of an inductive load connected to the first load terminal 21, to commutate this inductive load away.
The overvoltage protection function explained above operates accordingly for the second semiconductor switch Tn, when a potential rises at the first load terminal 2n of this second semiconductor switch Tn. In this case, the current sensor 4n actuates the current source 5n hooked up to the control terminal 1n of this semiconductor switch Tn, thereby biasing the semiconductor switch Tn into conduction. The overvoltage protection function in this overvoltage protection circuit is also present when the load potentials at both semiconductor switches T1, Tn increase to values above the threshold voltage of the voltage limiting unit 70. In this case, currents flow from both first load terminals 21, 2n across the diodes D1, Dn and the current sensors 41, 4n as well as the voltage limiting unit 70 to reference potential GND. These currents are detected by the current sensors 41, 4n, which in turn actuate the current sources 51, 5n.
The circuit arrangement depicted in FIG. 2 contains two “channels”, each with a semiconductor switch. This circuit, of course, can be expanded to more than two semiconductor switches T1, Tn, as suggested in FIG. 2. Each “channel” added in addition to this circuit comprises a semiconductor switch with a driver circuit, as well as an actuating circuit, having a current sensor and a current source. The current sensor is connected, similarly to the current sensors 41, 4n presented in FIG. 2, between a first load terminal of this additional semiconductor switch and the central circuit node 80.
Referring to FIG. 2 the at least two semiconductor switches T1, Tn may be used for driving one common load Z. In this case, the load paths of the two switches T1, Tn are connected in parallel. The parallel circuit of the at least two switches is connected in series to the load Z, with the series circuit being connected between terminals for a first and a second supply potential V+, GND. The central overvoltage protection circuit 60 of the circuit arrangement improves current sharing between the at least two switches T1, Tn if an overvoltage occurs at the circuit node common to the load Z and the load paths of the semiconductor switches. In case of such overvoltage the overvoltage protection circuit 60 turns the switches T1, Tn connected in parallel into conduction, thereby distributing the overall current equally to the switches.
FIG. 3 shows one possible exemplary embodiment for the voltage limiting unit 70. The voltage limiting unit in this case has a series circuit with several Zener diodes 81, 82, 83, being connected between the first and second terminals 71, 72. The breakthrough voltage of this series circuit with several Zener diodes 81, 82, 83 determines the threshold voltage at which the voltage limiting unit 70 will conduct a current between the first and second terminal 71, 72.
FIG. 4 shows another exemplary embodiment of such a voltage limiting unit. The voltage limiting unit in this case has a series circuit of several Zener diodes 81, 82, 83 and a resistor 84 between the first and second terminals 71, 72. Connected in parallel with this series circuit is the load path of another semiconductor switch, in the example an n-channel MOSFET 85. This MOSFET 85 is actuated by a voltage V84 across the resistor 84 and is conducting when the voltage between the first and second terminals 71, 72 is larger than the breakthrough voltage of the Zener diode chain 81-83 plus the threshold voltage of the MOSFET 85. Since the threshold resistance of the MOSFET 85 is lower than the forward resistance of the Zener diode chain operating in the blocking direction, the MOSFET 85 takes up the main share of the current flowing between the first and second terminals 71, 72. The current load on the Zener diodes 81-83 is therefore less than the current load on the Zener diodes in a voltage limiting unit according to FIG. 3, so that in the voltage limiting unit according to FIG. 4 the Zener diodes 81-83 can be smaller in dimension that the corresponding Zener diodes in the circuit of FIG. 3. Despite the additional MOSFET 85, the voltage limiting unit of FIG. 4 is more space-saving. Furthermore, the clamping voltage of the voltage limiting unit 73 in FIG. 4 is less dependent on the currents I41, . . . , I4n flowing into the voltage limiting unit 73.
FIG. 5 shows an exemplary embodiment of a circuit according to the invention, in which a current sensor 41 and a current source 51 are jointly realized as current mirrors. The current sensor 41 in this case forms an input transistor of the current mirror, while the current source 51 forms an output transistor of this current mirror. A current I41 flowing through the input transistor 41 is mapped in this arrangement via the output transistor 51 onto a current I51 at the control terminal 11 of the semiconductor switch T1. The current mirror 41, 51 can be of such a dimension that the current I41 corresponds to the current I51. Moreover, it is possible to adjust the output current I51 of the current mirror through the surface ratio of the transistors 41, 51 forming the current mirror to a value proportional to the input current I41. The two current mirror transistors in the depicted example are configured as p-channel MOSFETs, of which the input transistor 41 is wired as a diode.
Another exemplary embodiment of the current sensors and the current sources is given in FIG. 6. In this exemplary embodiment, the current sensor 41 of an actuating circuit is realized as an ohmic resistor, which are connected between the first load terminal 21 of the respective semiconductor switch T1 and the central circuit node 80. A current I41 flowing across this resistor 41 in event of an overload causes a voltage drop V41 across this resistor, which serves to actuate a transistor 51, whose load is connected between the first load terminal 21 and the control terminal 11 of the respective semiconductor switch T1. The transistor 51, 5n in this circuit according to FIG. 6 functions as a current source and is configured in the example as a p-channel MOSFET.
Also a mixed solution comprising a current mirror and a resistor may be used as a current sensor. Referring to FIG. 5 resistors 411, 411n may be connected between the rectifier elements D1, Dn and the gate terminals of the current mirror output transistors 51, 5n. These resistors serve to increase the robustness of the current sensors.
In the exemplary embodiment of FIG. 6 the diodes D1, Dn are realized using the parasitic bulk—drain junction of a PMOS transistors. This permits an area saving since the diodes/rectifiers D1, Dn and the current sources 51, 5n can be placed into the same bulk.
The above-described overvoltage protection arrangement of the circuit according to the invention merely requires, for protection of the semiconductor switches, a voltage limiting unit realized by using one or more Zener diodes. This overvoltage protection arrangement has the benefit of being space-saving, given the need to provide only one voltage limiting unit. Furthermore, no problems caused by manufacturing variations can arise in this overvoltage protection arrangement.
Referring to FIG. 7 current sharing between at least two semiconductor switches T1, T2, Tn connected in parallel for driving a common load Z may be improved by providing a coupling circuit 90. The coupling circuit serves for electrically coupling the control terminals 11, 12, 1n of the semiconductor switches T1, T2, Tn connected in parallel. The circuit arrangement of FIG. 7 comprises three semiconductor switches T1, T2, Tn each of which having a control terminal 11, 12, 1n and first and second load terminals 21, 22, 2n, 31, 32, 3n. The coupling arrangement 90 comprises a number of switches 901, 90n with each of these switches 901, 90n being connected between control terminals 11, 12, 1n of two semiconductor switches T1, T2, Tn and with each control terminal 11, 12, 1n being connected to only one switch 901, 90n. For connecting the control terminals of n (with n being an integer) semiconductor switches T1, T2, Tn, n-1 switches of the coupling arrangement 90 are required.
The switches 901, 90n of the coupling circuit have control terminals 91, 9n for applying switching signals. The switching signals which serve for switching on or off the switches 901, 90n may be provided by a control circuit 101 which also provides the input signals IN1, IN2, INn of the semiconductor switches T1, T2, Tn. The control circuit 101 is provided a control signal P including information on the semiconductor switches T1, T2, Tn to be actuated together for driving one common load Z. Depending on this control signal P the control circuits generates the switching signals for selectively switching on the switches 91, 9n thereby connecting the control 11, 12, 1n terminals of at least two semiconductor switches T1, T2, Tn.
The coupling circuit 90 improves current sharing/balancing between the semiconductor switches T1, T2, Tn which have their control 11, 12, 1n terminals connected by causing the same electrical potential at the control terminals 11, 12, 1n and thereby causing the transistors to be operated in the same operation point. This applies to a normal operation mode, when the semiconductor switches are switched on by input signals IN1, In2, INn, as well to an overvoltage protection mode, when the semiconductor switches T1, T2, Tn are switched on by overvoltage protection circuits.
In FIG. 7 each of the semiconductor switch has its own overvoltage protection circuit D1, Z1, D2, Z2, Dn, Zn being connected between the first load terminal 21, 22, 2n and the control terminal 11, 12, 1n. These overvoltage protection circuits may each have a diode D1, D2, Dn and a Zener diode Z1, Z2, Zn connected in series. In overvoltage protection mode, i.e. if the semiconductor switches T1, T2, Tn are normally switched off, the maximum voltage at the circuit node common to load Z and to the load paths of the semiconductor switches T1, T2, Tn is governed by the overvoltage protection circuit having the lowest activation voltage. However, due to the interconnection between the control terminals 11, 12, 1n each of the the semiconductor switches T1, T2, Tn connected in parallel is activated, thereby limiting the voltage at the common node. In general the activation voltages of the overvoltage protection circuits should be identical. However, variations may occur due to process variations in the manufacturing process of the circuit.
It should be mentioned that the control terminals 11, 12, 1n of the semiconductor switches are connected only then, if the switches T1, T2, Tn are to operated in parallel for driving one common load. Each of the switches T1,T2, Tn may drive its own load as well (not depicted). In this case the control terminals 11, 12, 1n are not connected, i.e. the switches 901, 90n are open. The number of switches to be switched in parallel may be chosen dependent on the load to be driven.
Referring to FIG. 8 the central overvoltage protection circuit 60 and the coupling circuit 90 may be implemented together in one circuit. Referring to FIG. 8 the switches 901, 90n of the coupling circuit may be so-called “transfer gates” each having a p-transistor 911, 91n and a n-transistor 921, 92n having their load paths (drain-source-paths) connected in parallel. One of theses transistors (the n-transistor 921, 92n in FIG. 8) is controlled directly by the control signal present at the control terminal 91, 9n, while the other one of these transistors (the p-transistor 911, 91n in FIG. 8) is controlled by the control signal via an inverter 931, 93n.
In the circuit of FIG. 8 the maximum voltage at the circuit node common to the load paths of the semiconductor switches T1, T2, Tn is governed by the central overvoltage protection 60. If the semiconductor switches are turned into conduction by overvoltage protection circuit 60 the coupling circuit helps to improve current sharing/balancing between the semiconductor switches T1, T2, Tn by effecting identical electrical potentials at their control nodes 11, 12, 1n.
Patent Application
20080002324
