Patent Application
20100040127
The present invention relates to a circuit configuration for data combining, and more particularly, to a circuit configuration that reduces the buffer size and computation complexity for data combining.
In order to increase the reliability of a data burst transmission in wireless fading channels, a wide variety of diversity utilization schemes have been proposed to deal with fading channels. Time diversity, which can be achieved by transmitting multiple copies of data through time varying channels, is one of the most promising diversity utilization techniques for use in WiMAX systems. The time diversity scheme benefits from diversity gain generated by combining data received from a plurality of independent and uncorrelated channels.
Hybrid automatic repeat-request (HARQ) algorithm is a well-known scheme that applies time diversity: it uses a forward error correcting (FEC) code in conjunction with a retransmission scheme. When a received packet is found to have uncorrectable errors, the HARQ scheme may discard the received packet and request a retransmission (type I HARQ), or store the received packet, request a retransmission and combine the packets received in these two transmissions (type II HARQ).
In addition to the time diversity scheme, the spatial diversity scheme, such as the multi-input multi-output (MIMO) system, is also known for its higher link reliability. In the MIMO diversity system, a single stream is emitted from each of the transmitting antennas with space-time coding. By utilizing multiple antennas at both the transmitter and receiver, the MIMO diversity system can improve communication performance, allowing higher spectral efficiency and link reliability.
When designing a receiving end, however, the spatial diversity scheme and the time diversity scheme are always considered separately. Since there is no explicit research on how to integrate the spatial diversity with the time diversity in order to gain the most advantage from both, the receiving end is not capable of reaching a best overall performance.
One objective of the present invention is therefore to provide a circuit configuration that properly constructs circuits of different diversity schemes. The spatial data combining is performed at a symbol level while the time-diversity data combining (for example, the HARQ data combining or the repetition data combining) is performed at a bit level. The circuit configuration can reduce the buffer size and computation complexity required; the overall performance is therefore improved.
According to one exemplary embodiment of the present invention, an apparatus for re-generating data from at least one received signal is disclosed. The apparatus comprises at least one equalizer, a de-mapper, a level adjuster, and a combining circuit, wherein the equalizer equalizes a received signal to generate an equalized signal, and the de-mapper, coupled to the equalizer, is utilized to de-map the equalized signal to generate a set of values representing data embedded in the received signal. The output of the de-mapper is delivered to the level adjuster in order to generate an adjusting factor according to a noise level of the received signal, and adjust the set of values according to the adjusting factor to generate a set of adjusted values. The combining circuit, coupled to the level adjuster, then performs a data combining on the set of adjusted values to re-generate the data embedded in the received signal.
According to another exemplary embodiment of the present invention, a method of re-generating data from at least one received signal is disclosed. The method comprises equalizing at least one received signal to generate at least an equalized signal, de-mapping the equalized signal to generate a set of values representing data embedded in the received signal, generating an adjusting factor according to a noise level of the received signal, adjusting the set of values according to the adjusting factor to generate a set of adjusted values, and performing a data combining on the set of adjusted values to re-generate the data embedded in the received signal.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
Certain terms are used throughout the description and following claims to refer to particular components. As one skilled in the art will appreciate, manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following description and in the claims, the terms “include” and “comprise” are used in an open-ended fashion, and thus should be interpreted to mean “include, but not limited to . . . ”. Also, the term “couple” is intended to mean either an indirect or direct electrical connection. Accordingly, if one device is coupled to another device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.
In order to achieve a better overall performance, a circuit structure for data combining proposed herein includes a spatial data combining circuit operating at a symbol level and a time data combining circuit operating at a bit level; that is, the process of the spatial data combining takes a “symbol” as a unit, while the process of the time data combining takes a “bit” as a unit. Please refer to
In this embodiment, the equalizers 120a and 120b first respectively generate the required channel responses, and then respectively store the power of the channel state information (CSI) and the equalized signals into a buffer (not shown). Each buffer has a size sufficient to contain the information of a plurality of sub-carriers, and provides the equalized data to the level adjuster 110 for noise level estimation. After the noise level of each equalized signal has been estimated, a spatial adjusting factor generator 112 of the level adjuster 110 generates the adjusting factors according to the noise levels, and adjusts the equalized signals according to the adjusting factors in order to adjust the signal level. In this embodiment, the first equalized signal output from the equalizer 120a is multiplied by 1, and the second equalized signal output from the equalizer 120b is multiplied by a factor of
where σ12 represents the noise variance of the first equalized signal, and σ22 represents the noise variance of the second equalized signal. In this way, the summed signal can have a maximal signal-to-noise ratio (SNR). Note that the above-mentioned factors provided by the level adjuster 110 are for illustrative purposes only, and should not be taken as limitations of the present invention. For example, multiplying the first equalized signal by
and multiplying the second equalized signal by
can achieve substantially the same result.
As mentioned above, the summed signal is de-mapped by the de-mapper 130, and the soft bits (log likelihood ratio values) representing data embedded in the received signals are generated. The level adjuster 110 further adjusts the soft bits according to a noise level of the transmission; for example, the level adjuster 110 multiplies the soft bits by a reciprocal of the overall noise variance of the equalized signals. The meaning of this adjustment is to reflect potential of this transmission, and reduce the bit width of the decoder input. The reference sources for the level adjuster 110 to estimate the noise variance include an RF error vector magnitude (EVM) table, pilot bits and data bits of the received signals in this embodiment. The noise level estimated from the pilot bits can provide a high accuracy, the data bits can be used to derive the true noise level by a data noise estimator 114, and the RF EVM table can be an auxiliary choice if both noise levels estimated from the pilot bits and the data bits are not available.
Disposing the equalizers 120a, 120b, and the level adjuster 110 prior to the de-mapper 130 allows the receiving-end circuit structure 100 to be provided with the advantages of reduced buffer size and computation complexity. Taking a WiMAX system applying 64 QAM as an example, when the spatial data combining is performed at symbol level, the required buffer size in an equalizer is 1152 bits since there are 24 sub-carriers, and the buffer needs to store 3 words including the power of the CSI and the equalized signal for each sub-carrier, wherein each word has a length of 16 bits. If the spatial data combining is performed at bit level, however, the required buffer size in an equalizer will increase to 1728 bits since the buffer needs to store 6 words for 64 QAM for each sub-carrier, wherein each word has a length of 12 bits. Moreover, the symbol level spatial data combining needs fewer adders and multipliers than the bit level spatial data combining, which means that the circuit complexity and the computation complexity are decreased.
The soft bits after adjustment by the adjusting factor are sent to the combining circuit 140 so long as the soft bits have a repetition characteristic (that is, the FEC code has a repetition function). The combining circuit 140 performs a data combining that is able to cancel the repetition function on the adjusted soft bits to re-generate the data embedded in the received signal. More specifically, the adjusted soft bits are first quantized by a quantizer 142 of the combining circuit 140 since the precision required for de-repetition is not as high as that required for equalization and de-mapping. The quantizer 142 is an optional element, however. A slot of the FEC block of the adjusted soft bits is stored in a repetition buffer 144 to wait for the next repetition slot, and a computing unit 146 of the combining circuit 146 performs a de-repetition on the slot buffered in the repetition buffer 144 and the next slot. After all the combining is complete, the generated data is sent to the decoding circuit 150 to check its correctness.
In the decoding circuit 150, the adjusted soft bits received from the combining circuit 140 are quantized by a quantizer 152 and then stored in a buffer 154 to wait for decoding by a decoder 156. This is due to the adjusting factor of the level adjuster 110 that enables the bit width of the decoder 156 to be reduced. The decoding should be started when all the soft bits of the FEC block are stored in the buffer 154, and if the decoder 156 determines that the correctness of the soft bits is doubtful, the receiving end 100 may request a retransmission to the transmitter.
If the soft bits outputted from the de-mapper 130 do not have the repetition characteristic, however, (i.e. the FEC code does not have the repetition function), the soft bits after adjustment by the adjusting factor are sent to the decoding circuit 150 directly to check their correctness. Moreover, the combining circuit 140 can be utilized as an HARQ combining circuit, and the adjusted soft bits that fail to pass the correctness examination are buffered in the HARQ combining circuit 140 to wait for a retransmission.
The retransmission is controlled by the base station with an ARQ channel identification (ACID) and AI_SN fields in the downlink MAC and uplink MAC. Each HARQ channel indicated by a specific ACID is managed separately, and the retransmission can be recognized if the AI_SN field in the HARQ channel remains the same between two HARQ burst allocations. Therefore, when a retransmission signal is received, it is equalized, de-mapped and level adjusted as mentioned above, and the set of soft bits corresponding to the retransmission signal are sent to the HARQ combining circuit 140. The computing unit 146 then performs a combining (for example, the chase combining) on two transmissions to improve the performance of decoding. Note that the level adjustment that adjusts the soft bits corresponding to the retransmission signal according to an overall noise level of the retransmission makes the soft bits corresponding to the retransmission signal have a same SNR level as the soft bits stored in the HARQ buffer 144; that is, a different noise level added to each signal during transmission is equalized, and the potential of each transmission is reflected.
In another embodiment, as shown in
In the above embodiments, disposing the repetition combining and the HARQ chase combining at bit level helps the receiving end 100 further reduce the buffer size. Please refer to
However, as the packet size or the number of the retransmission increases, the bit-level chase combining may induce performance loss, and the packet error rate (PER) of symbol-level chase combining may become lower than that of bit-level chase combining. In order to simultaneously reach the advantages of reduced buffer size and good performance (e.g. low PER), the first computing unit 146 is modified to compensate for the performance loss: the first computing unit 146 generates a first bit of output data according to a first bit of the set of buffered values and a first bit of the set of values corresponding to the retransmission signal, and generates an nth bit of the output data according to an nth bit and an (n−1)th bit of the set of buffered values, an nth bit and an (n−1)th bit of the set of values corresponding to the retransmission signal, and an (n−1)th bit of the output data of the first computing unit 146, where n is an integer larger than 1. Please refer to
Y=HX+Z,
G=|H|
2
, F=H*Y=|H|
2
X+H*Z,
b
OLD[0]=R(FOLD), bOLD[1]=4GOLD−|R(FOLD)|, bOLD[2]=2GOLD−|bOLD[1]|,
b
NEW[0]=R(FNEW), bNEW[1]=4GNEW−|R(FNEW)|, bNEW[2]=2GNEW−|bNEW[1]|,
b[0]=bOLD[0]+bNEW[0],
b[1]=bOLD[1]+bNEW[1]+|bOLD[0]|+|bNEW[0]|−|b[0]|,
b[2]=bOLD[2]+bNEW[2]+|bOLD[1]|+|bNEW[1]|−|b[1]|.
By applying this rule to the first computing unit 146, the modified bit-level HARQ chase combining can achieve the same performance as the symbol-level HARQ chase combining. Therefore, the receiving end 100 can gain the most advantage from both the spatial diversity and time diverity schemes, and reach a best overall performance. Moreover, although the above embodiments use MIMO system to raise the link reliability, the receiving end may have only one antenna to receive signals in other embodiments. In this situation, there will be only one equalizer 120 and the weighting adjustment performed on the equalized signals of the equalizer 120a and 120b may not be necessary; in other words, the spatial adjusting factor generator 112 may only adjust the output of the de-mapper 130 according to the adjusting factor corresponding to the noise level of the received signal. As long as the spatial data combining is performed at a symbol level while the time-diversity data combining is performed at a bit level, the circuit structure still obeys the spirit of the present invention.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.
